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SiFive E300 Platform Reference Manual, Version 1.0.1
Index
Meaning
0
Power-on reset
1
External reset
2
Watchdog timer reset
Table 6.3: Reset cause values.
Memory Map
The memory map for the PMU is shown in Table 6.4. The memory map has been designed to only
require naturally aligned 32-bit memory accesses.
Address
Name
Description
0x100
pmuwakeupi0
Wakeup program instruction 0
0x104
pmuwakeupi1
Wakeup program instruction 1
0x108
pmuwakeupi2
Wakeup program instruction 2
0x10c
pmuwakeupi3
Wakeup program instruction 3
0x110
pmuwakeupi4
Wakeup program instruction 4
0x114
pmuwakeupi5
Wakeup program instruction 5
0x118
pmuwakeupi6
Wakeup program instruction 6
0x11c
pmuwakeupi7
Wakeup program instruction 7
0x120
pmusleepi0
Sleep program instruction 0
0x124
pmusleepi1
Sleep program instruction 1
0x128
pmusleepi2
Sleep program instruction 2
0x12c
pmusleepi3
Sleep program instruction 3
0x130
pmusleepi4
Sleep program instruction 4
0x134
pmusleepi5
Sleep program instruction 5
0x138
pmusleepi6
Sleep program instruction 6
0x13c
pmusleepi7
Sleep program instruction 7
0x140
pmuie
PMU interrupt enables
0x144
pmucause
PMU wakeup cause
0x148
pmusleep
Initiate sleep sequence
0x14c
pmukey
PMU key register
Table 6.4: SiFive PMU register offsets within AON memory map. Only naturally aligned 32-bit
memory accesses are supported.
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