SiFive FE310-G002, Manual

Page 1: ...SiFive FE310 G002 Manual v19p05 SiFive Inc ...

Page 2: ...s of mer chantability fitness for a particular purpose and non infringement SiFive does not assume any liability rising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation indirect incidental spe cial exemplary or consequential damages SiFive reserves the right to make changes without further notice to any products h...

Page 3: ...9 Pulse Width Modulation 12 1 10 I C 12 1 11 Debug Support 12 2 List of Abbreviations and Terms 13 3 E31 RISC V Core 15 3 1 Instruction Memory System 15 3 1 1 I Cache Reconfigurability 16 3 2 Instruction Fetch Unit 16 3 3 Execution Pipeline 16 3 4 Data Memory System 17 3 5 Atomic Memory Operations 17 3 6 Supported Modes 18 3 7 Physical Memory Protection PMP 18 3 7 1 Functional Description 18 3 7 2...

Page 4: ... 6 6 PLL Output Divider 30 6 7 Internal Programmable Low Frequency Ring Oscillator LFROSC 31 6 8 Alternate Low Frequency Clock LFALTCLK 32 6 9 Clock Summary 32 7 Power Modes 33 7 1 Run Mode 33 7 2 Wait Mode 33 7 3 Sleep Mode 33 8 Interrupts 35 8 1 Interrupt Concepts 35 8 2 Interrupt Operation 36 8 2 1 Interrupt Entry and Exit 36 8 3 Interrupt Control Status Registers 37 8 3 1 Machine Status Regist...

Page 5: ...s 48 10 7 Interrupt Claim Process 48 10 8 Interrupt Completion 49 11 Error Device 51 12 One Time Programmable Memory OTP Peripheral 52 12 1 Memory Map 52 12 2 Programmed I O lock register otp_lock 53 12 3 Programmed I O Sequencing 54 12 4 Read sequencer control register otp_rsctrl 54 12 5 OTP Programming Warnings 54 12 6 OTP Programming Procedure 55 13 Always On AON Domain 56 13 1 AON Power Source...

Page 6: ...4 14 7 Watchdog Configuration 64 14 8 Watchdog Resets 64 14 9 Watchdog Interrupts wdogip0 64 15 Power Management Unit PMU 65 15 1 PMU Overview 66 15 2 Memory Map 66 15 3 PMU Key Register pmukey 67 15 4 PMU Program 67 15 5 Initiate Sleep Sequence Register pmusleep 68 15 6 Wakeup Signal Conditioning 68 15 7 PMU Interrupt Enables pmuie and Wakeup Cause pmucause 69 16 Real Time Clock RTC 71 16 1 RTC C...

Page 7: ...ontrol Register rxctrl 81 18 8 Interrupt Registers ip and ie 82 18 9 Baud Rate Divisor Register div 82 19 Serial Peripheral Interface SPI 84 19 1 SPI Overview 84 19 2 SPI Instances in FE310 G002 84 19 3 Memory Map 85 19 4 Serial Clock Divisor Register sckdiv 86 19 5 Serial Clock Mode Register sckmode 87 19 6 Chip Select ID Register csid 87 19 7 Chip Select Default Register csdef 88 19 8 Chip Selec...

Page 8: ...0 9 Generating Left or Right Aligned PWM Waveforms 100 20 10 Generating Center Aligned Phase Correct PWM Waveforms 100 20 11 Generating Arbitrary PWM Waveforms using Ganging 101 20 12 Generating One Shot Waveforms 102 20 13 PWM Interrupts 102 21 Inter Integrated Circuit I C Master Interface 103 21 1 I C Instance in FE310 G002 103 22 Debug 104 22 1 Debug CSRs 104 22 1 1 Trace and Debug Register Sel...

Page 9: ... and Program Buffer 0x300 0x3FF 109 22 3 2 Debug ROM 0x800 0xFFF 109 22 3 3 Debug Flags 0x100 0x110 0x400 0x7FF 110 22 3 4 Safe Zero Address 110 23 Debug Interface 111 23 1 JTAG TAPC State Machine 111 23 2 Resetting JTAG Logic 112 23 3 JTAG Clocking 112 23 4 JTAG Standard Instructions 113 23 5 JTAG Debug Commands 113 24 References 114 7 ...

Page 10: ...0nm process This manual serves as an architec tural reference and integration guide for the FE310 G002 The FE310 G002 is compatible with all applicable RISC V standards and this document should be read together with the official RISC V user level privileged and external debug architecture specifications 1 1 FE310 G002 Overview Figure 1 shows the overall block diagram of the FE310 G002 A feature su...

Page 11: ...Figure 1 FE310 G002 top level block diagram Copyright 2019 SiFive Inc All rights reserved 9 ...

Page 12: ... comparators I C 0 Inter Integrated Circuit I C controller GPIO 32 General Purpose I O pins Always On Domain Supports low power operation and wakeup Table 1 FE310 G002 Feature Summary 1 2 E31 RISC V Core The FE310 G002 includes a 32 bit E31 RISC V core which has a high performance single issue in order execution pipeline with a peak sustainable execution rate of one instruction per clock cycle The...

Page 13: ...PIO Complex The GPIO complex manages the connection of digital I O pads to digital peripherals including SPI UART I C and PWM controllers as well as for regular programmed I O operations The GPIO complex is described in more detail in Chapter 17 1 7 Universal Asynchronous Receiver Transmitter Multiple universal asynchronous receiver transmitter UARTs are available and provide a means for serial co...

Page 14: ...escribed in Chapter 20 1 10 I C The FE310 G002 has an I C controller to communicate with external I C devices such as sen sors ADCs etc The I C is described in detail in Chapter 21 1 11 Debug Support The FE310 G002 provides external debugger support over an industry standard JTAG port including 8 hardware programmable breakpoints per hart Debug support is described in detail in Chapter 22 and the ...

Page 15: ...Chapter 2 List of Abbreviations and Terms 13 ...

Page 16: ...t standard originally developed at UC Berke ley RO Used to describe a Read Only register field RW Used to describe a Read Write register field WO Used to describe a Write Only registers field WARL Write Any Read Legal field A register field that can be written with any value but returns only supported values when read WIRI Writes Ignored Reads Ignore field A read only register field reserved for f...

Page 17: ...tem The instruction memory system consists of a dedicated 16 KiB 2 way set associative instruction cache The access latency of all blocks in the instruction memory system is one clock cycle The instruction cache is not kept coherent with the rest of the platform memory system Writes to instruction memory must be synchronized with the instruction fetch stream by executing a FENCE I instruction The ...

Page 18: ...are preserved between deallocation and allocation 3 2 Instruction Fetch Unit The E31 instruction fetch unit contains branch prediction hardware to improve performance of the processor core The branch predictor comprises a 28 entry branch target buffer BTB which predicts the target of taken branches a 512 entry branch history table BHT which predicts the direction of conditional branches and a 6 en...

Page 19: ...d branches and jumps incur a three cycle penalty Most CSR writes result in a pipeline flush with a five cycle penalty 3 4 Data Memory System The E31 data memory system consists of a DTIM The access latency from a core to its own DTIM is two clock cycles for full words and three clock cycles for smaller quantities Misaligned accesses are not supported in hardware and result in a trap to allow softw...

Page 20: ... 3 7 1 Functional Description The E31 includes a PMP unit which can be used to restrict access to memory and isolate processes from each other The E31 PMP unit has 8 regions and a minimum granularity of 4 bytes Overlapping regions are permitted The E31 PMP unit implements the architecturally defined pmpcfgX CSRs pmpcfg0 and pmpcfg1 supporting 8 regions pmpcfg2 and pmpcfg3 are implemented but hardw...

Page 21: ... CSRs mhpmevent3 and mhpmevent4 are registers that con trol which event causes the corresponding counter to increment The mhpmcounters are 40 bit counters The mhpmcounter_i CSR holds the 32 least significant bits of the corresponding counter and the mhpmcounter_ih CSR holds the 8 most significant bits The event selectors are partitioned into two fields as shown in Table 3 the lower 8 bits select a...

Page 22: ...ication instruction retired 18 Integer division instruction retired Microarchitectural Events mhpeventX 7 0 1 Bits Meaning 8 Load use interlock 9 Long latency interlock 10 CSR read interlock 11 Instruction cache ITIM busy 12 Data cache DTIM busy 13 Branch direction misprediction 14 Branch jump target misprediction 15 Pipeline flush from CSR write 16 Pipeline flush from other event 17 Integer multi...

Page 23: ...Chapter 4 Memory Map The memory map of the FE310 G002 is shown in Table 4 21 ...

Page 24: ...00_FFFF Reserved 0x1001_0000 0x1001_0FFF RW A OTP Control 0x1001_1000 0x1001_1FFF Reserved 0x1001_2000 0x1001_2FFF RW A GPIO 0x1001_3000 0x1001_3FFF RW A UART 0 0x1001_4000 0x1001_4FFF RW A QSPI 0 0x1001_5000 0x1001_5FFF RW A PWM 0 0x1001_6000 0x1001_6FFF RW A I2C 0 0x1001_7000 0x1002_2FFF Reserved 0x1002_3000 0x1002_3FFF RW A UART 1 0x1002_4000 0x1002_4FFF RW A SPI 1 0x1002_5000 0x1002_5FFF RW A ...

Page 25: ...memory mapped QSPI0 10 jump directly to 0x0002_0000 OTP 11 jump directly to 0x0001_0000 Mask ROM Default Boot Mode Table 5 Boot media based on MSEL pins 5 1 Reset Vector On power on the core s reset vector is 0x1004 Address Contents 0x1000 The MSEL pin state 0x1004 auipc t0 0 0x1008 lw t1 4 t0 0x100C slli t1 t1 0x3 0x1010 add t0 t0 t1 0x1014 lw t0 252 t0 0x1018 jr t0 Table 6 Reset vector ROM This ...

Page 26: ...l register interface to program the OTP and a memory read port interface to fetch words from the OTP Instruction fetches from the OTP memory read port are cached in the E31 core s instruction cache The OTP needs to be programmed before use and can only be programmed by code running on the core The OTP bits contain all 0s prior to programming 5 1 3 Quad SPI Flash Controller QSPI The dedicated QSPI ...

Page 27: ...ters live either in the AON block Chapter 13 or the PRCI block Section 6 2 6 1 Clock Generation Overview Figure 2 FE310 G002 clock generation scheme Figure 2 shows an overview of the FE310 G002 clock generation scheme Most digital clocks on the chip are divided down from a central high frequency clock hfclk produced from either the PLL or an on chip trimmable oscillator The PLL can be driven from ...

Page 28: ... block contains registers with similar functions but only for the AON block units Table 8 shows the memory map for the PRCI on the FE310 G002 Offset Name Description 0x00 hfrosccfg Ring Oscillator Configuration and Status 0x04 hfxosccfg Crystal Oscillator Configuration and Status 0x08 pllcfg PLL Configuration and Status 0x0C plloutdiv PLL Final Divide Configuration 0xF0 procmoncfg Process Monitor ...

Page 29: ... used for the system core at reset After a reset the hfrosctrim value is reset to 16 the middle of the adjustable range and the divider is reset to divide by 5 hfroscdiv 4 which gives a nominal 13 8 MHz 50 output frequency The value of hfrosctrim that most closely achieves an 72 MHz clock output at nominal condi tions 1 8 V at 25 C is determined by manufacturing time calibration and is stored in o...

Page 30: ...ator Ready The hfxoscen bit turns on the crystal driver and is set on wakeup reset but can be cleared to turn off the crystal driver and reduce power consumption The hfxoscrdy bit indicates if the crystal oscillator output is ready for use The hfxoscen bit must also be turned on to use the HFXOSC input pad to connect an external clock source 6 5 Internal High Frequency PLL HFPLL The PLL generates ...

Page 31: ...nts must be observed between each stage for correct operation Figure 3 Controlling the FE310 G002 PLL output frequency The pllr 1 0 field encodes the reference clock divide ratio as a 2 bit binary value where the value is one less than the divide ratio i e 00 1 11 4 The frequency of the output of the refer ence divider refr must lie between 6 12 MHz The pllf 5 0 field encodes the PLL VCO multiply ...

Page 32: ...scclk directly drives hfclk The pllsel bit is clear on wakeup reset The pllcfg register is reset to bypass and power off the PLL pllbypass 1 input driven from external HFXOSC oscillator pllrefsel 1 PLL not driving system clock pllsel 0 and the PLL ratios are set to R 2 F 64 and Q 8 pllr 01 pllf 011111 pllq 11 The PLL provides a lock signal which is set when the PLL has achieved lock and which can ...

Page 33: ...requency 32 kHz clock source The LFROSC can generate frequencies in the range 1 5 230 kHz 45 The lfrosccfg register lives in the AON block as shown in Table 36 At power on reset the LFROSC resets to selecting the middle tap lfrosctrim 16 and 5 lfroscdiv 4 resulting in an output frequency of 30 kHz The LFROSC can be calibrated in software using a more accurate high frequency clock source lfrosccfg ...

Page 34: ...y Table 16 summarizes the major clocks on the FE310 G002 and their initial reset conditions At external reset the AON domain lfclk is clocked by either the LFROSC or psdlfaltclk as selected by psdlfaltclksel At wakeup reset the MOFF domain hfclk is clocked by the HFROSC Frequency Name Reset Source Reset Min Max Notes AON Domain LFROSC lfroscrst 32 kHz 1 5 kHz 230 kHz 45 psdlfaltclk 0 kHz 500 kHz W...

Page 35: ...driving the processor pipeline All state is preserved in the system The processor will resume in Run mode when there is a local interrupt pending or when the PLIC sends an interrupt notification The processor may also exit wait mode for other events and software must check system status when exiting wait mode to determine the correct course of action 7 3 Sleep Mode Sleep mode is entered by writing...

Page 36: ...reinitialize the core and can interrogate the PMU pmucause register to determine the cause of reset and can recover pre sleep state from the backup registers The processor always initially runs from the HFROSC at the default setting and must reconfigure clocks to run from an alternate clock source HFXOSC or PLL or at a different setting on the HFROSC Because the FE310 G002 has no internal power re...

Page 37: ...tional memory accesses are required to determine the cause of the interrupt Software and timer interrupts are local interrupts generated by the Core Local Interruptor CLINT The FE310 G002 contains no other local interrupt sources Global interrupts by contrast are routed through a Platform Level Interrupt Controller PLIC which can direct interrupts to any hart in the system via the external interru...

Page 38: ...MIE is copied into mcause MPIE and then mstatus MIE is cleared effectively disabling interrupts The privilege mode prior to the interrupt is encoded in mstatus MPP The current pc is copied into the mepc register and then pc is set to the value specified by mtvec as defined by the mtvec MODE described in Table 19 At this point control is handed over to software in the interrupt handler with interru...

Page 39: ...t contains fields unrelated to interrupts For the full description of mstatus please consult the The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 Machine Status Register CSR mstatus Bits Field Name Attr Description 2 0 Reserved WPRI 3 MIE RW Machine Interrupt Enable 6 4 Reserved WPRI 7 MPIE RW Machine Previous Interrupt Enable 10 8 Reserved WPRI 12 11 MPP RW Machine...

Page 40: ...pt exception code values Mode Direct When operating in direct mode all synchronous exceptions and asynchronous interrupts trap to the mtvec BASE address Inside the trap handler software must read the mcause register to determine what triggered the trap Mode Vectored While operating in vectored mode interrupts set the pc to mtvec BASE 4 exception code For example if a machine timer interrupt is tak...

Page 41: ...3 MSIP RO Machine Software Interrupt Pending 6 4 Reserved WIRI 7 MTIP RO Machine Timer Interrupt Pending 10 8 Reserved WIRI 11 MEIP RO Machine External Interrupt Pending 31 12 Reserved WIRI Table 21 mip Register 8 3 5 Machine Cause mcause When a trap is taken in machine mode mcause is written with a code indicating the event that caused the trap When the event that caused the trap is an interrupt ...

Page 42: ...truction address misaligned 0 1 Instruction access fault 0 2 Illegal instruction 0 3 Breakpoint 0 4 Load address misaligned 0 5 Load access fault 0 6 Store AMO address misaligned 0 7 Store AMO access fault 0 8 Environment call from U mode 0 9 10 Reserved 0 11 Environment call from M mode 0 12 Reserved Table 23 mcause Exception Codes 8 4 Interrupt Priorities Individual priorities of global interrup...

Page 43: ...dler Global interrupts routed through the PLIC incur additional latency of 3 cycles where the PLIC is clocked by coreClk This means that the total latency in cycles for a global interrupt is 4 3 This is a best case cycle count and assumes the handler is cached or located in ITIM It does not take into account additional latency from a peripheral source Copyright 2019 SiFive Inc All rights reserved ...

Page 44: ...p for hart 0 MTIMECMP Registers 0x2004008 0x200bff7 Reserved 0x200bff8 8B RW mtime Timer Register 0x200c000 Reserved Table 24 CLINT Register Map 9 2 MSIP Registers Machine mode software interrupts are generated by writing to the memory mapped control reg ister msip Each msip register is a 32 bit wide WARL register where the upper 31 bits are tied to 0 The least significant bit is reflected in the ...

Page 45: ... in Chapter 13 A timer interrupt is pending whenever mtime is greater than or equal to the value in the mtimecmp register The timer interrupt is reflected in the mtip bit of the mip register described in Chapter 8 On reset mtime is cleared to zero The mtimecmp registers are not reset Copyright 2019 SiFive Inc All rights reserved 43 ...

Page 46: ...2 The PLIC complies with The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 and supports 52 interrupt sources with 7 priority levels 10 1 Memory Map The memory map for the FE310 G002 PLIC control registers is shown in Table 25 The PLIC memory map has been designed to only require naturally aligned 32 bit memory accesses 44 ...

Page 47: ...eserved 0x0C20_0000 4B RW Hart 0 M Mode priority threshold See Section 10 6 for more information 0x0C20_0004 4B RW Hart 0 M Mode claim com plete See Section 10 7 for more information 0x0C20_0008 Reserved 0x1000_0000 End of PLIC Memory Map Table 25 SiFive PLIC Register Map Only naturally aligned 32 bit memory accesses are required 10 2 Interrupt Sources The FE310 G002 has 52 interrupt sources These...

Page 48: ...st effective priority See Table 27 for the detailed register description PLIC Interrupt Priority Register priority Base Address 0x0C00_0000 4 Interrupt ID Bits Field Name Attr Rst Description 2 0 Priority RW X Sets the priority for a given global inter rupt 31 3 Reserved RO 0 Table 27 PLIC Interrupt Priority Registers 10 4 Interrupt Pending Bits The current status of the interrupt source pending b...

Page 49: ...04 Bits Field Name Attr Rst Description 0 Interrupt 32 Pend ing RO 0 Pending bit for global interrupt 32 20 Interrupt 52 Pend ing RO 0 Pending bit for global interrupt 52 31 21 Reserved WIRI X Table 29 PLIC Interrupt Pending Register 2 10 5 Interrupt Enables Each global interrupt can be enabled by setting the corresponding bit in the enables registers The enables registers are accessed as a contig...

Page 50: ...31 PLIC Interrupt Enable Register 2 for Hart 0 M Mode 10 6 Priority Thresholds The FE310 G002 supports setting of an interrupt priority threshold via the threshold register The threshold is a WARL field where the FE310 G002 supports a maximum threshold of 7 The FE310 G002 masks all PLIC interrupts of a priority less than or equal to threshold For example a threshold value of zero permits all inter...

Page 51: ...hreshold register 10 8 Interrupt Completion A FE310 G002 hart signals it has completed executing an interrupt handler by writing the inter rupt ID it received from the claim to the claim complete register Table 33 The PLIC does not check whether the completion ID is the same as the last claim ID for that target If the comple tion ID does not match an interrupt source that is currently enabled for ...

Page 52: ... X A read of zero indicates that no inter rupts are pending A non zero read contains the id of the highest pending interrupt A write to this register signals completion of the interrupt id written Table 33 PLIC Interrupt Claim Complete Register for Hart 0 M Mode Copyright 2019 SiFive Inc All rights reserved 50 ...

Page 53: ...t has no registers The entire memory range discards writes and returns zeros on read Both operation acknowledgments carry an error indication The error device serves a dual role Internally it is used as a landing pad for illegal off chip requests However it also useful for testing software handling of bus errors 51 ...

Page 54: ... 37 MHz vrren is asserted during synchronous reset it is safe to read from OTP immediately after reset if reset is asserted for at least 150 us while the controller s clock is running Programmed I O reads and writes are sequenced entirely by software 12 1 Memory Map The memory map for the OTP control registers is shown in Table 34 The control register mem ory map has been designed to only require ...

Page 55: ...s clear memory mapped reads may proceed When the lock is set memory mapped reads do not access the OTP device and instead return 0 immedi ately The otp_lock should be acquired before writing to any other control register Software can attempt to acquire the lock by storing 1 to otp_lock If a memory mapped read is in progress the lock will not be acquired and will retain the value 0 Software can che...

Page 56: ...lock cycles in each phase is given by and the width of each phase may be optionally scaled by 3 That is the number of controller clock cycles in the address setup phase is given by the expression the number of clock cycles in the read pulse phase is given by and the read access phase is cycles long Software should acquire the otp_lock prior to modifying otp_rsctrl otp_rsctrl OTP read sequencer con...

Page 57: ...tages to stabilize 4 ADDRESS the memory by setting otp_a 5 WRITE one bit at a time a Set only the bit you want to write high in otp_d b Bring otp_ck HIGH for 50 us c Bring otp_ck LOW Note that this means only one bit of otp_d should be high at any time 6 VERIFY the written bits setting otp_mrr 0x9 for read margin 7 SOAK any verification failures by repeating steps 2 5 using 400 us pulses 8 REVERIF...

Page 58: ...always on AON domain that includes real time counter a watchdog timer backup registers low frequency clocking and reset and power management circuitry for the rest of the system Figure 5 shows an overview of the AON block Figure 5 FE310 G002 Always On Domain 56 ...

Page 59: ...t_n a debug unit reset ndreset or expiration of the watchdog timer wdogrst These sources provide a short initial reset pulse frst which is extended by a reset stretcher to provide the LFROSC reset signal lfroscrst and a longer stretched internal reset srst The lfroscrst signal is used to initialize the ring oscillator in the LFROSC This oscillator pro vides lfclk which is used to clock the AON lfc...

Page 60: ...imer WDT The watchdog timer can be used to provide a watchdog reset function or a periodic timer inter rupt The watchdog is described in detail in Chapter 14 13 8 Real Time Clock RTC The real time clock maintains time for the system and can also be used to generate interrupts for timed wakeup from sleep mode or timer interrupts during normal operation The Real Time Clock is described in detail in ...

Page 61: ...kup_7 Backup Register 7 0x0A0 backup_8 Backup Register 8 0x0A4 backup_9 Backup Register 9 0x0A8 backup_10 Backup Register 10 0x0AC backup_11 Backup Register 11 0x0B0 backup_12 Backup Register 12 0x0B4 backup_13 Backup Register 13 0x0B8 backup_14 Backup Register 14 0x0BC backup_15 Backup Register 15 0x100 pmuwakeupi0 Wakeup program instruction 0 0x104 pmuwakeupi1 Wakeup program instruction 1 0x108 ...

Page 62: ...usleepi7 Sleep program instruction 7 0x140 pmuie PMU Interrupt Enables 0x144 pmucause PMU Wakeup Cause 0x148 pmusleep Initiate PMU Sleep Sequence 0x14C pmukey PMU Key Reads as 1 when PMU is unlocked 0x210 SiFiveBandgap Bandgap configuration 0x300 AONCFG AON Block Configuration Information Table 36 AON Domain Memory Map Copyright 2019 SiFive Inc All rights reserved 60 ...

Page 63: ...old else it will trigger a full power on reset To prevent errant code from resetting the counter the WDT registers can only be updated by presenting a WDT key sequence w dogcm p w dogcf g w dogcm pi p w dogcl k aonrst w dogcount w dogs w dogscal e Wdog TileLink w dogf eed reset w dogrst aonrst en w dogcl k w dogkey corerst Synch w dogzerocm p w dogrst en w dogenal w ays w dogencoreaw ake Figure 6 ...

Page 64: ...ways RW 0x0 Enable Always run continuously 13 wdogcoreawake RW 0x0 Increment the watchdog counter if the processor is not asleep 27 14 Reserved 28 wdogip0 RW X Interrupt 0 Pending 31 29 Reserved The wdogen bits control the conditions under which the watchdog counter wdogcount is incre mented The wdogenalways bit if set means the watchdog counter always increments The wdogencoreawake bit if set mea...

Page 65: ...cmp0 Register Offset 0x20 Bits Field Name Attr Rst Description 15 0 wdogcmp0 RW X Comparator 0 31 16 Reserved The wdogcmp compare register is a 16 bit value against which the current wdogs value is com pared every cycle The output of the comparator is asserted whenever the value of wdogs is greater than or equal to wdogcmp 14 5 Watchdog Key Register wdogkey The wdogkey register has one bit of stat...

Page 66: ... If the watchdog is not fed before the wdogcount register exceeds the compare register zero while the WDT is enabled a reset pulse is sent to the reset circuitry and the chip will go through a complete power on sequence The WDT will be initalized after a full reset with the wdogrsten and wdogen bits cleared 14 9 Watchdog Interrupts wdogip0 The WDT can be configured to provide periodic counter inte...

Page 67: ...The FE310 G002 power management unit PMU is implemented within the AON domain and sequences the system s power supplies and reset signals during power on reset and when tran sitioning the mostly off MOFF block into and out of sleep mode 65 ...

Page 68: ...d by power on reset wakeup events and sleep requests When the MOFF block is powered off the PMU monitors AON signals to initiate the wakeup sequence When the MOFF block is powered on the PMU awaits sleep requests from the MOFF block which initiate the sleep sequence The PMU is based around a simple pro grammable microcode sequencer that steps through short programs to sequence output signals that ...

Page 69: ...n PMU is unlocked 15 3 PMU Key Register pmukey The pmukey register has one bit of state To prevent spurious sleep or PMU program modifica tion all writes to PMU registers must be preceded by an unlock operation to the pmukey register location which sets pmukey to 1 The value 0x51F15E must be written to the pmukey register address to set the state bit before any write access to any other PMU regist...

Page 70: ...ogram Instruction Value Meaning 0 0x3F0 Assert all resets and enable all power supplies 1 0x2F8 Idle cycles then deassert hfclkrst 2 0x030 Deassert corerst and padrst 3 7 0x030 Repeats Program Instruction Value Meaning 0 0x2F0 Assert corerst 1 0x3F0 Assert hfclkrst 2 0x3D0 Deassert pmu_out_1 3 0x3C0 Deassert pmu_out_0 4 7 0x3C0 Repeats 15 5 Initiate Sleep Sequence Register pmusleep Writing any val...

Page 71: ...ollowing a wakeup the pmucause register indicates which event caused the wakeup The value in the wakeupcause field corresponds to the bit position of the event in pmuie e g a value of 2 indicates dwakeup The value 0 indicates a wakeup from reset These causes are shown in Table 45 In the event of a wakeup from reset the resetcause field indicates which reset source triggered the wakeup Table 46 lis...

Page 72: ...Index Meaning 0 Power on Reset 1 External reset 2 Watchdog timer reset Table 46 Reset cause values Copyright 2019 SiFive Inc All rights reserved 70 ...

Page 73: ... rt cl o rt cs rt cen rt cscal e Figure 8 Real Time Clock 16 1 RTC Count Registers rtccounthi rtccountlo The real time counter is based around the rtccounthi rtccountlo register pair which incre ment at the low frequency clock rate when the RTC is enabled The rtccountlo register holds the low 32 bits of the RTC while rtccounthi holds the upper 16 bits of the RTC value The total 48 bit counter widt...

Page 74: ...n rtcscale is the bit position within the rtccountlo rtccounthi register pair of the start of a 32 bit field rtcs A value of 0 in rtcscale indicates no scaling and rtcs would then be equal to rtclo The maximum value of 15 in rtcscale corresponds to dividing the clock rate by so for an input clock of 32 768 kHz the LSB of rtcs will incre ment once per second The value of rtcs is memory mapped and c...

Page 75: ...rtccmp0 Comparator 0 rtccmp0 Register Offset 0x60 Bits Field Name Attr Rst Description 31 0 rtccmp0 RW X Comparator 0 Table 50 rtccmp0 Comparator 0 Copyright 2019 SiFive Inc All rights reserved 73 ...

Page 76: ...al memory map It is responsible for low level configuration of actual GPIO pads on the device direction pull up enable and drive value as well as selecting between various sources of the controls for these signals The GPIO controller allows separate configuration of each of ngpio GPIO bits Figure 9 shows the control structure for each pin Atomic operations such as toggles are natively possible wit...

Page 77: ...Figure 9 Structure of a single GPIO Pin with Control Registers This structure is repeated for each pin Copyright 2019 SiFive Inc All rights reserved 75 ...

Page 78: ...x20 fall_ie Fall interrupt enable 0x24 fall_ip Fall interrupt pending 0x28 high_ie High interrupt enable 0x2C high_ip High interrupt pending 0x30 low_ie Low interrupt enable 0x34 low_ip Low interrupt pending 0x40 out_xor Output XOR invert 17 3 Input Output Values The GPIO can be configured on a bitwise fashion to represent inputs and or outputs as set by the input_en and output_en registers Writin...

Page 79: ...d pull ups are disabled 17 6 Drive Strength When configured as output each pin has a software controllable drive strength 17 7 Output Inversion When configured as an output either software or IOF controlled the software writable out_xor register is combined with the output to invert it 17 8 HW I O Functions IOF Each GPIO pin can implement up to 2 HW Driven functions IOF enabled with the iof_en reg...

Page 80: ...SPI1_CS2 10 SPI1_CS3 PWM2_PWM0 11 PWM2_PWM1 12 I2C0_SDA PWM2_PWM2 13 I2C0_SCL PWM2_PWM3 14 15 16 UART0_RX 17 UART0_TX 18 UART1_TX 19 PWM1_PWM1 20 PWM1_PWM0 21 PWM1_PWM2 22 PWM1_PWM3 23 UART1_RX 24 25 26 SPI2_CS0 27 SPI2_DQ0 28 SPI2_DQ1 29 SPI2_SCK 30 SPI2_DQ2 31 SPI2_DQ3 Table 53 GPIO IOF Mapping Copyright 2019 SiFive Inc All rights reserved 78 ...

Page 81: ...transmit and receive FIFO buffers with programmable watermark interrupts 16 Rx oversampling with 2 3 majority voting per bit The UART peripheral does not support hardware flow control or other modem control signals or synchronous serial data transfers 18 2 UART Instances in FE310 G002 FE310 G002 contains two UART instances Their addresses and parameters are shown in Table 54 Instance Num ber Addre...

Page 82: ...ro in the data field The full flag indicates whether the transmit FIFO is able to accept new entries when set writes to data are ignored A RISC V amoor w instruction can be used to both read the full status and attempt to enqueue data with a non zero return value indicating the character was not accepted Transmit Data Register txdata Register Offset 0x0 Bits Field Name Attr Rst Description 7 0 dat...

Page 83: ... register is reset to 0 Transmit Control Register txctrl Register Offset 0x8 Bits Field Name Attr Rst Description 0 txen RW 0x0 Transmit enable 1 nstop RW 0x0 Number of stop bits 15 2 Reserved 18 16 txcnt RW 0x0 Transmit watermark level 31 19 Reserved 18 7 Receive Control Register rxctrl The read write rxctrl register controls the operation of the receive channel The rxen bit con trols whether the...

Page 84: ...ount specified by the rxcnt field of the rxctrl register The pending bit is cleared when sufficient entries have been dequeued to fall below the watermark UART Interrupt Enable Register ie Register Offset 0x10 Bits Field Name Attr Rst Description 0 txwm RW 0x0 Transmit watermark interrupt enable 1 rxwm RW 0x0 Receive watermark interrupt enable 31 2 Reserved UART Interrupt Pending Register ip Regis...

Page 85: ... 250000 0 200 1843200 109 1834862 0 45 384 31250 12288 31250 0 384 115200 3333 115211 0 01 384 250000 1536 250000 0 384 1843200 208 1846153 0 16 Table 62 Common baud rates MIDI 31250 DMX 250000 and required divide values to achieve them with given bus clock frequencies The divide val ues are one greater than the value stored in the div register The receive channel is sampled at 16 the baud rate an...

Page 86: ...memory mapped device Such controllers are reset to a state that allows memory mapped reads under the assumption that the input clock rate is less than 100 MHz and the external SPI flash device supports the common Win bond Numonyx serial read 0x03 command Sequential accesses are automatically combined into one long read command for higher performance The fctrl register controls switching between th...

Page 87: ...0x10024000 4 12 SPI 2 N 0x10034000 1 12 Table 64 SPI Instances 19 3 Memory Map The memory map for the SPI control registers is shown in Table 65 The SPI memory map has been designed to require only naturally aligned 32 bit memory accesses Copyright 2019 SiFive Inc All rights reserved 85 ...

Page 88: ... FIFO watermark 0x54 rxmark Rx FIFO watermark 0x58 Reserved 0x5C Reserved 0x60 fctrl SPI flash interface control 0x64 ffmt SPI flash instruction format 0x68 Reserved 0x6C Reserved 0x70 ie SPI interrupt enable 0x74 ip SPI interrupt pending 19 4 Serial Clock Divisor Register sckdiv The sckdiv is a div_width bit register that specifies the divisor used for generating the serial clock SCK The relation...

Page 89: ...Name Attr Rst Description 0 pha RW 0x0 Serial clock phase 1 pol RW 0x0 Serial clock polarity 31 2 Reserved Value Description 0 Inactive state of SCK is logical 0 1 Inactive state of SCK is logical 1 Value Description 0 Data is sampled on the leading edge of SCK and shifted on the trailing edge of SCK 1 Data is shifted on the leading edge of SCK and sampled on the trailing edge of SCK 19 6 Chip Sel...

Page 90: ...avior as described in Table 72 The reset value is 0x0 AUTO In HOLD mode the CS pin is deasserted only when one of the fol lowing conditions occur A different value is written to csmode or csid A write to csdef changes the state of the selected pin Direct mapped flash mode is enabled Chip Select Mode Register csmode Register Offset 0x18 Bits Field Name Attr Rst Description 1 0 mode RW 0x0 Chip sele...

Page 91: ...deasserting CS This is applicable only when sckmode is HOLD or OFF The reset value is 0x0 Delay Control Register 0 delay0 Register Offset 0x28 Bits Field Name Attr Rst Description 7 0 cssck RW 0x1 CS to SCK Delay 15 8 Reserved 23 16 sckcs RW 0x1 SCK to CS Delay 31 24 Reserved Delay Control Register 1 delay1 Register Offset 0x2C Bits Field Name Attr Rst Description 7 0 intercs RW 0x1 Minimum CS ina...

Page 92: ...ins 0 Single DQ0 MOSI DQ1 MISO 1 Dual DQ0 DQ1 2 Quad DQ0 DQ1 DQ2 DQ3 Value Description 0 Transmit most significant bit MSB first 1 Transmit least significant bit LSB first Value Description 0 Rx For dual and quad protocols the DQ pins are tri stated For the single protocol the DQ0 pin is driven with the transmit data as normal 1 Tx The receive FIFO is not populated 19 11 Transmit Data Register txd...

Page 93: ... field does not contain a valid frame Writes to rxdata are ignored Receive Data Register rxdata Register Offset 0x4C Bits Field Name Attr Rst Description 7 0 data RO X Received data 30 8 Reserved 31 empty RW X FIFO empty flag 19 13 Transmit Watermark Register txmark The txmark register specifies the threshold at which the Tx FIFO watermark interrupt triggers The reset value is 1 for flash enabled ...

Page 94: ...fficient entries have been enqueued to exceed the watermark See Table 85 The rxwm condition becomes raised when the number of entries in the receive FIFO is strictly greater than the count specified by the rxmark register The pending bit is cleared when suffi cient entries have been dequeued to fall below the watermark See Table 85 SPI Interrupt Enable Register ie Register Offset 0x70 Bits Field N...

Page 95: ...e An instruction consists of a command byte followed by a variable number of address bytes dummy cycles padding and data bytes Table 87 describes the function and reset value of each field SPI Flash Instruction Format Register ffmt Register Offset 0x64 Bits Field Name Attr Rst Description 0 cmd_en RW 0x1 Enable sending of command 3 1 addr_len RW 0x3 Number of address bytes 0 to 4 7 4 pad_cnt RW 0x...

Page 96: ...enerate multi ple types of waveforms on output pins pwm gpio and can also be used to generate several forms of internal timer interrupt The comparator results are captured in the pwmcmp ip flops and then fed to the PLIC as potential interrupt sources The pwmcmp ip outputs are further processed by an output ganging stage before being fed to the GPIOs PWM instances can support comparator precisions ...

Page 97: ...es Their addresses and parameters are shown in Table 88 Instance Number Address ncmp cmpwidth 0 0x10015000 4 8 1 0x10025000 4 16 2 0x10035000 4 16 Table 88 PWM Instances 20 3 PWM Memory Map The memory map for the PWM peripheral is shown in Table 89 Copyright 2019 SiFive Inc All rights reserved 95 ...

Page 98: ...its the counter is held in pwmcount 30 0 and bit 31 of pwmcount returns a zero when read When used for PWM generation the counter is normally incremented at a fixed rate then reset to zero at the end of every PWM cycle The PWM counter is either reset when the scaled counter pwms reaches the value in pwmcmp0 or is simply allowed to wrap around to zero The counter can also be used in one shot mode w...

Page 99: ... Compare Gang 28 pwmcmp0ip RW X PWM0 Interrupt Pending 29 pwmcmp1ip RW X PWM1 Interrupt Pending 30 pwmcmp2ip RW X PWM2 Interrupt Pending 31 pwmcmp3ip RW X PWM3 Interrupt Pending The pwmcfg register contains various control and status information regarding the PWM periph eral as shown in Table 91 The pwmen bits control the conditions under which the PWM counter pwmcount is incremented The counter i...

Page 100: ...o implement periodic counter interrupts where the period is independent of interrupt service time 20 6 Scaled PWM Count Register pwms The Scaled PWM Count Register pwms reports the cmpwidth bit portion of pwmcount which starts at pwmscale and is what is used for comparison against the pwmcmp registers Scaled PWM Count Register pwms Register Offset 0x10 Bits Field Name Attr Rst Description 15 0 pwm...

Page 101: ...ise the counter is allowed to wrap around 20 8 Deglitch and Sticky Circuitry To avoid glitches in the PWM waveforms when changing pwmcmp register values the pwmdeglitch bit in pwmcfg can be set to capture any high output of a PWM comparator in a sticky bit pwmcmp ip for comparator and prevent the output falling again within the same PWM cycle The pwmcmp ip bits are only allowed to change at the st...

Page 102: ...less than the maximum count value 6 in this case it is possible to generate both 100 pwmcmp 0 and 0 pwmcmp pwmcmp0 right aligned duty cycles using the other comparators The pwmcmp ip bits are routed to the GPIO pads where they can be optionally and individually inverted thereby creating left aligned PWM waveforms high at beginning of cycle 20 10 Generating Center Aligned Phase Correct PWM Waveform...

Page 103: ... a 3 bit PWM precision The signals can be inverted at the GPIOs to generate opposite phase waveforms When a comparator is operating in center mode the deglitch circuit allows one 0 to 1 transition during the first half of the cycle and one 1 to 0 transition during the second half of the cycle 20 11 Generating Arbitrary PWM Waveforms using Ganging A comparator can be ganged together with its next h...

Page 104: ...rupts The PWM can be configured to provide periodic counter interrupts by enabling auto zeroing of the count register when a comparator 0 fires pwmzerocmp 1 The pwmsticky bit should also be set to ensure interrupts are not forgotten while waiting to run a handler The interrupt pending bits pwmcmp ip can be cleared down using writes to the pwmcfg register The PWM peripheral can also be used as a re...

Page 105: ...ed on OpenCores I C Master Core Download the original documentation at https opencores org project i2c All I C control register addresses are 4 byte aligned 21 1 I C Instance in FE310 G002 FE310 G002 contains one I C instance Its address is shown in Table 98 Instance Number Address 0 0x10016000 Table 98 I C Instance 103 ...

Page 106: ...d TDR D M tdata3 Third field of selected TDR D M dcsr Debug control and status register D dpc Debug PC D dscratch Debug scratch register D Table 99 Debug Control and Status Registers The dcsr dpc and dscratch registers are only accessible in debug mode while the tselect and tdata1 3 registers are accessible from either debug mode or machine mode 22 1 1 Trace and Debug Register Select tselect To su...

Page 107: ...Data Register 1 CSR tdata1 Bits Field Name Attr Description 27 0 TDR Specific Data 31 28 type RO Type of the trace debug register selected by tselect Table 101 tdata1 CSR Trace and Debug Data Registers 2 and 3 CSR tdata2 3 Bits Field Name Attr Description 31 0 TDR Specific Data Table 102 tdata2 3 CSRs The high nibble of tdata1 contains a 4 bit type code that is used to identify the type of TDR sel...

Page 108: ...Debug ROM The debugger may use it as described in The RISC V Debug Specifi cation 0 13 22 2 Breakpoints The FE310 G002 supports eight hardware breakpoint registers per hart which can be flexibly shared between debug mode and machine mode When a breakpoint register is selected with tselect the other CSRs access the following infor mation for the selected breakpoint CSR Name Breakpoint Alias Descrip...

Page 109: ...ifies the available actions when the address match is successful The value 0 generates a breakpoint exception The value 1 enters debug mode Other actions are not implemented The R W X bits are individual WARL fields and if set indicate an address match should only be successful for loads stores instruction fetches respectively and all combinations of imple mented bits must be supported The M S U b...

Page 110: ...s set to 1 bit 30 set to 0 and bit 31 holding the only address bit considered in the address comparison To provide breakpoints on an exact range two neighboring breakpoints can be combined with the chain bit The first breakpoint can be set to match on an address using action of 2 greater than or equal The second breakpoint can be set to match on address using action of 3 less than Setting the chai...

Page 111: ... can be determined by executing aiupc instructions and storing the result into the program buffer The FE310 G002 has one 32 bit words of debug data RAM Its location can be determined by reading the DMHARTINFO register as described in the RISC V Debug Specification This RAM space is used to pass data for the Access Register abstract command described in the RISC V Debug Specification The FE310 G002...

Page 112: ...by any program buffer code The specific behavior of the flags is not further documented here 22 3 4 Safe Zero Address In the FE310 G002 the debug module contains the address 0x0 in the memory map Reads to this address always return 0 and writes to this address have no impact This property allows a safe location for unprogrammed parts as the default mtvec location is 0x0 Copyright 2019 SiFive Inc A...

Page 113: ...stry standard 1149 1 JTAG interface to test and debug the system The JTAG interface is directly connected to input pins 23 1 JTAG TAPC State Machine The JTAG controller includes the standard TAPC state machine shown in Figure 13 The state machine is clocked with TCK All transitions are labelled with the value on TMS except for the arc showing asynchronous reset when TRST 0 111 ...

Page 114: ...s reset the jtag_reset signal is synchronized inside the FE310 G002 During operation the JTAG DTM logic can also be reset without jtag_reset by issuing 5 jtag_TCK clock ticks with jtag_TMS asserted This action resets only the JTAG DTM not the debug module 23 3 JTAG Clocking The JTAG logic always operates in its own clock domain clocked by jtag_TCK The JTAG logic is fully static and has no minimum ...

Page 115: ...e debug module by connecting the debug scan register between jtag_TDI and jtag_TDO The debug scan register includes a 2 bit opcode field a 7 bit debug module address field and a 32 bit data field to allow various memory mapped read write operations to be specified with a single scan of the debug scan register These are described in The RISC V Debug Specification 0 13 Copyright 2019 SiFive Inc All ...

Page 116: ... sifive com 1 A Waterman and K Asanovic Eds The RISC V Instruction Set Manual Volume I User Level ISA Version 2 2 May 2017 Online Available https riscv org specifications 2 The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 May 2017 Online Available https riscv org specifications 114 ...