Silicon Laboratories C8051F12 Series, Manual

Page 1: ...executes 70 of instruction set in 1 or 2 system clocks 100 MIPS or 50 MIPS throughput with on chip PLL 2 cycle 16 x 16 MAC engine C8051F120 1 2 3 and C8051F130 1 2 3 only Memory 8448 bytes internal data RAM 8 k 256 128 or 64 kB Banked Flash in system programma ble in 1024 byte sectors External 64 kB data memory interface programma ble multiplexed or non multiplexed modes Digital Peripherals 8 byte...

Page 2: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 2 Rev 1 4 NOTES ...

Page 3: ... 4 Pinout and Package Definitions 41 5 ADC0 12 Bit ADC C8051F120 1 4 5 Only 55 5 1 Analog Multiplexer and PGA 55 5 2 ADC Modes of Operation 57 5 2 1 Starting a Conversion 57 5 2 2 Tracking Modes 58 5 2 3 Settling Time Requirements 59 5 3 ADC0 Programmable Window Detector 66 6 ADC0 10 Bit ADC C8051F122 3 6 7 and C8051F13x Only 73 6 1 Analog Multiplexer and PGA 73 6 2 ADC Modes of Operation 75 6 2 1...

Page 4: ...emory 135 11 2 3 General Purpose Registers 135 11 2 4 Bit Addressable Locations 135 11 2 5 Stack 135 11 2 6 Special Function Registers 136 11 2 7 Register Descriptions 151 11 3 Interrupt Handler 154 11 3 1 MCU Interrupt Sources and Vectors 154 11 3 2 External Interrupts 155 11 3 3 Interrupt Priorities 156 11 3 4 Interrupt Latency 156 11 3 5 Interrupt Register Descriptions 157 11 4 Power Management...

Page 5: ...ultiplication and Output Clock 191 14 7 3 Powering on and Initializing the PLL 192 15 Flash Memory 199 15 1 Programming the Flash Memory 199 15 1 1 Non volatile Data Storage 200 15 1 2 Erasing Flash Pages From Software 201 15 1 3 Writing Flash Memory From Software 202 15 2 Security Options 203 15 2 1 Summary of Flash Security Options 207 16 Branch Target Cache 211 16 1 Cache and Prefetch Operation...

Page 6: ...onfiguring the Output Modes of the Port Pins 252 18 2 3 Configuring Port Pins as Digital Inputs 253 18 2 4 Weak Pullups 253 18 2 5 External Memory Interface 253 19 System Management Bus I2C Bus SMBus0 259 19 1 Supporting Documents 260 19 2 SMBus Protocol 260 19 2 1 Arbitration 261 19 2 2 Clock Low Extension 261 19 2 3 SCL Low Timeout 261 19 2 4 SCL High SMBus Free Timeout 261 19 3 SMBus Transfer M...

Page 7: ... 301 22 2 1 8 Bit UART 301 22 2 2 9 Bit UART 302 22 3 Multiprocessor Communications 303 23 Timers 309 23 1 Timer 0 and Timer 1 309 23 1 1 Mode 0 13 bit Counter Timer 309 23 1 2 Mode 1 16 bit Counter Timer 311 23 1 3 Mode 2 8 bit Counter Timer with Auto Reload 311 23 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only 312 23 2 Timer 2 Timer 3 and Timer 4 317 23 2 1 Configuring Timer 2 3 and 4 to Count...

Page 8: ...E 1149 1 341 25 1 Boundary Scan 342 25 1 1 EXTEST Instruction 343 25 1 2 SAMPLE Instruction 343 25 1 3 BYPASS Instruction 343 25 1 4 IDCODE Instruction 343 25 2 Flash Programming Commands 344 25 3 Debug Support 347 Document Change List 349 Contact Information 350 ...

Page 9: ...trical Characteristics 4 Pinout and Package Definitions Figure 4 1 C8051F120 2 4 6 Pinout Diagram TQFP 100 49 Figure 4 2 C8051F130 2 Pinout Diagram TQFP 100 50 Figure 4 3 TQFP 100 Package Drawing 51 Figure 4 4 C8051F121 3 5 7 Pinout Diagram TQFP 64 52 Figure 4 5 C8051F131 3 Pinout Diagram TQFP 64 53 Figure 4 6 TQFP 64 Package Drawing 54 5 ADC0 12 Bit ADC C8051F120 1 4 5 Only Figure 5 1 12 Bit ADC0...

Page 10: ...ential Mode 101 8 DACs 12 Bit Voltage Mode C8051F12x Only Figure 8 1 DAC Functional Block Diagram 105 9 Voltage Reference Figure 9 1 Voltage Reference Functional Block Diagram C8051F120 2 4 6 114 Figure 9 2 Voltage Reference Functional Block Diagram C8051F121 3 5 7 115 Figure 9 3 Voltage Reference Functional Block Diagram C8051F130 1 2 3 117 10 Comparators Figure 10 1 Comparator Functional Block D...

Page 11: ... 229 Figure 17 7 Multiplexed 16 bit MOVX Timing 230 Figure 17 8 Multiplexed 8 bit MOVX without Bank Select Timing 231 Figure 17 9 Multiplexed 8 bit MOVX with Bank Select Timing 232 18 Port Input Output Figure 18 1 Port I O Cell Block Diagram 235 Figure 18 2 Port I O Functional Block Diagram 237 Figure 18 3 Priority Crossbar Decode Table EMIFLE 0 P1MDIN 0xFF 238 Figure 18 4 Priority Crossbar Decode...

Page 12: ... Diagram 294 22 UART1 Figure 22 1 UART1 Block Diagram 299 Figure 22 2 UART1 Baud Rate Logic 300 Figure 22 3 UART Interconnect Diagram 301 Figure 22 4 8 Bit UART Timing Diagram 301 Figure 22 5 9 Bit UART Timing Diagram 302 Figure 22 6 UART Multi Processor Mode Interconnect Diagram 303 23 Timers Figure 23 1 T0 Mode 0 Block Diagram 310 Figure 23 2 T0 Mode 2 Block Diagram 311 Figure 23 3 T0 Mode 3 Blo...

Page 13: ...acteristics 103 8 DACs 12 Bit Voltage Mode C8051F12x Only Table 8 1 DAC Electrical Characteristics 111 9 Voltage Reference Table 9 1 Voltage Reference Electrical Characteristics 118 10 Comparators Table 10 1 Comparator Electrical Characteristics 126 11 CIP 51 Microcontroller Table 11 1 CIP 51 Instruction Set Summary 129 Table 11 2 Special Function Register SFR Memory Map 144 Table 11 3 Special Fun...

Page 14: ...Settings for Standard Baud Rates Using The Internal 24 5 MHz Oscillator 305 Table 22 2 Timer Settings for Standard Baud Rates Using an External 25 0 MHz Oscillator 306 Table 22 3 Timer Settings for Standard Baud Rates Using an External 22 1184 MHz Oscillator 306 Table 22 4 Timer Settings for Standard Baud Rates Using the PLL 307 Table 22 5 Timer Settings for Standard Baud Rates Using the PLL 307 2...

Page 15: ...Than Data High Byte 85 SFR Definition 6 10 ADC0LTL ADC0 Less Than Data Low Byte 85 SFR Definition 7 1 AMX2CF AMUX2 Configuration 95 SFR Definition 7 2 AMX2SL AMUX2 Channel Select 96 SFR Definition 7 3 ADC2CF ADC2 Configuration 97 SFR Definition 7 4 ADC2CN ADC2 Control 98 SFR Definition 7 5 ADC2 ADC2 Data Word 99 SFR Definition 7 6 ADC2GT ADC2 Greater Than Data Byte 102 SFR Definition 7 7 ADC2LT AD...

Page 16: ...inition 12 7 MAC0ACC3 MAC0 Accumulator Byte 3 173 SFR Definition 12 8 MAC0ACC2 MAC0 Accumulator Byte 2 173 SFR Definition 12 9 MAC0ACC1 MAC0 Accumulator Byte 1 173 SFR Definition 12 10 MAC0ACC0 MAC0 Accumulator Byte 0 174 SFR Definition 12 11 MAC0OVR MAC0 Accumulator Overflow 174 SFR Definition 12 12 MAC0RNDH MAC0 Rounding Register High Byte 174 SFR Definition 12 13 MAC0RNDL MAC0 Rounding Register...

Page 17: ...OUT Port5 Output Mode 255 SFR Definition 18 17 P6 Port6 Data 256 SFR Definition 18 18 P6MDOUT Port6 Output Mode 256 SFR Definition 18 19 P7 Port7 Data 257 SFR Definition 18 20 P7MDOUT Port7 Output Mode 257 SFR Definition 19 1 SMB0CN SMBus0 Control 266 SFR Definition 19 2 SMB0CR SMBus0 Clock Rate 267 SFR Definition 19 3 SMB0DAT SMBus0 Data 268 SFR Definition 19 4 SMB0ADR SMBus0 Address 269 SFR Defi...

Page 18: ... 4 High Byte 324 SFR Definition 24 1 PCA0CN PCA Control 335 SFR Definition 24 2 PCA0MD PCA0 Mode 336 SFR Definition 24 3 PCA0CPMn PCA0 Capture Compare Mode 337 SFR Definition 24 4 PCA0L PCA0 Counter Timer Low Byte 338 SFR Definition 24 5 PCA0H PCA0 Counter Timer High Byte 338 SFR Definition 24 6 PCA0CPLn PCA0 Capture Module Low Byte 338 SFR Definition 24 7 PCA0CPHn PCA0 Capture Module High Byte 33...

Page 19: ... Array with 6 capture compare modules On chip Watchdog Timer VDD Monitor and Temperature Sensor With on chip VDD monitor Watchdog Timer and clock oscillator the C8051F12x and C8051F13x devices are truly stand alone System on a Chip solutions All analog and digital peripherals are enabled disabled and configured by user firmware The Flash memory can be reprogrammed even in circuit providing non vol...

Page 20: ...8051F122 GQ 100 128 k 8448 2 5 64 8 8 12 2 2 100TQFP C8051F123 100 128 k 8448 2 5 32 8 8 12 2 2 64TQFP C8051F123 GQ 100 128 k 8448 2 5 32 8 8 12 2 2 64TQFP C8051F124 50 128 k 8448 2 5 64 8 8 12 2 2 100TQFP C8051F124 GQ 50 128 k 8448 2 5 64 8 8 12 2 2 100TQFP C8051F125 50 128 k 8448 2 5 32 8 8 12 2 2 64TQFP C8051F125 GQ 50 128 k 8448 2 5 32 8 8 12 2 2 64TQFP C8051F126 50 128 k 8448 2 5 64 8 8 12 2 ...

Page 21: ... Digital Power Analog Power Debug HW Boundary Scan 8 kB XRAM P2 0 P2 7 P1 0 AIN2 0 P1 7 AIN2 7 P0 0 P0 7 P1 Drv P2 Drv Data Bus Address Bus Bus Control DAC1 DAC1 12 Bit VREF DAC0 12 Bit ADC 100 ksps 12 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFD VREF0 Prog Gain CP0 CP1 C T L P4 Latch D a t a P7...

Page 22: ... P1 Drv P2 Drv Data Bus Address Bus Bus Control DAC1 DAC1 12 Bit VREF DAC0 12 Bit ADC 100 ksps 12 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFA Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 DRV P5 DRV P6 DRV P4 DRV Prog Gain ADC 500 ksps 8 Bit A M U X VREFA AV XTA...

Page 23: ...Control DAC1 DAC1 12 Bit VREF DAC0 12 Bit ADC 100 ksps 10 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFD VREF0 Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 0 D0 P7 7 D7 P7 DRV P5 0 A8 P5 7 A15 P5 DRV P6 0 A0 P6 7 A7 P6 DRV P4 DRV P4 5 ALE P4 6 RD P4 7 WR P4 0 P4 4...

Page 24: ... P1 Drv P2 Drv Data Bus Address Bus Bus Control DAC1 DAC1 12 Bit VREF DAC0 12 Bit ADC 100 ksps 10 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 DAC0 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv 8 1 MONEN WDT VREFA Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 DRV P5 DRV P6 DRV P4 DRV Prog Gain ADC 500 ksps 8 Bit A M U X VREFA AV XTA...

Page 25: ... P2 Drv Data Bus Address Bus Bus Control VREF ADC 100ksps 10 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv MONEN WDT VREF0 Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 0 D0 P7 7 D7 P7 DRV P5 0 A8 P5 7 A15 P5 DRV P6 0 A0 P6 7 A7 P6 DRV P4 DRV P4 5 ALE P4 6 RD P4 7 WR P4 0 P4 4 XTAL1 XTAL2...

Page 26: ... 0 AIN2 0 P1 7 AIN2 7 P0 0 P0 7 P1 Drv P2 Drv Data Bus Address Bus Bus Control VREF ADC 100ksps 10 Bit A M U X AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 CP0 CP0 CP1 CP1 VREF TEMP SENSOR UART0 P3 0 P3 7 P3 Drv MONEN WDT VREF0 Prog Gain CP0 CP1 C T L P4 Latch D a t a P7 Latch A d d r P5 Latch P6 Latch P7 DRV P5 DRV P6 DRV P4 DRV XTAL1 XTAL2 External Oscillator Circuit System Clock Cali...

Page 27: ...pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 MHz By contrast the CIP 51 core exe cutes 70 of its instructions in one or two system clock cycles with only four instructions taking more than fo...

Page 28: ... disabled by the user in software the VDD monitor is enabled disabled via the MONEN pin The Watchdog Timer may be permanently enabled in software after a power on reset during MCU ini tialization The MCU has an internal stand alone clock generator which is used by default as the system clock after any reset If desired the clock source may be switched on the fly to the external oscillator which can...

Page 29: ...he C8051F12x and C8051F130 1 the MCU s program memory consists of 128 k bytes of banked Flash memory The 1024 bytes from addresses 0x1FC00 to 0x1FFFF are reserved On the C8051F132 3 the MCU s program memory consists of 64 k bytes of Flash memory This memory may be reprogrammed in system in 1024 byte sectors and requires no special off chip programming voltage On all devices there are also two 128 ...

Page 30: ...der to keep them synchronized The C8051F120DK development kit provides all the hardware and software necessary to develop applica tion code and perform in circuit debugging with the C8051F12x or C8051F13x MCUs The kit includes a Windows 95 or later development environment a serial adapter for connecting to the JTAG port and a target application board with a C8051F120 MCU installed All of the neces...

Page 31: ...SYSCLK cycles A rounding engine provides a rounded 16 bit fractional result after an addi tional third SYSCLK cycle MAC0 also contains a 1 bit arithmetic shifter that will left or right shift the con tents of the 40 bit accumulator in a single SYSCLK cycle Figure 1 10 MAC0 Block Diagram MAC0CF MAC0MS MAC0FM MAC0SAT MAC0CA MAC0SD MAC0SC MAC0STA MAC0N MAC0SO MAC0Z MAC0HO 16 x 16 Multiply MAC0RNDH MA...

Page 32: ...iplexed digital I O all combinations of functions are supported The on chip counter timers serial buses HW interrupts ADC Start of Conversion inputs comparator out puts and other digital signals in the controller can be configured to appear on the Port I O pins specified in the Crossbar Control registers This allows the user to select the exact mix of general purpose Port I O and digital resources...

Page 33: ...lator or 16 Bit Pulse Width Modulator The PCA Capture Compare Module I O and External Clock Input are routed to the MCU Port I O via the Digital Crossbar Figure 1 12 PCA Block Diagram 1 7 Serial Ports Serial peripherals included on the devices are two Enhanced Full Duplex UARTs SPI Bus and SMBus I2C Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP 51 s i...

Page 34: ...age can be especially useful when different ADC input channels have widely varied input voltage signals or when it is necessary to zoom in on a signal with a large DC offset in dif ferential mode a DAC could be used to provide the DC offset Conversions can be started in four ways a software command an overflow of Timer 2 an overflow of Timer 3 or an external signal input This flexibility allows th...

Page 35: ...rent ADC input channels have widely varied input voltage signals or when it is necessary to zoom in on a signal with a large DC offset in differential mode a DAC could be used to provide the DC offset The PGA gain can be set in software to 0 5 1 2 or 4 A flexible conversion scheduling system allows ADC2 conversions to be initiated by software commands timer overflows or an external input signal AD...

Page 36: ...ed by a software write or scheduled on a Timer 2 3 or 4 overflow The DAC voltage reference is supplied from the dedicated VREFD input pin on the 100 pin TQFP devices or via the internal Voltage reference on the 64 pin TQFP devices The DACs are especially useful as references for the comparators or offsets for the differential inputs of the ADCs Figure 1 15 DAC System Block Diagram DAC0 AV 12 AGND ...

Page 37: ...ing edge falling edge or both The interrupts are capable of waking up the MCU from sleep mode and Comparator 0 can be used as a reset source The output state of the comparators can be polled in software or routed to Port I O pins via the Crossbar The comparators can be programmed to a low power shutdown mode when not in use Figure 1 16 Comparator Block Diagram CPn CPn CIP 51 and Interrupt Handler ...

Page 38: ...through VDD AV DGND and AGND 800 mA Maximum Output Current Sunk by any Port pin 100 mA Maximum Output Current Sunk by any other I O pin 50 mA Maximum Output Current Sourced by any Port pin 100 mA Maximum Output Current Sourced by any other I O Pin 50 mA Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and function...

Page 39: ... 7 3 0 3 0 3 3 3 6 3 6 V V Digital Supply Current with CPU active VDD 3 0 V Clock 100 MHz VDD 3 0 V Clock 50 MHz VDD 3 0 V Clock 1 MHz VDD 3 0 V Clock 32 kHz 65 35 1 33 mA mA mA µA Digital Supply Current with CPU inactive not accessing Flash VDD 3 0 V Clock 100 MHz VDD 3 0 V Clock 50 MHz VDD 3 0 V Clock 1 MHz VDD 3 0 V Clock 32 kHz 40 20 0 4 15 mA mA mA µA Digital Supply Current shut down Oscillat...

Page 40: ...6 V Digital Supply Current with CPU active VDD 3 0 V Clock 50 MHz VDD 3 0 V Clock 1 MHz VDD 3 0 V Clock 32 kHz 35 1 33 mA mA µA Digital Supply Current with CPU inactive not accessing Flash VDD 3 0 V Clock 50 MHz VDD 3 0 V Clock 1 MHz VDD 3 0 V Clock 32 kHz 27 0 4 15 mA mA µA Digital Supply Current shut down Oscillator not running 0 4 µA Digital Supply RAM Data Retention Voltage 1 5 V SYSCLK System...

Page 41: ...Test Data Output with internal pullup Data is shifted out on TDO on the falling edge of TCK TDO output is a tri state driver RST 5 62 5 62 D I O Device Reset Open drain output of internal VDD monitor Is driven low when VDD is VRST and MONEN is high An external source can initiate a system reset by driving this pin low XTAL1 26 17 26 17 A In Crystal Input This pin is the return for the inter nal os...

Page 42: ...put Channel 3 See ADC0 Specification for complete description AIN0 4 22 13 22 13 A In ADC0 Input Channel 4 See ADC0 Specification for complete description AIN0 5 23 14 23 14 A In ADC0 Input Channel 5 See ADC0 Specification for complete description AIN0 6 24 15 24 15 A In ADC0 Input Channel 6 See ADC0 Specification for complete description AIN0 7 25 16 25 16 A In ADC0 Input Channel 7 See ADC0 Speci...

Page 43: ...e for External Memory Address bus multiplexed mode Port 0 5 See Port Input Output section for complete description RD P0 6 56 49 56 49 D I O RD Strobe for External Memory Address bus Port 0 6 See Port Input Output section for complete description WR P0 7 55 48 55 48 D I O WR Strobe for External Memory Address bus Port 0 7 See Port Input Output section for complete description AIN2 0 A8 P1 0 36 29 ...

Page 44: ...s Multiplexed mode Bit 0 External Memory Address bus Non multi plexed mode Port 2 0 See Port Input Output section for complete description A9m A1 P2 1 45 36 45 36 D I O Port 2 1 See Port Input Output section for com plete description A10m A2 P2 2 44 35 44 35 D I O Port 2 2 See Port Input Output section for com plete description A11m A3 P2 3 43 34 43 34 D I O Port 2 3 See Port Input Output section ...

Page 45: ...ption AD5 D5 P3 5 49 42 49 42 D I O Port 3 5 See Port Input Output section for com plete description AD6 D6 P3 6 48 39 48 39 D I O Port 3 6 See Port Input Output section for com plete description AD7 D7 P3 7 47 38 47 38 D I O Port 3 7 See Port Input Output section for com plete description P4 0 98 98 D I O Port 4 0 See Port Input Output section for com plete description P4 1 97 97 D I O Port 4 1 S...

Page 46: ...tion for complete description A9 P5 1 87 87 D I O Port 5 1 See Port Input Output section for com plete description A10 P5 2 86 86 D I O Port 5 2 See Port Input Output section for com plete description A11 P5 3 85 85 D I O Port 5 3 See Port Input Output section for com plete description A12 P5 4 84 84 D I O Port 5 4 See Port Input Output section for com plete description A13 P5 5 83 83 D I O Port 5...

Page 47: ...lete description A14m A6 P6 6 74 74 D I O Port 6 6 See Port Input Output section for com plete description A15m A7 P6 7 73 73 D I O Port 6 7 See Port Input Output section for com plete description AD0 D0 P7 0 72 72 D I O Bit 0 External Memory Address Data bus Multi plexed mode Bit 0 External Memory Data bus Non multi plexed mode Port 7 0 See Port Input Output section for complete description AD1 D...

Page 48: ...D6 D6 P7 6 66 66 D I O Port 7 6 See Port Input Output section for com plete description AD7 D7 P7 7 65 65 D I O Port 7 7 See Port Input Output section for com plete description NC 15 17 99 100 63 64 No Connection Table 4 1 Pin Definitions Continued Name Pin Numbers Type Description F120 F122 F124 F126 F121 F123 F125 F127 F130 F132 F131 F133 ...

Page 49: ...3 D3 P3 3 A13m A5 P6 5 A14m A6 P6 6 A15m A7 P6 7 AD0 D0 P7 0 AD1 D1 P7 1 AD2 D2 P7 2 AD3 D3 P7 3 AD4 D4 P7 4 AD5 D5 P7 5 DAC0 DAC1 P4 0 P4 1 P4 2 P4 3 P4 4 ALE P4 5 RD P4 6 WR P4 7 VDD DGND A8 P5 0 A9 P5 1 A10 P5 2 A11 P5 3 A12 P5 4 A13 P5 5 A14 P5 6 A15 P5 7 A8m A0 P6 0 A9m A1 P6 1 A10m A2 P6 2 A11m A3 P6 3 A12m A4 P6 4 AGND AV VREF AGND AV VREFD VREF0 VREF2 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN...

Page 50: ... 3 A13m A5 P6 5 A14m A6 P6 6 A15m A7 P6 7 AD0 D0 P7 0 AD1 D1 P7 1 AD2 D2 P7 2 AD3 D3 P7 3 AD4 D4 P7 4 AD5 D5 P7 5 NC NC P4 0 P4 1 P4 2 P4 3 P4 4 ALE P4 5 RD P4 6 WR P4 7 VDD DGND A8 P5 0 A9 P5 1 A10 P5 2 A11 P5 3 A12 P5 4 A13 P5 5 A14 P5 6 A15 P5 7 A8m A0 P6 0 A9m A1 P6 1 A10m A2 P6 2 A11m A3 P6 3 A12m A4 P6 4 AGND AV VREF AGND AV NC VREF0 NC AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7...

Page 51: ... 1 2 3 Rev 1 4 51 Figure 4 3 TQFP 100 Package Drawing A A1 A2 b D D1 e E E1 L 0 05 0 95 0 17 0 45 1 00 0 22 16 00 14 00 0 50 16 00 14 00 0 60 1 20 0 15 1 05 0 27 0 75 MIN mm NOM mm MAX mm 100 e A1 b A2 A PIN 1 DESIGNATOR 1 E1 E D1 D L ...

Page 52: ...C1 RST TDO TDI TCK TMS VDD DGND P0 0 P0 1 P0 2 P0 3 P0 4 ALE P0 5 RD P0 6 WR P0 7 AD0 D0 P3 0 AD1 D1 P3 1 AD2 D2 P3 2 AD3 D3 P3 3 AD4 D4 P3 4 AD5 D5 P3 5 VDD DGND AD6 D6 P3 6 AD7 D7 P3 7 A8m A0 P2 0 A9m A1 P2 1 A10m A2 P2 2 A11m A3 P2 3 A12m A4 P2 4 CP1 CP1 CP0 CP0 AGND AV VREF VREFA AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 XTAL1 XTAL2 MONEN AIN2 7 A15 P1 7 AIN2 6 A14 P1 6 AIN2 5 A1...

Page 53: ... TCK TMS VDD DGND P0 0 P0 1 P0 2 P0 3 P0 4 ALE P0 5 RD P0 6 WR P0 7 AD0 D0 P3 0 AD1 D1 P3 1 AD2 D2 P3 2 AD3 D3 P3 3 AD4 D4 P3 4 AD5 D5 P3 5 VDD DGND AD6 D6 P3 6 AD7 D7 P3 7 A8m A0 P2 0 A9m A1 P2 1 A10m A2 P2 2 A11m A3 P2 3 A12m A4 P2 4 CP1 CP1 CP0 CP0 AGND AV VREF VREF0 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 XTAL1 XTAL2 MONEN AIN2 7 A15 P1 7 AIN2 6 A14 P1 6 AIN2 5 A13 P1 5 AIN2 4 ...

Page 54: ...0 1 2 3 54 Rev 1 4 Figure 4 6 TQFP 64 Package Drawing A A1 A2 b D D1 e E E1 L 0 05 0 95 0 17 0 45 1 00 0 22 12 00 10 00 0 50 12 00 10 00 0 60 1 20 0 15 1 05 0 27 0 75 MIN mm NOM mm MAX mm 1 64 E E1 e A1 b D D1 PIN 1 DESIGNATOR A2 A L ...

Page 55: ...igure 5 2 AMUX input pairs can be programmed to operate in either differential or single ended mode This allows the user to select the best measurement technique for each input channel and even accommodates mode changes on the fly The AMUX defaults to all single ended inputs upon reset There are two registers associated with the AMUX the Channel Selection register AMX0SL SFR Definition 5 2 and the...

Page 56: ...lected by bits AMX0AD3 0 in register AMX0SL this voltage will be amplified by the PGA according to the user programmed PGA settings Typical values for the Slope and Offset parameters can be found in Table 5 1 Figure 5 2 Typical Temperature Sensor Transfer Function 0 50 50 100 Temperature Celsius Voltage VTEMP Slope x TempC Offset Offset V at 0 Celsius Slope V deg C TempC VTEMP Offset Slope ...

Page 57: ... conversion is complete The falling edge of AD0BUSY triggers an interrupt when enabled and sets the AD0INT interrupt flag ADC0CN 5 Converted data is available in the ADC0 data word MSB and LSB registers ADC0H ADC0L Converted data can be either left or right justified in the ADC0H ADC0L register pair see example in Figure 5 5 depending on the programmed state of the AD0LJST bit in the ADC0CN regist...

Page 58: ... shutdown when the entire chip is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX or PGA settings are frequently changed to ensure that settling time requirements are met see Section 5 2 3 Settling Time Requirements on page 59 Figure 5 3 ADC0 Track and Conversion Example Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CNVSTR0 AD0CM 1 0 10 ADC0TM 1 ADC0TM 0 ...

Page 59: ...uces to RMUX An absolute minimum settling time of 1 5 µs is required after any MUX or PGA selection Note that in low power track ing mode three SAR clocks are used for tracking at the start of every conversion For most applications these three SAR clocks will meet the tracking requirements Equation 5 1 ADC0 Settling Time Requirements Where SA is the settling accuracy given as a fraction of an LSB ...

Page 60: ... AIN0 5 are respectively differential input pair Bit1 AIN23IC AIN0 2 AIN0 3 Input Pair Configuration Bit 0 AIN0 2 and AIN0 3 are independent single ended inputs 1 AIN0 2 AIN0 3 are respectively differential input pair Bit0 AIN01IC AIN0 0 AIN0 1 Input Pair Configuration Bit 0 AIN0 0 and AIN0 1 are independent single ended inputs 1 AIN0 0 AIN0 1 are respectively differential input pair Note The ADC0...

Page 61: ...AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0100 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0101 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0110 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0111 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 1000 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 10...

Page 62: ...C0 SAR Conversion Clock should be less than or equal to 2 5 MHz When the AD0SC bits are equal to 00000b the SAR Conversion clock is equal to SYSCLK to facilitate faster ADC conversions at slower SYSCLK speeds Bits2 0 AMP0GN2 0 ADC0 Internal Amplifier Gain PGA 000 Gain 1 001 Gain 2 010 Gain 4 011 Gain 8 10x Gain 16 11x Gain 0 5 SFR Page SFR Address 0 0xBC R W R W R W R W R W R W R W R W Reset Value...

Page 63: ...y write of 1 to AD0BUSY 01 ADC0 conversion initiated on overflow of Timer 3 10 ADC0 conversion initiated on rising edge of external CNVSTR0 11 ADC0 conversion initiated on overflow of Timer 2 If AD0TM 1 00 Tracking starts with the write of 1 to AD0BUSY and lasts for 3 SAR clocks followed by conversion 01 Tracking started by the overflow of Timer 3 and lasts for 3 SAR clocks followed by con version...

Page 64: ...0 are the most significant bits of the 12 bit ADC0 Data Word SFR Page SFR Address 0 0xBF R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 ADC0 Data Word Low Order Bits For AD0LJST 0 Bits 7 0 are the lower 8 bits of the 12 bit ADC0 Data Word For AD0LJST 1 Bits 7 4 are the lower 4 bits of the 12 bit ADC0 Data Word Bits 3 0 will always read 0 SFR Pa...

Page 65: ...0CF 0x00 AMX0SL 0x00 Example ADC0 Data Word Conversion Map AIN0 0 AIN0 1 Differential Input Pair AMX0CF 0x01 AMX0SL 0x00 For AD0LJST 0 n 12 for Single Ended n 11 for Differential AIN0 0 AGND Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0LJST 1 VREF x 4095 4096 0x0FFF 0xFFF0 VREF 2 0x0800 0x8000 VREF x 2047 4096 0x07FF 0x7FF0 0 0x0000 0x0000 AIN0 0 AIN0 1 Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0LJS...

Page 66: ...n and ADC0 Less Than registers ADC0GTH ADC0GTL ADC0LTH and ADC0LTL Reference comparisons are shown starting on page 68 Notice that the window detector flag can be asserted when the measured data is inside or out side the user programmed limits depending on the programming of the ADC0GTx and ADC0LTx regis ters SFR Definition 5 7 ADC0GTH ADC0 Greater Than Data High Byte SFR Definition 5 8 ADC0GTL AD...

Page 67: ...an Data Low Byte Bits7 0 High byte of ADC0 Less Than Data Word SFR Page SFR Address 0 0xC7 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 Low byte of ADC0 Less Than Data Word SFR Page SFR Address 0 0xC6 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ...

Page 68: ...TL 0x0100 ADC0GTH ADC0GTL 0x0200 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0200 or 0x0100 0x0FFF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 AD0WINT 1 AD0WINT not affected AD0WINT not affected ADC Data Word 0x0FFF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 AD0WINT 1 AD0WINT not affected AD0WINT 1 ADC0LTH ADC0LTL ...

Page 69: ...a Word ADC0LTH ADC0LTL ADC0GTH ADC0GTL REF x 256 2048 REF x 1 2048 REF Input Voltage AD0 0 AD0 1 REF x 2047 2048 REF x 256 2048 REF x 1 2048 Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 0 ADC0LTH ADC0LTL 0x0100 ADC0GTH ADC0GTL 0xFFFF An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0100 and 0xFFFF In 2s complement math 0xFFFF 1 Given AMX...

Page 70: ...ADC0GTL ADC0LTH ADC0LTL 0 Input Voltage AD0 0 AGND REF x 4095 4096 REF x 256 4096 REF x 512 4096 0 Input Voltage AD0 0 AGND REF x 4095 4096 REF x 256 4096 REF x 512 4096 Given AMX0SL 0x00 AMX0CF 0x00 AD0LJST 1 ADC0LTH ADC0LTL 0x2000 ADC0GTH ADC0GTL 0x1000 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x2000 and 0x1000 Given AMX0S...

Page 71: ...ord ADC Data Word ADC0LTH ADC0LTL ADC0GTH ADC0GTL REF x 256 2048 REF x 1 2048 REF Input Voltage AD0 0 AD0 1 REF x 2047 2048 REF x 256 2048 REF x 1 2048 Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 1 ADC0LTH ADC0LTL 0x1000 ADC0GTH ADC0GTL 0xFFF0 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x1000 and 0xFFF0 2s complement math Given AMX0...

Page 72: ...istortion 66 dB Total Harmonic Distortion Up to the 5th harmonic 75 dB Spurious Free Dynamic Range 80 dB Conversion Rate SAR Clock Frequency 2 5 MHz Conversion Time in SAR Clocks 16 clocks Track Hold Acquisition Time 1 5 µs Throughput Rate 100 ksps Analog Inputs Input Voltage Range Single ended operation 0 VREF V Common mode Voltage Range Differential operation AGND AV V Input Capacitance 10 pF Te...

Page 73: ... is shown in Figure 6 2 AMUX input pairs can be programmed to operate in either differential or single ended mode This allows the user to select the best measurement technique for each input channel and even accommodates mode changes on the fly The AMUX defaults to all single ended inputs upon reset There are two registers associated with the AMUX the Channel Selection register AMX0SL SFR Definiti...

Page 74: ...lected by bits AMX0AD3 0 in register AMX0SL this voltage will be amplified by the PGA according to the user programmed PGA settings Typical values for the Slope and Offset parameters can be found in Table 6 1 Figure 6 2 Typical Temperature Sensor Transfer Function 0 50 50 100 Temperature Celsius Voltage VTEMP Slope x TempC Offset Offset V at 0 Celsius Slope V deg C TempC VTEMP Offset Slope ...

Page 75: ... conversion is complete The falling edge of AD0BUSY triggers an interrupt when enabled and sets the AD0INT interrupt flag ADC0CN 5 Converted data is available in the ADC0 data word MSB and LSB registers ADC0H ADC0L Converted data can be either left or right justified in the ADC0H ADC0L register pair see example in Figure 6 5 depending on the programmed state of the AD0LJST bit in the ADC0CN regist...

Page 76: ... shutdown when the entire chip is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX or PGA settings are frequently changed to ensure that settling time requirements are met see Section 6 2 3 Settling Time Requirements on page 77 Figure 6 3 ADC0 Track and Conversion Example Timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CNVSTR0 AD0CM 1 0 10 ADC0TM 1 ADC0TM 0 ...

Page 77: ...uces to RMUX An absolute minimum settling time of 1 5 µs is required after any MUX or PGA selection Note that in low power track ing mode three SAR clocks are used for tracking at the start of every conversion For most applications these three SAR clocks will meet the tracking requirements Equation 6 1 ADC0 Settling Time Requirements Where SA is the settling accuracy given as a fraction of an LSB ...

Page 78: ... AIN0 5 are respectively differential input pair Bit1 AIN23IC AIN0 2 AIN0 3 Input Pair Configuration Bit 0 AIN0 2 and AIN0 3 are independent single ended inputs 1 AIN0 2 AIN0 3 are respectively differential input pair Bit0 AIN01IC AIN0 0 AIN0 1 Input Pair Configuration Bit 0 AIN0 0 and AIN0 1 are independent single ended inputs 1 AIN0 0 AIN0 1 are respectively differential input pair Note The ADC0...

Page 79: ...AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0100 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0101 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0110 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 0111 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 1000 AIN0 0 AIN0 1 AIN0 2 AIN0 3 AIN0 4 AIN0 5 AIN0 6 AIN0 7 TEMP SENSOR 10...

Page 80: ... SAR Conversion Clock should be less than or equal to 2 5 MHz When the AD0SC bits are equal to 00000b the SAR Conversion clock is equal to SYSCLK to facilitate faster ADC conversions at slower SYSCLK speeds Bits2 0 AMP0GN2 0 ADC0 Internal Amplifier Gain PGA 000 Gain 1 001 Gain 2 010 Gain 4 011 Gain 8 10x Gain 16 11x Gain 0 5 SFR Page SFR Address 0 0xBC R W R W R W R W R W R W R W R W Reset Value A...

Page 81: ...y write of 1 to AD0BUSY 01 ADC0 conversion initiated on overflow of Timer 3 10 ADC0 conversion initiated on rising edge of external CNVSTR0 11 ADC0 conversion initiated on overflow of Timer 2 If AD0TM 1 00 Tracking starts with the write of 1 to AD0BUSY and lasts for 3 SAR clocks followed by conversion 01 Tracking started by the overflow of Timer 3 and lasts for 3 SAR clocks followed by con version...

Page 82: ...0 are the most significant bits of the 10 bit ADC0 Data Word SFR Page SFR Address 0 0xBF R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 ADC0 Data Word Low Order Bits For AD0LJST 0 Bits 7 0 are the lower 8 bits of the 10 bit ADC0 Data Word For AD0LJST 1 Bits 7 4 are the lower 4 bits of the 10 bit ADC0 Data Word Bits 3 0 will always read 0 SFR Pa...

Page 83: ... AMX0CF 0x00 AMX0SL 0x00 Example ADC0 Data Word Conversion Map AIN0 0 AIN0 1 Differential Input Pair AMX0CF 0x01 AMX0SL 0x00 For AD0LJST 0 n 10 for Single Ended n 9 for Differential AIN0 0 AGND Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0LJST 1 VREF x 1023 1024 0x03FF 0xFFC0 VREF 2 0x0200 0x8000 VREF x 511 1024 0x01FF 0x7FC0 0 0x0000 0x0000 AIN0 0 AIN0 1 Volts ADC0H ADC0L AD0LJST 0 ADC0H ADC0L AD0L...

Page 84: ...n and ADC0 Less Than registers ADC0GTH ADC0GTL ADC0LTH and ADC0LTL Reference comparisons are shown starting on page 87 Notice that the window detector flag can be asserted when the measured data is inside or out side the user programmed limits depending on the programming of the ADC0GTx and ADC0LTx regis ters SFR Definition 6 7 ADC0GTH ADC0 Greater Than Data High Byte SFR Definition 6 8 ADC0GTL AD...

Page 85: ...an Data Low Byte Bits7 0 High byte of ADC0 Less Than Data Word SFR Page SFR Address 0 0xC7 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 Low byte of ADC0 Less Than Data Word SFR Page SFR Address 0 0xC6 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ...

Page 86: ...C0LTL 0x0100 ADC0GTH ADC0GTL 0x0200 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0200 or 0x0100 0x03FF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 ADWINT 1 ADWINT not affected ADWINT not affected ADC Data Word 0x03FF 0x0201 0x0200 0x01FF 0x0101 0x0100 0x00FF 0x0000 ADWINT 1 ADWINT not affected ADWINT 1 ADC0LTH ADC0LTL ADC...

Page 87: ... Word ADC0LTH ADC0LTL ADC0GTH ADC0GTL REF x 256 512 REF x 1 512 REF Input Voltage AD0 0 AD0 1 REF x 511 512 REF x 256 512 REF x 1 512 Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 0 ADC0LTH ADC0LTL 0x0100 ADC0GTH ADC0GTL 0xFFFF An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x0100 and 0xFFFF In 2s complement math 0xFFFF 1 Given AMX0SL 0x0...

Page 88: ...0GTL ADC0LTH ADC0LTL 0 Input Voltage AD0 0 AGND REF x 1023 1024 REF x 256 1024 REF x 512 1024 0 Input Voltage AD0 0 AGND REF x 1023 1024 REF x 256 1024 REF x 512 1024 Given AMX0SL 0x00 AMX0CF 0x00 AD0LJST 1 ADC0LTH ADC0LTL 0x2000 ADC0GTH ADC0GTL 0x1000 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x2000 and 0x1000 Given AMX0SL 0...

Page 89: ...rd ADC Data Word ADC0LTH ADC0LTL ADC0GTH ADC0GTL REF x 128 512 REF x 1 512 REF Input Voltage AD0 0 AD0 1 REF x 511 512 REF x 128 512 REF x 1 512 Given AMX0SL 0x00 AMX0CF 0x01 AD0LJST 1 ADC0LTH ADC0LTL 0x2000 ADC0GTH ADC0GTL 0xFFC0 An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt AD0WINT 1 if the resulting ADC0 Data Word is 0x2000 and 0xFFC0 2s complement math Given AMX0SL 0x00...

Page 90: ...se Plus Distortion 59 dB Total Harmonic Distortion Up to the 5th harmonic 70 dB Spurious Free Dynamic Range 80 dB Conversion Rate SAR Clock Frequency 2 5 MHz Conversion Time in SAR Clocks 16 clocks Track Hold Acquisition Time 1 5 µs Throughput Rate 100 ksps Analog Inputs Input Voltage Range Single ended operation 0 VREF V Common mode Voltage Range Differential operation AGND AV V Input Capacitance...

Page 91: ...C2 output signal by an amount determined by the states of the AMP2GN2 0 bits in the ADC2 Configuration register ADC2CF SFR Definition 7 3 The PGA can be soft ware programmed for gains of 0 5 1 2 or 4 Gain defaults to 0 5 on reset Important Note AIN2 pins also function as Port 1 I O pins and must be configured as analog inputs when used as ADC2 inputs To configure an AIN2 pin for analog input set t...

Page 92: ...ing a 1 to AD2BUSY it is recommended to poll AD2INT to determine when the conversion is complete The recommended procedure is Step 1 Write a 0 to AD2INT Step 2 Write a 1 to AD2BUSY Step 3 Poll AD2INT for 1 Step 4 Process ADC2 data When CNVSTR2 is used as a conversion start source it must be enabled in the crossbar and the corre sponding pin must be set to open drain high impedance mode see Section...

Page 93: ... 1xx AD2TM 1 AD2TM 0 SAR Clocks 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 SAR Clocks Track Convert Low Power Mode Low Power or Convert Track or Convert Convert Track B ADC Timing for Internal Trigger Source 1 2 3 4 5 6 7 8 9 CNVSTR2 AD2CM 2 0 010 AD2TM 1 A ADC Timing for External Trigger Source SAR Clocks Track or Convert Convert Track AD2TM 0 Track Convert Low Power Mode Low Power or Convert ...

Page 94: ...racking mode three SAR2 clocks are used for tracking at the start of every conversion For most applications these three SAR2 clocks will meet the tracking requirements Equation 7 1 ADC2 Settling Time Requirements Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle within 1 4 LSB t is the required settling time in seconds RTOTAL is the sum of the ADC2 MUX resi...

Page 95: ... AIN2 5 are respectively differential input pair Bit1 PIN23IC AIN2 2 AIN2 3 Input Pair Configuration Bit 0 AIN2 2 and AIN2 3 are independent single ended inputs 1 AIN2 2 and AIN2 3 are respectively differential input pair Bit0 PIN01IC AIN2 0 AIN2 1 Input Pair Configuration Bit 0 AIN2 0 and AIN2 1 are independent single ended inputs 1 AIN2 0 and AIN2 1 are respectively differential input pair Note ...

Page 96: ...6 AIN2 7 0011 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0100 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0101 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0110 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 0111 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 1000 AIN2 0 AIN2 1 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN2 6 AIN2 7 1001 AIN2 0 AIN2 1 AIN2 2...

Page 97: ...e held in AD2SC4 0 and CLKSAR2 refers to the desired ADC2 SAR clock Note the ADC2 SAR Conversion Clock should be less than or equal to 6 MHz Bit2 UNUSED Read 0b Write don t care Bits1 0 AMP2GN1 0 ADC2 Internal Amplifier Gain PGA 00 Gain 0 5 01 Gain 1 10 Gain 2 11 Gain 4 SFR Page SFR Address 2 0xBC R W R W R W R W R W R W R W R W Reset Value AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 AMP2GN1 AMP2GN0 111110...

Page 98: ...on every write of 1 to AD2BUSY 001 ADC2 conversion initiated on overflow of Timer 3 010 ADC2 conversion initiated on rising edge of external CNVSTR2 011 ADC2 conversion initiated on overflow of Timer 2 1xx ADC2 conversion initiated on write of 1 to AD0BUSY synchronized with ADC0 soft ware commanded conversions AD2TM 1 000 Tracking initiated on write of 1 to AD2BUSY for 3 SAR2 clocks followed by co...

Page 99: ...d Register as follows Example ADC2 Data Word Conversion Map Single Ended AIN2 0 Input AMX2CF 0x00 AMX2SL 0x00 Differential Example 8 bit ADC Data Word appears in the ADC2 Data Word Register as follows Example ADC2 Data Word Conversion Map Differential AIN2 0 AIN2 1 Input AMX2CF 0x01 AMX2SL 0x00 AIN2 0 AGND Volts ADC2 VREF 255 256 0xFF VREF 128 256 0x80 VREF 64 256 0x40 0 0x00 AIN2 0 AIN2 1 Volts A...

Page 100: ...nding on the contents of the ADC2LT and ADC2GT registers 7 3 1 Window Detector In Single Ended Mode Figure 7 5 shows two example window comparisons for Single ended mode with ADC2LT 0x20 and ADC2GT 0x10 Notice that in Single ended mode the codes vary from 0 to VREF 255 256 and are represented as 8 bit unsigned integers In the left example an AD2WINT interrupt will be generated if the ADC2 conversi...

Page 101: ...2GT and ADC2LT if 0xFF 1d ADC2 0x0F 16d In the right example an AD2WINT interrupt will be gener ated if ADC2 is outside of the range defined by ADC2GT and ADC2LT if ADC2 0xFF 1d or ADC2 0x10 16d Figure 7 6 ADC2 Window Compare Examples Differential Mode 0x7F 127d 0x11 17d 0x10 16d 0x0F 15d 0x00 0d 0xFF 1d 0xFE 2d 0x80 128d REF Input Voltage AIN2 x AIN2 y REF x 127 128 REF x 16 128 REF x 1 256 0x7F ...

Page 102: ...DC2 Less Than Data Byte Bits7 0 ADC2 Greater Than Data Word SFR Page SFR Address 2 0xC4 R W R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 ADC2 Less Than Data Word SFR Page SFR Address 2 0xC6 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ...

Page 103: ...de 1 0 2 LSB Offset Temperature Coefficient 10 ppm C Dynamic Performance 10 kHz sine wave input 1 dB below Full Scale 500 ksps Signal to Noise Plus Distortion 45 47 dB Total Harmonic Distortion Up to the 5th harmonic 51 dB Spurious Free Dynamic Range 52 dB Conversion Rate SAR Clock Frequency 6 MHz Conversion Time in SAR Clocks 8 clocks Track Hold Acquisition Time 300 ns Throughput Rate 500 ksps An...

Page 104: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 104 Rev 1 4 NOTES ...

Page 105: ...y be driven by the internal voltage reference or an external source If the internal voltage reference is used it must be enabled in order for the DAC outputs to be valid See Section 9 Voltage Reference on page 113 for more information on configuring the voltage reference for the DACs 8 1 DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full scale...

Page 106: ...an output update event This feature is useful in systems where the DAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the DAC output When the DAC0MD bits DAC0CN 4 3 are set to 01 10 or 11 writes to both DAC data regis ters DAC0L and DAC0H are held until an associated Timer overflow event ...

Page 107: ...Bits7 0 DAC0 Data Word Most Significant Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD3 0 Bits7 0 DAC0 Data Word Least Significant Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD2 0 ...

Page 108: ...d is in DAC0H 3 0 while the least significant byte is in DAC0L 001 The most significant 5 bits of the DAC0 Data Word is in DAC0H 4 0 while the least significant 7 bits are in DAC0L 7 1 010 The most significant 6 bits of the DAC0 Data Word is in DAC0H 5 0 while the least significant 6 bits are in DAC0L 7 2 011 The most significant 7 bits of the DAC0 Data Word is in DAC0H 6 0 while the least signifi...

Page 109: ...Bits7 0 DAC1 Data Word Most Significant Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD3 1 Bits7 0 DAC1 Data Word Least Significant Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD2 1 ...

Page 110: ... is in DAC1H 3 0 while the least significant byte is in DAC1L 001 The most significant 5 bits of the DAC1 Data Word is in DAC1H 4 0 while the least significant 7 bits are in DAC1L 7 1 010 The most significant 6 bits of the DAC1 Data Word is in DAC1H 5 0 while the least significant 6 bits are in DAC1L 7 2 011 The most significant 7 bits of the DAC1 Data Word is in DAC1H 6 0 while the least signific...

Page 111: ...4 3 30 mV Offset Tempco 6 ppm C Full Scale Error 20 60 mV Full Scale Error Tempco 10 ppm C VDD Power Supply Rejection Ratio 60 dB Output Impedance in Shutdown Mode DACnEN 0 100 kΩ Output Sink Current 300 µA Output Short Circuit Current Data Word 0xFFF 15 mA Dynamic Performance Voltage Output Slew Rate Load 40 pF 0 44 V µs Output Settling Time to 1 2 LSB Load 40 pF Output swing from code 0xFFF to 0...

Page 112: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 112 Rev 1 4 NOTES ...

Page 113: ...ogic 1 If the internal reference is not used REFBE may be set to logic 0 Note that the BIASE bit must be set to logic 1 if any DACs or ADCs are used regardless of whether the voltage reference is derived from the on chip reference or supplied by an off chip source If no ADCs or DACs are being used both of these bits can be set to logic 0 to conserve power When enabled the temperature sensor connec...

Page 114: ... from VREF0 pin 1 ADC0 voltage reference from DAC0 output Bit3 AD2VRS ADC2 Voltage Reference Select 0 ADC2 voltage reference from VREF2 pin 1 ADC2 voltage reference from AV Bit2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor Off 1 Internal Temperature Sensor On Bit1 BIASE ADC DAC Bias Generator Enable Bit Must be 1 if using ADC DAC or VREF 0 Internal Bias Generator Off 1 Interna...

Page 115: ... a voltage reference input for ADC0 and ADC2 which can be connected to an external precision reference or the internal voltage reference ADC0 may also reference the DAC0 output internally and ADC2 may refer ence the analog power supply voltage via the VREF multiplexers shown in Figure 9 2 Figure 9 2 Voltage Reference Functional Block Diagram C8051F121 3 5 7 Recommended Bypass Capacitors x2 VREF DA...

Page 116: ...ference from AV Bit2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor Off 1 Internal Temperature Sensor On Bit1 BIASE ADC DAC Bias Generator Enable Bit Must be 1 if using ADC DAC or VREF 0 Internal Bias Generator Off 1 Internal Bias Generator On Bit0 REFBE Internal Reference Buffer Enable Bit 0 Internal Reference Buffer Off 1 Internal Reference Buffer On Internal voltage reference...

Page 117: ... VREF0 4 7μF 0 1μF External Voltage Reference Circuit R1 VDD DGND Bias to ADC 1 2V Band Gap EN REF0CN REFBE BIASE TEMPE Bits7 5 UNUSED Read 000b Write don t care Bits4 3 Reserved Must be written to 0 Bit2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor Off 1 Internal Temperature Sensor On Bit1 BIASE ADC DAC Bias Generator Enable Bit Must be 1 if using ADC or VREF 0 Internal Bias ...

Page 118: ...FBE 1 Output Voltage 25 C ambient 2 36 2 43 2 48 V VREF Short Circuit Current 30 mA VREF Temperature Coefficient 15 ppm C Load Regulation Load 0 to 200 µA to AGND 0 5 ppm µA VREF Turn on Time 1 4 7 µF tantalum 0 1 µF ceramic bypass 2 ms VREF Turn on Time 2 0 1 µF ceramic bypass 20 µs VREF Turn on Time 3 no bypass cap 10 µs Reference Buffer Power Sup ply Current 40 µA Power Supply Rejection 140 ppm...

Page 119: ...r push pull modes See Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 238 for Crossbar and port initialization details Figure 10 1 Comparator Functional Block Diagram Q Q SET CLR D Q Q SET CLR D Crossbar Interrupt Handler Reset Decision Tree SYNCHRONIZER CP0 CP0 AGND CPT0CN CP0HYN0 CP0MD CP0HYN1 CP0HYP0 CP0HYP1 CP0FIF CP0RIF CP0OUT CP0EN AV CPT0MD CP0MD0 CP0MD1 CP0FIE CP0R...

Page 120: ...teresis of each comparator is software programmable via its respective Comparator control regis ter CPT0CN and CPT1CN for Comparator0 and Comparator1 respectively The user can program both the amount of hysteresis voltage referred to the input voltage and the positive and negative going sym metry of this hysteresis around the threshold voltage The output of the comparator can be polled in soft war...

Page 121: ...tive Hysteresis Voltage Programmed with CP0HYP Bits Negative Hysteresis Voltage Programmed by CP0HYN Bits VIN VIN INPUTS CIRCUIT CONFIGURATION _ CP0 CP0 CP0 VIN VIN OUT VOH Positive Hysteresis Disabled Maximum Positive Hysteresis Negative Hysteresis Disabled Maximum Negative Hysteresis OUTPUT VOL ...

Page 122: ...g 0 No Comparator0 Falling Edge has occurred since this flag was last cleared 1 Comparator0 Falling Edge has occurred Bits3 2 CP0HYP1 0 Comparator0 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 15 mV Bits1 0 CP0HYN1 0 Comparator0 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Neg...

Page 123: ...ator 0 Falling Edge Interrupt Enable Bit 0 Comparator 0 falling edge interrupt disabled 1 Comparator 0 falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CP0MD1 CP0MD0 Comparator0 Mode Select These bits select the response time for Comparator0 SFR Page SFR Address 1 0x89 R W R W R W R W R W R W R W R W Reset Value CP0RIE CP0FIE CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit...

Page 124: ...o Comparator1 Falling Edge has occurred since this flag was last cleared 1 Comparator1 Falling Edge Interrupt has occurred Bits3 2 CP1HYP1 0 Comparator1 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 15 mV Bits1 0 CP1HYN1 0 Comparator1 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 0...

Page 125: ...ator 0 Falling Edge Interrupt Enable Bit 0 Comparator 1 falling edge interrupt disabled 1 Comparator 1 falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CP1MD1 CP1MD0 Comparator1 Mode Select These bits select the response time for Comparator1 SFR Page SFR Address 2 0x89 R W R W R W R W R W R W R W R W Reset Value CP1RIE CP1FIE CP1MD1 CP1MD0 00000010 Bit7 Bit6 Bit5 Bit...

Page 126: ... V Positive Hysteresis 1 CPnHYP1 0 00 0 1 mV Positive Hysteresis 2 CPnHYP1 0 01 2 4 5 7 mV Positive Hysteresis 3 CPnHYP1 0 10 4 9 13 mV Positive Hysteresis 4 CPnHYP1 0 11 10 17 25 mV Negative Hysteresis 1 CPnHYN1 0 00 0 1 mV Negative Hysteresis 2 CPnHYN1 0 01 2 4 5 7 mV Negative Hysteresis 3 CPnHYN1 0 10 4 9 13 mV Negative Hysteresis 4 CPnHYN1 0 11 10 17 25 mV Inverting or Non Inverting Input Volt...

Page 127: ...eripherals as well as additional custom peripherals and functions to extend its capability see Figure 11 1 for a block diagram The CIP 51 includes the following features Performance The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock c...

Page 128: ...s method of on chip debug is completely non intrusive and non invasive requiring no RAM Stack timers or other on chip resources The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs pro vides an integrated development environment IDE including editor macro assembler debugger and pro grammer The IDE s debugger and programmer interface to the CIP 51 via ...

Page 129: ...umber of clock cycles for each instruction 11 1 2 MOVX Instruction and Program Memory In the CIP 51 the MOVX instruction serves three purposes accessing on chip XRAM accessing off chip XRAM and accessing on chip program Flash memory The Flash access feature provides a mechanism for user software to update program code and use the program memory space for non volatile data stor age see Section 15 F...

Page 130: ...sive OR Register to A 1 1 XRL A direct Exclusive OR direct byte to A 2 2 XRL A Ri Exclusive OR indirect RAM to A 1 2 XRL A data Exclusive OR immediate to A 2 2 XRL direct A Exclusive OR A to direct byte 2 2 XRL direct data Exclusive OR immediate to direct byte 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through Carry 1 1 RR A Rotate A right 1 1 RRC A Rot...

Page 131: ...nibble of indirect RAM with A 1 2 Boolean Manipulation CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set Carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 ANL C bit AND complement of direct bit to Carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to Carry 2 2 MOV C ...

Page 132: ... Summary Continued Mnemonic Description Bytes Clock Cycles Notes on Registers Operands and Addressing Modes Rn Register R0 R7 of the currently selected register bank Ri Data RAM location addressed indirectly through R0 or R1 rel 8 bit signed 2s complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s addr...

Page 133: ...ads of the Flash memory Note 1024 bytes of the memory in Bank 3 0x1FC00 to 0x1FFFF are reserved and are not available for user program or data storage The C8051F132 3 have a 64k byte program memory space implemented as in system re programmable Flash memory and organized in a contiguous block from address 0x00000 to 0x0FFFF Program memory is normally assumed to be read only However the CIP 51 can ...

Page 134: ...Target Bank 3 Bits 3 2 Reserved Bits 1 0 IFBANK Instruction Fetch Operations Bank Select These bits select which Flash bank is used for instruction fetches involving addresses 0x8000 to 0xFFFF These bits can only be changed from code in Bank 0 see Figure 11 3 00 Instructions Fetch From Bank 0 note that Bank 0 is also mapped between 0x0000 to 0x7FFF 01 Instructions Fetch From Bank 1 10 Instructions...

Page 135: ...es and interrupt service routines Indirect addressing modes use registers R0 and R1 as index registers 11 2 4 Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits Each bit has a bit address from 0x00 to 0x7F Bit 0 of the byte at 0x20 has bit address 0x...

Page 136: ...2 3 and F SFR pages are selected using the Special Function Register Page Selection register SFRPAGE see SFR Definition 11 3 The procedure for reading and writing an SFR is as follows 1 Select the appropriate SFR page number using the SFRPAGE register 2 Use direct accessing mode to read or write the special function register MOV instruction 11 2 6 2 Interrupts and SFR Paging When an interrupt occu...

Page 137: ...ss dis abled in software A summary of the SFR locations address and SFR page is provided in Table 11 2 in the form of an SFR memory map Each memory location in the map has an SFR page row denoting the page in which that SFR resides Note that certain SFR s are accessible from ALL SFR pages and are denoted by the ALL PAGES designation For example the Port I O registers P0 P1 P2 and P3 all have the A...

Page 138: ...s window comparator is being used with an associ ated ISR that is set to low priority At this point the SFR page is set to access the Port 5 SFR SFRPAGE 0x0F See Figure 11 5 below Figure 11 5 SFR Page Stack While Using SFR Page 0x0F To Access Port 5 While CIP 51 executes in line code writing values to Port 5 in this example ADC2 Window Comparator Interrupt occurs The CIP 51 vectors to the ADC2 Win...

Page 139: ...CA s special function registers into the SFRPAGE register SFR Page 0x00 The value that was in the SFRPAGE register before the PCA interrupt SFR Page 2 for ADC2 is pushed down the stack into SFRNEXT Likewise the value that was in the SFRNEXT register before the PCA interrupt in this case SFR Page 0x0F for Port 5 is pushed down to the SFRLAST register the bottom of the stack Note that a value stored...

Page 140: ...ISR can continue to access SFR s as it did prior to the PCA interrupt Likewise the contents of SFRLAST are moved to the SFRNEXT register Recall this was the SFR Page value 0x0F being used to access Port 5 before the ADC2 interrupt occurred See Figure 11 8 below Figure 11 8 SFR Page Stack Upon Return From PCA Interrupt 0x00 PCA 0x02 ADC2 0x0F Port 5 SFRPAGE SFRLAST SFRNEXT SFR Page 0x00 Automatical...

Page 141: ...possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call Direct access to the SFR Page stack can be useful to enable real time operating systems to control and manage context switching between multiple tasks Push operations on the SFR Page Stack only occur on interrupt service and pop operations only occur on interrupt exit execution on the RETI inst...

Page 142: ...eral or function that is the source of the inter rupt R W R W R W R W R W R W R W R W Reset Value SFRPGEN 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x96 F Bits7 0 SFR Page Bits Byte Represents the SFR Page the C8051 MCU uses when reading or mod ifying SFR s Write Sets the SFR Page Read Byte is the SFR page the C8051 MCU is using When enabled in the SFR Page Control Regi...

Page 143: ...R stack This is the value that will go to the SFR Page register upon a return from interrupt R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x85 All Pages Bits7 0 SFR Page Stack Bits SFR page context is retained upon interrupts return from interrupts in a 3 byte SFR Page Stack SFRPAGE is the first entry SFRNEXT is the second and SF...

Page 144: ...CA0CPH4 RSTSRC E0 0 1 2 3 F ACC ALL PAGES PCA0CPL5 XBR0 PCA0CPH5 XBR1 XBR2 EIE1 ALL PAGES EIE2 ALL PAGES D8 0 1 2 3 F PCA0CN P5 PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5 D0 0 1 2 3 F PSW ALL PAGES REF0CN DAC0L DAC1L DAC0H DAC1H DAC0CN DAC1CN C8 0 1 2 3 F TMR2CN TMR3CN TMR4CN P4 TMR2CF TMR3CF TMR4CF RCAP2L RCAP3L RCAP4L RCAP2H RCAP3H RCAP4H TMR2L TMR3L TMR4L TMR2H TMR3H TMR4H MAC...

Page 145: ...N0 SCON1 SBUF0 SBUF1 SPI0CFG CCH0MA SPI0DAT P4MDOUT SPI0CKR P5MDOUT P6MDOUT P7MDOUT 90 0 1 2 3 F P1 ALL PAGES SSTA0 MAC0BL MAC0BH MAC0ACC0 MAC0ACC1 MAC0ACC2 MAC0ACC3 SFRPGCN MAC0OVR CLKSEL 88 0 1 2 3 F TCON CPT0CN CPT1CN FLSTAT TMOD CPT0MD CPT1MD PLL0CN TL0 OSCICN TL1 OSCICL TH0 OSCXCN TH1 PLL0DIV CKCON PLL0MUL PSCTL PLL0FLT 80 0 1 2 3 F P0 ALL PAGES SP ALL PAGES DPL ALL PAGES DPH ALL PAGES SFRPAG...

Page 146: ...ADC2LT 0xC6 2 ADC2 Less Than page 1023 AMX0CF 0xBA 0 ADC0 Multiplexer Configuration page 601 page 782 AMX0SL 0xBB 0 ADC0 Multiplexer Channel Select page 611 page 792 AMX2CF 0xBA 2 ADC2 Multiplexer Configuration page 953 AMX2SL 0xBB 2 ADC2 Multiplexer Channel Select page 963 B 0xF0 All Pages B Register page 153 CCH0CN 0xA1 F Cache Control page 215 CCH0LC 0xA3 F Cache Lock page 216 CCH0MA 0x9A F Cac...

Page 147: ...page 1724 MAC0CF 0xC3 3 MAC0 Configuration page 1704 MAC0OVR 0x97 3 MAC0 Accumulator Overflow page 1744 MAC0RNDH 0xCF 3 MAC0 Rounding Register High Byte page 1744 MAC0RNDL 0xCE 3 MAC0 Rounding Register Low Byte page 1754 MAC0STA 0xC0 3 MAC0 Status Register page 1714 OSCICL 0x8B F Internal Oscillator Calibration page 186 OSCICN 0x8A F Internal Oscillator Control page 186 OSCXCN 0x8C F External Osci...

Page 148: ...0xDA 0 PCA Module 0 Mode page 337 PCA0CPM1 0xDB 0 PCA Module 1 Mode page 337 PCA0CPM2 0xDC 0 PCA Module 2 Mode page 337 PCA0CPM3 0xDD 0 PCA Module 3 Mode page 337 PCA0CPM4 0xDE 0 PCA Module 4 Mode page 337 PCA0CPM5 0xDF 0 PCA Module 5 Mode page 337 PCA0H 0xFA 0 PCA Counter High Byte page 338 PCA0L 0xF9 0 PCA Counter Low Byte page 338 PCA0MD 0xD9 0 PCA Mode page 336 PCON 0x87 All Pages Power Contro...

Page 149: ...0x9D 0 SPI Clock Rate Control page 282 SPI0CN 0xF8 0 SPI Control page 281 SPI0DAT 0x9B 0 SPI Data page 282 SSTA0 0x91 0 UART 0 Status page 297 TCON 0x88 0 Timer Counter Control page 313 TH0 0x8C 0 Timer Counter 0 High Byte page 316 TH1 0x8D 0 Timer Counter 1 High Byte page 316 TL0 0x8A 0 Timer Counter 0 Low Byte page 315 TL1 0x8B 0 Timer Counter 1 Low Byte page 316 TMOD 0x89 0 Timer Counter Mode p...

Page 150: ...F120 1 4 5 only 2 Refers to a register in the C8051F122 3 6 7 and C8051F130 1 2 3 only 3 Refers to a register in the C8051F120 1 2 3 4 5 6 7 only 4 Refers to a register in the C8051F120 1 2 3 and C8051F130 1 2 3 only 5 Refers to a register in the C8051F120 2 4 6 only 6 Refers to a register in the C8051F121 3 5 7 only 7 Refers to a register in the C8051F130 1 2 3 only Table 11 3 Special Function Re...

Page 151: ... Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incremented before every PUSH operation The SP register defaults to 0x07 after reset R W R W R W R W R W R W R W R W Reset Value 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x81 All Pages Bits7 0 DPL Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is ...

Page 152: ...d during register accesses Bit2 OV Overflow Flag This bit is set to 1 under the following circumstances An ADD ADDC or SUBB instruction causes a sign change overflow A MUL instruction results in an overflow result is greater than 255 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases Bit1 F1 User Flag 1 Th...

Page 153: ... Reset Value ACC 7 ACC 6 ACC 5 ACC 4 ACC 3 ACC 2 ACC 1 ACC 0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xE0 All Pages Bits7 0 B B Register This register serves as a second accumulator for certain arithmetic operations R W R W R W R W R W R W R W R W Reset Value B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressab...

Page 154: ... interrupt enable settings Note Any instruction that clears the EA bit should be immediately followed by an instruction that has two or more opcode bytes For example in C EA 0 clear EA bit EA 0 this is a dummy instruction with two byte opcode in assembly CLR EA clear EA bit CLR EA this is a dummy instruction with two byte opcode If an interrupt is posted during the execution phase of a CLR EA opco...

Page 155: ... pt Vector Priority Order Pending Flags Bit addressable Cleared by HW SFRPAGE SFRPGEN 1 Enable Flag Priority Control Reset 0x0000 Top None N A N A 0 Always Enabled Always Highest External Interrupt 0 INT0 0x0003 0 IE0 TCON 1 Y Y 0 EX0 IE 0 PX0 IP 0 Timer 0 Overflow 0x000B 1 TF0 TCON 5 Y Y 0 ET0 IE 1 PT0 IP 1 External Interrupt 1 INT1 0x0013 2 IE1 TCON 3 Y Y 0 EX1 IE 2 PX1 IP 2 Timer 1 Overflow 0x0...

Page 156: ...pt is pending when a RETI is executed a single instruc tion is executed before an LCALL is made to service the pending interrupt Therefore the maximum response time for an interrupt when no other interrupt is currently being serviced or the new interrupt is of greater priority is when the CPU is performing an RETI instruction followed by a DIV as the next instruc tion and a cache miss event also o...

Page 157: ...is bit sets the masking of the Timer 2 interrupt 0 Disable Timer 2 interrupt 1 Enable Timer 2 interrupt Bit4 ES0 Enable UART0 Interrupt This bit sets the masking of the UART0 interrupt 0 Disable UART0 interrupt 1 Enable UART0 interrupt Bit3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable Timer 1 interrupt 1 Enable Timer 1 interrupt Bit2 EX1 Enable External...

Page 158: ...t to low priority 1 Timer 1 interrupts set to high priority Bit2 PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority 1 External Interrupt 1 set to high priority Bit1 PT0 Timer 0 Interrupt Priority Control This bit sets the priority of the Timer 0 interrupt 0 Timer 0 interrupt set to low priority 1 Tim...

Page 159: ...f the CP0 falling edge interrupt 0 Disable CP0 falling edge interrupts 1 Enable CP0 falling edge interrupts Bit3 EPCA0 Enable Programmable Counter Array PCA0 Interrupt This bit sets the masking of the PCA0 interrupts 0 Disable PCA0 interrupts 1 Enable PCA0 interrupts Bit2 EWADC0 Enable Window Comparison ADC0 Interrupt This bit sets the masking of ADC0 Window Comparison interrupt 0 Disable ADC0 Win...

Page 160: ...s the masking of ADC2 Window Comparison interrupt 0 Disable ADC2 Window Comparison Interrupts 1 Enable ADC2 Window Comparison Interrupts Bit2 ET4 Enable Timer 4 Interrupt This bit sets the masking of the Timer 4 interrupt 0 Disable Timer 4 interrupts 1 Enable Timer 4 interrupts Bit1 EADC0 Enable ADC0 End of Conversion Interrupt This bit sets the masking of the ADC0 End of Conversion Interrupt 0 Di...

Page 161: ... set to low priority 1 CP0 falling interrupt set to high priority Bit3 PPCA0 Programmable Counter Array PCA0 Interrupt Priority Control This bit sets the priority of the PCA0 interrupt 0 PCA0 interrupt set to low priority 1 PCA0 interrupt set to high priority Bit2 PWADC0 ADC0 Window Comparator Interrupt Priority Control This bit sets the priority of the ADC0 Window interrupt 0 ADC0 Window interrup...

Page 162: ...C2 Window Compare interrupt 0 ADC2 Window Compare interrupt set to low priority 1 ADC2 Window Compare interrupt set to high priority Bit2 PT4 Timer 4 Interrupt Priority Control This bit sets the priority of the Timer 4 interrupt 0 Timer 4 interrupt set to low priority 1 Timer 4 interrupt set to high priority Bit1 PADC0 ADC0 End of Conversion Interrupt Priority Control This bit sets the priority of...

Page 163: ... is terminated when an enabled interrupt or RST is asserted The assertion of an enabled inter rupt will cause the Idle Mode Selection bit PCON 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Id...

Page 164: ... will cause an internal reset and thereby terminate the Stop mode The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100 µs SFR Definition 11 18 PCON Power Control Bits7 3 Reserved Bit1 STOP STOP Mode Select Writing a 1 to this bit will place the CIP 51 into STOP mode This bit will always read 0 1 CIP 51 forced into power down mode Tur...

Page 165: ... these regis ters are related to configuration and operation while the other eleven are used to store multi byte input and output data for MAC0 The Configuration register MAC0CF SFR Definition 12 1 is used to configure and control MAC0 The Status register MAC0STA SFR Definition 12 2 contains flags to indicate overflow conditions as well as zero and negative results The 16 bit MAC0A MAC0AH MAC0AL a...

Page 166: ...0 bit 2 s complement fractional value with the decimal point located between bits 31 and 30 Figure 12 3 shows how fractional numbers are stored in the SFRs Figure 12 3 Fractional Mode Data Representation 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 239 238 233 232 231 230 21 20 22 229 23 228 24 High Byte Low Byte MAC0OVR MAC0ACC3 MAC0ACC2 MAC0ACC1 MAC0ACC0 MAC0A and MAC0B Bit Weighting MA...

Page 167: ...s complete Figure 12 4 MAC0 Pipeline 12 4 Operating in Multiply Only Mode MAC0 operates in Multiply Only mode when the MAC0MS bit MAC0CF 0 is set to 1 Multiply Only mode is identical to Multiply and Accumulate mode except that the multiplication result is added with a value of zero before being stored in the MAC0 accumulator i e it overwrites the current accumulator contents The result of the mult...

Page 168: ...ls some software examples for using MAC0 Section 12 7 1 shows a series of two MAC operations using fractional numbers Section 12 7 2 shows a single operation in Multiply Only mode with integer numbers The last example shown in Section 12 7 3 demonstrates how the left shift and right shift operations can be used to modify the accumulator All of the examples assume that all of the flags in the MAC0S...

Page 169: ...ive result NOP After this instruction the Rounding register is updated 12 7 3 MAC0 Accumulator Shift Example The example below shifts the MAC0 accumulator left one bit and then right two bits MOV MAC0OVR 40h The next few instructions load the accumulator with the value MOV MAC0ACC3 88h 4088442211 Hex MOV MAC0ACC2 44h MOV MAC0ACC1 22h MOV MAC0ACC0 11h MOV MAC0CF 20h Initiate a Left shift NOP After ...

Page 170: ...le This bit will be cleared to 0 by hardware when the reset is complete Bit 2 MAC0SAT Saturate Rounding Register This bit controls whether the Rounding Register will saturate If this bit is set and a Soft Overflow occurs the Rounding Register will saturate This bit does not affect the operation of the MAC0 Accumulator See Section 12 6 for more details about rounding and saturation 0 Rounding Regis...

Page 171: ...ero this bit will be cleared to 0 Bit 1 MAC0SO Soft Overflow Flag This bit is set to 1 when a MAC operation causes an overflow into the sign bit bit 31 of the MAC0 Accumulator If the overflow condition is corrected after a subsequent MAC opera tion this bit is cleared to 0 Bit 0 MAC0N Negative Flag If the MAC Accumulator result is negative this bit will be set to 1 If the result is positive or zer...

Page 172: ...ress 0xC1 SFR Page 3 Bits 7 0 High Byte bits 15 8 of MAC0 B Register R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x92 SFR Page 3 Bits 7 0 Low Byte bits 7 0 of MAC0 B Register A write to this register initiates a Multiply or Multiply and Accumulate operation Note The contents of this register should not be changed by software during the first MAC0 pipeli...

Page 173: ...0000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x96 SFR Page 3 Bits 7 0 Byte 2 bits 23 16 of MAC0 Accumulator Note The contents of this register should not be changed by software during the first two MAC0 pipeline stages R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x95 SFR Page 3 Bits 7 0 Byte 1 bits 15 8 of MAC0 Accumulator Note The conten...

Page 174: ...two MAC0 pipeline stages R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x93 SFR Page 3 Bits 7 0 MAC0 Accumulator Overflow Bits bits 39 32 Note The contents of this register should not be changed by software during the first two MAC0 pipeline stages R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x97 SFR Page 3 Bit...

Page 175: ... 2 3 Rev 1 4 175 SFR Definition 12 13 MAC0RNDL MAC0 Rounding Register Low Byte Bits 7 0 Low Byte bits 7 0 of MAC0 Rounding Register R R R R R R R R Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xCE SFR Page 3 ...

Page 176: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 176 Rev 1 4 ...

Page 177: ...exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator running at its lowest frequency Refer to Section 14 Oscillators on page 185 for informa tion on selecting and configuring the system clock source The Watchdog Timer is enabled using its longest timeout interval see Section 13 7 Watchdog Timer Reset on page 179 Once the system clock s...

Page 178: ... the other reset flags in the RSTSRC Register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The contents of internal data memory should be assumed to be undefined after a power on reset Figure 13 2 Reset Timing 13 2 Power fail Res...

Page 179: ...reads 0 The state of the RST pin is unaffected by this reset 13 6 External CNVSTR0 Pin Reset The external CNVSTR0 signal can be configured as a reset input by writing a 1 to the CNVRSEF flag RSTSRC 6 The CNVSTR0 signal can appear on any of the P0 P1 P2 or P3 I O pins as described in Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 238 Note that the Cross bar must be configu...

Page 180: ...ETB EA re enable interrupts The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other or the disable operation is ignored This means that the prefetch engine should be enabled and interrupts should be disabled during this procedure to avoid any delay between the two writes 13 7 3 Disable WDT Lockout Writing 0xFF to WDTCN locks out the disable feature Once locked out the disable op...

Page 181: ...riting 0xFF locks out the disable feature Bit4 Watchdog Status Bit when Read Reading the WDTCN 4 bit indicates the Watchdog Timer Status 0 WDT is inactive 1 WDT is active Bits2 0 Watchdog Timeout Interval Bits The WDTCN 2 0 bits set the Watchdog Timeout Interval When writing these bits WDTCN 7 must be set to 0 R W R W R W R W R W R W R W R W Reset Value xxxxx111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ...

Page 182: ...timeout 1 Source of last reset was a Missing Clock Detector timeout Bit1 PORSF Power On Reset Flag Write If the VDD monitor circuitry is enabled by tying the MONEN pin to a logic high state this bit can be written to select or de select the VDD monitor as a reset source 0 De select the VDD monitor as a reset source 1 Select the VDD monitor as a reset source Important At power on the VDD monitor is...

Page 183: ...Low Voltage 0 3 x VDD RST Input Leakage Current RST 0 0 V 50 µA VDD for RST Output Valid 1 0 V AV for RST Output Valid 1 0 V VDD POR Threshold VRST 2 40 2 55 2 70 V Minimum RST Low Time to Gen erate a System Reset 10 ns Reset Time Delay RST rising edge after VDD crosses VRST threshold 80 100 120 ms Missing Clock Detector Timeout Time from last system clock to reset initiation 100 220 500 µs Note W...

Page 184: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 184 Rev 1 4 NOTES ...

Page 185: ...the system clock after a system reset The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 14 1 OSCICL is factory calibrated to obtain a 24 5 MHz frequency Table 14 1 Oscillator Electrical Characteristics 40 C to 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Calibrated Internal Oscillator Frequency 24 24 5 25 MHz Internal Osci...

Page 186: ...ted to generate an inter nal oscillator frequency of 24 5 MHz R W R W R W R W R W R W R W R W Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x8B F Bit 7 IOSCEN Internal Oscillator Enable Bit 0 Internal Oscillator Disabled 1 Internal Oscillator Enabled Bit 6 IFRDY Internal Oscillator Frequency Ready Flag 0 Internal Oscillator not running at programmed frequency 1...

Page 187: ...l oscillator however the external oscillator may still clock certain peripherals such as the timers and PCA when the internal oscillator or the PLL is selected as the system clock The system clock may be switched on the fly between the internal and external oscillators or the PLL so long as the selected oscillator source is enabled and settled The internal oscillator requires little start up time ...

Page 188: ...CLK 4 11 Output will be SYSCLK 8 See Section 18 Port Input Output on page 235 for more details about routing this out put to a port pin Bits 3 2 Reserved Bits 1 0 CLKSL1 0 System Clock Source Select Bits 00 SYSCLK derived from the Internal Oscillator and scaled as per the IFCN bits in OSCICN 01 SYSCLK derived from the External Oscillator circuit 10 SYSCLK derived from the PLL 11 Reserved R W R W R...

Page 189: ...uency RC MODE Circuit from Figure 14 1 Option 2 XOSCMD 10x Choose XFCN value to match frequency range f 1 23 103 R C where f frequency of oscillation in MHz C capacitor value in pF R Pullup resistor value in kΩ C MODE Circuit from Figure 14 1 Option 3 XOSCMD 10x Choose K Factor KF for the oscillation frequency desired f KF C VDD where f frequency of oscillation in MHz C capacitor value on XTAL1 XT...

Page 190: ...which could introduce noise or interference 14 5 External RC Example If an RC network is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 14 1 Option 2 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To deter mine the required Exter...

Page 191: ... in the PLL Pre divider Register PLL0DIV shown in SFR Definition 14 6 14 7 2 PLL Multiplication and Output Clock The PLL circuitry will multiply the divided reference clock by the multiplication factor stored in the PLL0MUL register shown in SFR Definition 14 7 To accomplish this it uses a feedback loop consisting of a phase frequency detector a loop filter and a current controlled oscillator ICO ...

Page 192: ...o be changed when the PLL is already running the following procedure should be implemented Step 1 The system clock should first be switched to either the internal oscillator or an external clock source that is running and stable using the CLKSEL register Step 2 Ensure that the reference clock to be used for the new PLL setting internal or external is running and stable Step 3 Set the PLLSRC bit PL...

Page 193: ... Definition 14 5 PLL0CN PLL Control Bits 7 5 UNUSED Read 000b Write don t care Bit 4 PLLCK PLL Lock Flag 0 PLL Frequency is not locked 1 PLL Frequency is locked Bit 3 RESERVED Must write to 0 Bit 2 PLLSRC PLL Reference Clock Source Select Bit 0 PLL Reference Clock Source is Internal Oscillator 1 PLL Reference Clock Source is External Oscillator Bit 1 PLLEN PLL Enable Bit 0 PLL is held in reset 1 P...

Page 194: ... clock will be divided by 32 R W R W R W R W R W R W R W R W Reset Value PLLM4 PLLM3 PLLM2 PLLM1 PLLM0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x8D F Bits 7 0 PLLN7 0 PLL Multiplier These bits select the multiplication factor of the divided PLL reference clock When set to any non zero value the multiplication factor will be equal to the value in PLLN7 0 When set to 00...

Page 195: ...LICO1 0 PLL Current Controlled Oscillator Control Bits Selection is based on the desired output frequency according to the following table Bits 3 0 PLLLP3 0 PLL Loop Filter Control Bits Selection is based on the divided PLL reference clock according to the following table R W R W R W R W R W R W R W R W Reset Value PLLICO1 PLLICO0 PLLLP3 PLLLP2 PLLLP1 PLLLP0 00110001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 ...

Page 196: ...g Output Frequency Min Typ Max Units 5 MHz 20 0x0F 100 MHz 202 µs 13 0x0F 65 MHz 115 µs 16 0x1F 80 MHz 241 µs 9 0x1F 45 MHz 116 µs 12 0x2F 60 MHz 258 µs 6 0x2F 30 MHz 112 µs 10 0x3F 50 MHz 263 µs 5 0x3F 25 MHz 113 µs 25 MHz 4 0x01 100 MHz 42 µs 2 0x01 50 MHz 33 µs 3 0x11 75 MHz 48 µs 2 0x11 50 MHz 17 µs 2 0x21 50 MHz 42 µs 1 0x21 25 MHz 33 µs 2 0x31 50 MHz 60 µs 1 0x31 25 MHz 25 µs ...

Page 197: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Rev 1 4 197 NOTES ...

Page 198: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 198 Rev 1 4 ...

Page 199: ...n initial ized device For details on the JTAG commands to program Flash memory see Section 25 JTAG IEEE 1149 1 on page 341 The Flash memory can be programmed from software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands Before writing to Flash memory using MOVX Flash write operations must be enabled by setting the PSWE Program Store Writ...

Page 200: ...r must be erased first In order to change a single byte of a multi byte data set the data must be moved to temporary storage The 128 byte sector size facilitates updating data without wasting program memory or RAM space The 128 byte sectors are double mapped over the normal Flash memory for MOVC reads and MOVX writes only their addresses range from 0x00 to 0x7F and from 0x80 to 0xFF see Figure 15 ...

Page 201: ...ank 3 set the COBANK bits PSBANK 5 4 for the appropriate bank Step 3 If erasing a page in the Scratchpad area set the SFLE bit PSCTL 2 Step 4 Set FLWE FLSCL 0 to enable Flash writes erases via user software Step 5 Set PSEE PSCTL 1 to enable Flash erases Step 6 Set PSWE PSCTL 0 to redirect MOVX commands to write to Flash Step 7 Use the MOVX instruction to write a data byte to any location within th...

Page 202: ... SFLE bit Step 11 Re enable interrupts For block Flash writes the Flash write procedure is only performed after the last byte of each block is writ ten with the MOVX write instruction When writing to addresses located in any of the four code banks a Flash write block is four bytes long from addresses ending in 00b to addresses ending in 11b Writes must be performed sequentially i e addresses endin...

Page 203: ...ecurity lock bytes are located at 0x0FFFE Write Erase Lock and 0x0FFFF Read Lock as shown in Figure 15 3 The 1024 byte sector containing the lock bytes can be written to but not erased by software An attempted read of a read locked byte returns undefined data Debugging code in a read locked sector is not possible through the JTAG interface The lock bits can always be read from and written to logic...

Page 204: ... are locked disabled for corresponding block across the JTAG interface 1 Read operations are unlocked enabled for corresponding block across the JTAG inter face Flash Write Erase Lock Byte Bits7 0 Each bit locks a corresponding block of memory 0 Write Erase operations are locked disabled for corresponding block across the JTAG interface 1 Write Erase operations are unlocked enabled for correspondi...

Page 205: ...g block across the JTAG interface 1 Read operations are unlocked enabled for corresponding block across the JTAG inter face Flash Write Erase Lock Byte Bits7 0 Each bit locks a corresponding block of memory 0 Write Erase operations are locked disabled for corresponding block across the JTAG interface 1 Write Erase operations are unlocked enabled for corresponding block across the JTAG interface NO...

Page 206: ... location in the upper partition If entry points are published software running in the upper partition may execute program code in the lower partition but it cannot read or change the contents of the lower partition Parameters may be passed to the program code running in the lower parti tion either through the typical method of placing them on the stack or in registers before the call or by plac i...

Page 207: ...ritten to or erased at any time Accessing Flash from firmware residing below the Flash Access Limit 1 The Read and Write Erase Lock bytes security bytes do not restrict Flash access from user firmware 2 Any page of Flash except the page containing the security bytes may be read from written to or erased 3 The page containing the security bytes cannot be erased Unlocking pages of Flash can only be ...

Page 208: ...t 0 FLWE Flash Write Erase Enable This bit must be set to allow Flash writes erasures from user software 0 Flash writes erases disabled 1 Flash writes erases enabled Important Note When changing the FLRT bits to a lower setting e g when changing from a value of 11b to 00b cache reads cache writes and the prefetch engine should be disabled using the CCH0CN register see SFR Definition 16 1 R W R W R...

Page 209: ...t allows an entire page of the Flash program memory to be erased provided the PSWE bit is also set After setting this bit a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction The value of the data byte written does not matter Note The Flash page con taining the Read Lock Byte and Write Erase Lock Byte cannot be e...

Page 210: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 210 Rev 1 4 NOTES ...

Page 211: ...6 1 Branch Target Cache Data Flow 16 1 Cache and Prefetch Operation The branch target cache maintains two sets of memory locations slots and tags A slot is where the cached instruction data from Flash is stored Each slot holds four consecutive code bytes A tag contains the 15 most significant bits of the corresponding Flash address for each four byte slot Thus instruction data is always cached alo...

Page 212: ...ize the execution time of a specific routine or critical timing loop The branch target cache includes options to exclude caching of certain types of data as well as the ability to pre load and lock time critical branch locations to optimize execution speed The most basic level of cache control is implemented with the Cache Miss Penalty Threshold bits CHMSTH CCH0TN 1 0 If the processor is stalled d...

Page 213: ...e prefetch engine To dis able cache reads the CHRDEN bit CCH0CN 6 can be cleared to 0 Note that when cache reads are disabled cache writes will still occur if CHWREN is set to 1 Disabling the prefetch engine is accom plished using the CHPFEN bit CCH0CN 5 When this bit is cleared to 0 the prefetch engine will be dis abled If both CHPFEN and CHRDEN are 0 code will execute at a fixed rate as instruct...

Page 214: ... 62 TAG 61 SLOT 61 TAG 2 SLOT 2 TAG 1 SLOT 1 TAG 0 SLOT 0 TAG 60 SLOT 60 TAG 59 SLOT 59 CHSLOT 58 LOCKED LOCKED LOCKED UNLOCKED UNLOCKED UNLOCKED Lock Status Cache Push Operations Decrement CHSLOT Cache Pop Operations Increment CHSLOT LOCKED TAG 58 SLOT 58 UNLOCKED UNLOCKED TAG 57 SLOT 57 UNLOCKED ...

Page 215: ... enables the destination of a RETI address to be cached 0 Destinations of RETI instructions will not be cached 1 RETI destinations will be cached Bit 2 CHISR Cache ISR Enable This bit allows instructions which are part of an Interrupt Service Rountine ISR to be cached 0 Instructions in ISRs will not be loaded into cache memory 1 Instructions in ISRs can be cached Bit 1 CHMOVC Cache MOVC Enable Thi...

Page 216: ...100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xA2 F Bit 7 CHPUSH Cache Push Enable This bit enables cache push operations which will lock information in cache slots using MOVC instructions 0 Cache push operations are disabled 1 Cache push operations are enabled When a MOVC read is executed the requested 4 byte segment containing the data is locked into the cache at the location...

Page 217: ...rocessor is delayed due to a cache miss This is primarily used as a diagnostic feature when optimizing code for execution speed Writing to CHMSCTH clears the lower 5 bits of the Cache Miss Penalty Accumulator Reading from CHMSCTH returns the current value of CHMSTCH and latches bits 4 1 into CHMSTCL so that they can be read Because bit 0 of the Cache Miss Penalty Accumulator is not available the C...

Page 218: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 218 Rev 1 4 NOTES ...

Page 219: ...th of these methods are given below 17 1 1 16 Bit MOVX Example The 16 bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A MOV DPTR 1234h load DPTR with 16 bit address to read 0x1234 MOVX A DPTR load contents of 0x1234 into accumulator A...

Page 220: ...the Crossbar on Ports 3 2 1 and 0 See Section 18 Port Input Output on page 235 for more information about the Crossbar and Port operation and configuration The Port latches should be explicitly configured to park the External Memory Interface pins in a dor mant state most commonly by setting them to a logic 1 During the execution of the MOVX instruction the External Memory Interface will explicitl...

Page 221: ...use the current contents of the Address High port latches to resolve upper address byte Note that in order to access off chip space EMI0CN must be set to a page that is not contained in the on chip address space 10 Split Mode with Bank Select Accesses below the 8 k boundary are directed on chip Accesses above the 8k boundary are directed off chip 8 bit off chip MOVX operations use the contents of ...

Page 222: ...ration is shown in Figure 17 1 In Multiplexed mode the external MOVX operation can be broken into two phases delineated by the state of the ALE signal During the first phase ALE is high and the lower 8 bits of the Address Bus are pre sented to AD 7 0 During this phase the address latch is configured such that the Q outputs reflect the states of the D inputs When ALE falls signaling the beginning o...

Page 223: ...s pins are not shared An example of a Non multiplexed Configuration is shown in Figure 17 2 See Section 17 6 1 Non multiplexed Mode on page 227 for more information about Non multiplexed operation Figure 17 2 Non multiplexed Configuration Example ADDRESS BUS E M I F A 15 0 64K X 8 SRAM A 15 0 DATA BUS D 7 0 I O 7 0 VDD 8 WR RD OE WE CE Optional ...

Page 224: ...it into two areas on chip space and off chip space Effective addresses below the 8 k boundary will access on chip XRAM space Effective addresses above the 8 k boundary will access off chip space 8 bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on chip or off chip However in the No Bank Select mode an 8 bit MOVX operation will not drive the upper 8 bits A 1...

Page 225: ...ts at will by setting the Port state directly The lower 8 bits of the effective address A 7 0 are determined by the contents of R0 or R1 16 bit MOVX operations use the contents of DPTR to determine the effective address A 15 0 The full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 17 6 EMIF Timing The timing parameters of the External Memory Interface can be configur...

Page 226: ...6 SYSCLK cycles 0110 WR and RD pulse width 7 SYSCLK cycles 0111 WR and RD pulse width 8 SYSCLK cycles 1000 WR and RD pulse width 9 SYSCLK cycles 1001 WR and RD pulse width 10 SYSCLK cycles 1010 WR and RD pulse width 11 SYSCLK cycles 1011 WR and RD pulse width 12 SYSCLK cycles 1100 WR and RD pulse width 13 SYSCLK cycles 1101 WR and RD pulse width 14 SYSCLK cycles 1110 WR and RD pulse width 15 SYSCL...

Page 227: ...s from DPL P2 P6 P1 P5 P0 7 P4 7 P0 6 P4 6 P3 P7 EMIF WRITE DATA P2 P6 P1 P5 P0 7 P4 7 P0 6 P4 6 P3 P7 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 MSBs from DPH EMIF ADDRESS 8 LSBs from DPL P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 16 bit WRIT...

Page 228: ... P2 P6 P1 P5 P0 7 P4 7 P0 6 P4 6 P3 P7 EMIF WRITE DATA P2 P6 P0 7 P4 7 P0 6 P4 6 P3 P7 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 LSBs from R0 or R1 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 P2 P6 P0 6 P4 6 P0 7 P4 7 P3 P7 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 8 bit WRITE without Bank Select Nonmuxed 8 bit READ witho...

Page 229: ... P5 P0 7 P4 7 P0 6 P4 6 P3 P7 EMIF WRITE DATA P2 P6 P1 P5 P0 7 P4 7 P0 6 P4 6 P3 P7 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 MSBs from EMI0CN EMIF ADDRESS 8 LSBs from R0 or R1 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 P2 P6 P1 P5 P0 6 P4 6 P0 7 P4 7 P3 P7 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 8 bit WRITE with Bank ...

Page 230: ... 5 P4 5 P0 7 P4 7 P0 6 P4 6 P0 5 P4 5 T ACH T WDH T ACW T ACS T WDS ALE WR RD EMIF ADDRESS 8 MSBs from DPH EMIF WRITE DATA EMIF ADDRESS 8 LSBs from DPL T ALEH T ALEL P3 P7 P2 P6 P3 P7 ADDR 15 8 AD 7 0 P2 P6 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 MSBs from DPH EMIF ADDRESS 8 LSBs from DPL T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed ...

Page 231: ... 6 P4 6 P0 5 P4 5 P0 7 P4 7 P0 6 P4 6 P0 5 P4 5 T ACH T WDH T ACW T ACS T WDS ALE WR RD EMIF WRITE DATA EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL P3 P7 P2 P6 P3 P7 ADDR 15 8 AD 7 0 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 8 bit WRITE Without Bank Select Muxed 8 bit ...

Page 232: ... 6 P0 5 P4 5 T ACH T WDH T ACW T ACS T WDS ALE WR RD EMIF ADDRESS 8 MSBs from EMI0CN EMIF WRITE DATA EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL P3 P7 P2 P6 P3 P7 ADDR 15 8 AD 7 0 P2 P6 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 P0 6 P4 6 P0 7 P4 7 P0 5 P4 5 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 MSBs from EMI0CN EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 8 bit WRI...

Page 233: ... TSYSCLK 16 x TSYSCLK ns TACH Address Control Hold Time 0 3 x TSYSCLK ns TALEH Address Latch Enable High Time 1 x TSYSCLK 4 x TSYSCLK ns TALEL Address Latch Enable Low Time 1 x TSYSCLK 4 x TSYSCLK ns TWDS Write Data Setup Time 1 x TSYSCLK 19 x TSYSCLK ns TWDH Write Data Hold Time 0 3 x TSYSCLK ns TRDS Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns Note TSYSCLK is equal to one period of t...

Page 234: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 234 Rev 1 4 NOTES ...

Page 235: ...te addressable through their corresponding Port Data registers All Port pins are 5 V toler ant and all support configurable Open Drain or Push Pull output modes and weak pullups A block dia gram of the Port I O cell is shown in Figure 18 1 Complete Electrical Specifications for the Port I O pins are given in Table 18 1 Figure 18 1 Port I O Cell Block Diagram DGND PORT OUTENABLE PORT OUTPUT PUSH PU...

Page 236: ... Units Output High Voltage VOH IOH 3 mA Port I O Push Pull IOH 10 µA Port I O Push Pull IOH 10 mA Port I O Push Pull VDD 0 7 VDD 0 1 VDD 0 8 V Output Low Voltage VOL IOL 8 5 mA IOL 10 µA IOL 25 mA 1 0 0 6 0 1 V Input High Voltage VIH 0 7 x VDD Input Low Voltage VIL 0 3 x VDD Input Leakage Current DGND Port Pin VDD Pin Tri state Weak Pullup Off Weak Pullup On 10 1 µA Input Capacitance 5 pF ...

Page 237: ... on Port 1 can be used as Analog Inputs to ADC2 An External Memory Interface which is active during the execution of an off chip MOVX instruction can be active on either the lower Ports or the upper Ports See Section 17 External Data Memory Interface and On Chip XRAM on page 219 for more information about the External Memory Interface Figure 18 2 Port I O Functional Block Diagram External Pins Dig...

Page 238: ...as the highest priority its pins will always be mapped to P0 0 and P0 1 when UART0EN is set to a logic 1 If a digital peripheral s enable bits are not set to a logic 1 then its ports are not accessi ble at the Port pins of the device Also note that the Crossbar assigns pins to all associated functions when a serial communication peripheral is selected i e SMBus SPI UART It would be impossible for ...

Page 239: ...gisters are typically left alone Once the Crossbar registers have been properly configured the Crossbar is enabled by setting XBARE XBR2 4 to a logic 1 Until XBARE is set to a logic 1 the output drivers on Ports 0 through 3 are explicitly disabled in order to prevent possible contention on the Port pins while the Crossbar reg isters and other registers which can affect the device pinout are being ...

Page 240: ...ctivated on any pin that is driving a logic 0 that is an output pin will not contend with its own pullup device The weak pullup device can also be explicitly disabled on any Port 1 pin by configuring the pin as an Analog Input as described below 18 1 5 Configuring Port 1 Pins as Analog Inputs The pins on Port 1 can serve as analog inputs to the ADC2 analog MUX on the C8051F12x devices A Port pin i...

Page 241: ...that Read operations will explicitly disable the output drivers on the Data Bus See Section 17 External Data Mem ory Interface and On Chip XRAM on page 219 for more information about the External Memory Inter face Figure 18 4 Priority Crossbar Decode Table EMIFLE 1 EMIF in Multiplexed Mode P1MDIN 0xFF PIN I O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 TX0 RX0 SCK MISO MOSI NSS...

Page 242: ...R1 0 T0 T0E XBR1 1 INT0 INT0E XBR1 2 T1 T1E XBR1 3 INT1 INT1E XBR1 4 T2 T2E XBR1 5 T2EX T2EXE XBR1 6 T4 T4E XBR2 3 T4EX T4EXE XBR2 4 SYSCLK SYSCKE XBR1 7 CNVSTR0 CNVSTE0 XBR2 0 CNVSTR2 CNVSTE2 XBR2 5 ALE RD WR AIN2 0 A8 AIN2 1 A9 AIN2 2 A10 AIN2 3 A11 AIN2 4 A12 AIN2 5 A13 AIN2 6 A14 AIN2 7 A15 A8m A0 A9m A1 A10m A2 A11m A3 A12m A4 A13m A5 A14m A6 A15m A7 AD0 D0 AD1 D1 AD2 D2 AD3 D3 AD4 D4 AD5 D5 ...

Page 243: ...us is next in priority order so P0 2 is assigned to SDA and P0 3 is assigned to SCL UART1 is next in priority order so P0 4 is assigned to TX1 Because the External Memory Interface is selected on the lower Ports EMIFLE 1 which causes the Crossbar to skip P0 6 RD and P0 7 WR Because the External Memory Interface is configured in Multi plexed mode the Crossbar will also skip P0 5 ALE RX1 is assigned...

Page 244: ...E XBR2 3 T4EX T4EXE XBR2 4 SYSCLK SYSCKE XBR1 7 CNVSTR0 CNVSTE0 XBR2 0 CNVSTR2 CNVSTE2 XBR2 5 ALE RD WR AIN2 0 A8 AIN2 1 A9 AIN2 2 A10 AIN2 3 A11 AIN2 4 A12 AIN2 5 A13 AIN2 6 A14 AIN2 7 A15 A8m A0 A9m A1 A10m A2 A11m A3 A12m A4 A13m A5 A14m A6 A15m A7 AD0 D0 AD1 D1 AD2 D2 AD3 D3 AD4 D4 AD5 D5 AD6 D6 AD7 D7 XBR2 2 XBR0 5 3 UART0EN SPI0EN Crossbar Register Bits XBR0 2 XBR0 1 XBR0 0 SMB0EN AIN2 Input...

Page 245: ...EX0 CEX1 CEX2 CEX3 and CEX4 routed to 5 port pins 110 CEX0 CEX1 CEX2 CEX3 CEX4 and CEX5 routed to 6 port pins Bit2 UART0EN UART0 I O Enable Bit 0 UART0 I O unavailable at Port pins 1 UART0 TX routed to P0 0 and RX routed to P0 1 Bit1 SPI0EN SPI0 Bus I O Enable Bit 0 SPI0 I O unavailable at Port pins 1 SPI0 SCK MISO MOSI and NSS routed to 4 Port pins Note that the NSS signal is not assigned to a po...

Page 246: ...Bit 0 T2 unavailable at Port pin 1 T2 routed to Port pin Bit4 INT1E INT1 Input Enable Bit 0 INT1 unavailable at Port pin 1 INT1 routed to Port pin Bit3 T1E T1 Input Enable Bit 0 T1 unavailable at Port pin 1 T1 routed to Port pin Bit2 INT0E INT0 Input Enable Bit 0 INT0 unavailable at Port pin 1 INT0 routed to Port pin Bit1 T0E T0 Input Enable Bit 0 T0 unavailable at Port pin 1 T0 routed to Port pin...

Page 247: ...and RX routed to 2 Port pins Bit1 EMIFLE External Memory Interface Low Port Enable Bit 0 P0 7 P0 6 and P0 5 functions are determined by the Crossbar or the Port latches 1 If EMI0CF 4 0 External Memory Interface is in Multiplexed mode P0 7 WR P0 6 RD and P0 5 ALE are skipped by the Crossbar and their output states are determined by the Port latches and the External Memory Interface 1 If EMI0CF 4 1 ...

Page 248: ...ce and On Chip XRAM on page 219 for more information See also SFR Definition 18 3 for information about configuring the Crossbar for External Memory accesses R W R W R W R W R W R W R W R W Reset Value P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0x80 All Pages Bits7 0 P0MDOUT 7 0 Port0 Output Mode Bits 0 Port Pin out...

Page 249: ... more information about ADC2 2 P1 7 0 can be driven by the External Data Memory Interface as Address 15 8 in Non multiplexed mode See Section 17 External Data Memory Interface and On Chip XRAM on page 219 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit A...

Page 250: ...ts7 0 P2 7 0 Port2 Output Latch Bits Write Output appears on I O pins per XBR0 XBR1 and XBR2 Registers 0 Logic Low Output 1 Logic High Output open if corresponding P2MDOUT n bit 0 Read Regardless of XBR0 XBR1 and XBR2 Register settings 0 P2 n pin is logic low 1 P2 n pin is logic high Note P2 7 0 can be driven by the External Data Memory Interface as Address 15 8 in Multiplexed mode or as Address 7...

Page 251: ...A6 F Bits7 0 P3 7 0 Port3 Output Latch Bits Write Output appears on I O pins per XBR0 XBR1 and XBR2 Registers 0 Logic Low Output 1 Logic High Output open if corresponding P3MDOUT n bit 0 Read Regardless of XBR0 XBR1 and XBR2 Register settings 0 P3 n pin is logic low 1 P3 n pin is logic high Note P3 7 0 can be driven by the External Data Memory Interface as AD 7 0 in Multiplexed mode or as D 7 0 in...

Page 252: ... TQFP devices the Port Data regis ters are still present and can be used by software Because the digital input paths also remain active it is recommended that these pins not be left in a floating state in order to avoid unnecessary power dissipa tion arising from the inputs floating to non valid logic levels This condition can be prevented by any of the following 1 Leave the weak pullup devices en...

Page 253: ...ovides a resistive connection about 100 kΩ between the pin and VDD The weak pullup devices can be globally disabled by writing a logic 1 to the Weak Pullup Disable bit WEAKPUD XBR2 7 The weak pullup is automatically deactivated on any pin that is driving a logic 0 that is an output pin will not contend with its own pullup device 18 2 5 External Memory Interface If the External Memory Interface EMI...

Page 254: ...P4 6 RD and P4 5 ALE can be driven by the External Data Memory Interface See Section 17 External Data Memory Interface and On Chip XRAM on page 219 for more information R W R W R W R W R W R W R W R W Reset Value P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xC8 F Bits7 0 P4MDOUT 7 0 Port4 Output Mode Bits 0 Port Pin ...

Page 255: ... Data Memory Interface as Address 15 8 in Non multiplexed mode See Section 17 External Data Memory Interface and On Chip XRAM on page 219 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xD8 F Bits7 0 P5MDOUT 7 0 Port5 Ou...

Page 256: ...ace as Address 15 8 in Multiplexed mode or as Address 7 0 in Non multiplexed mode See Section 17 External Data Memory Interface and On Chip XRAM on page 219 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xE8 F Bits7 0 P...

Page 257: ...Interface as AD 7 0 in Multiplexed mode or as D 7 0 in Non multiplexed mode See Section 17 External Data Memory Interface and On Chip XRAM on page 219 for more information about the External Memory Interface R W R W R W R W R W R W R W R W Reset Value P7 7 P7 6 P7 5 P7 4 P7 3 P7 2 P7 1 P7 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable SFR Address SFR Page 0xF8 F Bits7 0 P7MDOUT...

Page 258: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 258 Rev 1 4 NOTES ...

Page 259: ...a bus with multiple masters SMBus0 provides control of SDA serial data SCL serial clock generation and synchronization arbitration logic and START STOP control and generation Figure 19 1 SMBus0 Block Diagram SFR Bus Data Path Control SFR Bus Write to SMB0DAT SMBUS CONTROL LOGIC Read SMB0DAT SMB0ADR S L V 6 G C S L V 5 S L V 4 S L V 3 S L V 2 S L V 1 S L V 0 C R O S S B A R Clock Divide Logic SYSCL...

Page 260: ...data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL Note multiple master devices on the same bus are supported If two or more masters attempt to initiate a data transfer simultaneously an arbi...

Page 261: ...e winning master continues its transmission without interruption the losing master becomes a slave and receives the rest of the transfer This arbitration scheme is non destructive one device always wins and no data is lost 19 2 2 Clock Low Extension SMBus provides a clock synchronization mechanism similar to I2C which allows devices with different speed capabilities to coexist on the bus A clock l...

Page 262: ...e slave after each byte To indicate the end of the serial transfer SMBus0 generates a STOP condition Figure 19 4 Typical Master Transmitter Sequence 19 3 2 Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL The SMBus0 interface generates a START followed by the first data byte containing the address of the target slave and the data direction bit In this cas...

Page 263: ...serial clock is received on SCL The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit If the received slave address matches the address held in register SMB0ADR the interface generates an ACK SMBus0 will also ACK if the general call address 0x00 is received and the General Call Address Enable bit SMB0ADR 0 is set to logic 1 In this case the data...

Page 264: ...e for 50 µs and no STOP condition was recognized If STA is set to logic 1 while SMBus0 is in master mode and one or more bytes have been transferred a repeated START condition will be generated When the Stop flag STO SMB0CN 4 is set to logic 1 while the SMBus0 interface is in master mode the interface generates a STOP condition In a slave mode the STO flag may be used to recover from an error cond...

Page 265: ... than 50 µs see SFR Definition 19 2 SMBus0 Clock Rate Register When the TOE bit in SMB0CN is set to logic 1 Timer 3 is used to detect SCL low timeouts If Timer 3 is enabled see Section 23 2 Timer 2 Timer 3 and Timer 4 on page 317 Timer 3 is forced to reload when SCL is high and forced to count when SCL is low With Timer 3 enabled and configured to overflow after 25 ms and TOE set a Timer 3 overflo...

Page 266: ...g causes SMBus to behave as if a STOP condition was received Bit3 SI SMBus Serial Interrupt Flag This bit is set by hardware when one of 27 possible SMBus0 states is entered Status code 0xF8 does not cause SI to be set When the SI interrupt is enabled setting this bit causes the CPU to vector to the SMBus interrupt service routine This bit is not automatically cleared by hardware and must be clear...

Page 267: ...etting should be bounded by the following equation where SMB0CR is the unsigned 8 bit value in register SMB0CR and SYSCLK is the system clock frequency in MHz The resulting SCL signal high and low times are given by the following equations where SYSCLK is the system clock frequency in Hz Using the same value of SMB0CR from above the Bus Free Timeout period is given in the following equation R W R ...

Page 268: ... data in SMB0DAT SFR Definition 19 3 SMB0DAT SMBus0 Data 19 4 4 Address Register The SMB0ADR Address register holds the slave address for the SMBus0 interface In slave mode the seven most significant bits hold the 7 bit slave address The least significant bit Bit0 is used to enable the recognition of the general call address 0x00 If Bit0 is set to logic 1 the general call address will be recog niz...

Page 269: ...SMBus0 Slave Address These bits are loaded with the 7 bit slave address to which SMBus0 will respond when oper ating as a slave transmitter or slave receiver SLV6 is the most significant bit of the address and corresponds to the first bit of the address byte received Bit0 GC General Call Address Enable This bit is used to enable general call address 0x00 recognition 0 General call address is ignor...

Page 270: ...cknowledge poll to retry Set STO STA 0x28 Data byte transmitted ACK received 1 Load SMB0DAT with next byte OR 2 Set STO OR 3 Clear STO then set STA for repeated START 0x30 Data byte transmitted NACK received 1 Retry transfer OR 2 Set STO 0x38 Arbitration Lost Save current data Master Receiver 0x40 Slave Address R transmitted ACK received If only receiving one byte clear AA send NACK after received...

Page 271: ...Wait for next byte or STOP 0x98 Data byte received after general call address NACK transmitted Set STO to reset SMBus 0xA0 STOP or repeated START received No action necessary Slave Transmitter 0xA8 Own address R received ACK transmitted Load SMB0DAT with data to transmit 0xB0 Arbitration lost in transmitting SLA R W as master Own address R received ACK transmitted Save current data for retry when ...

Page 272: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 272 Rev 1 4 NOTES ...

Page 273: ...more than one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional gen eral purpose port I O pins can be used to select multiple slave devices in master mode Figure 20 1 SPI Block Diagram SFR Bus Data Path Control SFR Bus Write SPI0DAT Receive Data Buffer SPI0DAT 0 1 2 3 4 5 6 7 Shift Register SPI ...

Page 274: ...ster The SCK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 20 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register There are three possible modes that can be selected with these bits 1 NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode SPI0 operates in 3 wire mode ...

Page 275: ...multi master mode is active when NSS MD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 1 In this mode NSS is an input to the device and is used to disable the master SPI0 when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPI0CN 6 and SPIEN SPI0CN 0 are set to 0 to disable the SPI master device and a Mode Fault is generated MODF SPI0CN 5 1 Mode Fault will generate an interrupt if ...

Page 276: ...er and Slave Mode Connection Diagram Figure 20 4 4 Wire Single Master and Slave Mode Connection Diagram Master Device 2 Master Device 1 MOSI MISO SCK MISO MOSI SCK NSS GPIO NSS GPIO Slave Device Master Device MOSI MISO SCK MISO MOSI SCK Slave Device Master Device MOSI MISO SCK MISO MOSI SCK NSS NSS GPIO Slave Device MOSI MISO SCK NSS ...

Page 277: ... active when NSSMD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 0 NSS is not used in this mode and is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode SPI0 must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines wh...

Page 278: ...quency This register is ignored when operating in slave mode When the SPI is configured as a master the maximum data transfer rate bits sec is one half the system clock frequency or 12 5 MHz whichever is slower When the SPI is configured as a slave the maximum data transfer rate bits sec for full duplex operation is 1 10 the system clock frequency provided that the master issues SCK NSS in 4 wire ...

Page 279: ...ck Timing CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI SCK CKPOL 0 CKPHA 0 SCK CKPOL 1 CKPHA 0 SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI ...

Page 280: ...aneous value at the NSS pin but rather a de glitched version of the pin input Bit 2 NSSIN NSS Instantaneous Pin Input read only This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched Bit 1 SRMT Shift Register Empty Valid in Slave Mode read only This bit will be set to logic 1 when all data has been transferred...

Page 281: ...ata from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register This bit is not automatically cleared by hardware It must be cleared by software Bits 3 2 NSSMD1 NSSMD0 Slave Select Mode Selects between the following NSS operation modes See Section 20 2 SPI0 Master Mode Operation on page 275 and Section 20 3 SPI0 Slave Mode Operation on page 277 00 3 Wi...

Page 282: ...gister for 0 SPI0CKR 255 Example If SYSCLK 2 MHz and SPI0CKR 0x04 R W R W R W R W R W R W R W R W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x9D 0 fSCK SYSCLK 2 SPI0CKR 1 fSCK 2000000 2 4 1 fSCK 200kHz Bits 7 0 SPI0DAT SPI0 Transmit and Receive Data The SPI0DAT register is used to transmit and receive SPI0 data Writing...

Page 283: ...aster Timing CKPHA 0 Figure 20 9 SPI Master Timing CKPHA 1 SCK T MCKH T MCKL MOSI T MIS MISO SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIH SCK T MCKH T MCKL MISO T MIH MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIS ...

Page 284: ... SPI Slave Timing CKPHA 1 SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SEZ T SDZ SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SLH T SEZ T SDZ ...

Page 285: ...0 10 and Figure 20 11 TSE NSS Falling to First SCK Edge 2 x TSYSCLK ns TSD Last SCK Edge to NSS Rising 2 x TSYSCLK ns TSEZ NSS Falling to MISO Valid 4 x TSYSCLK ns TSDZ NSS Rising to MISO High Z 4 x TSYSCLK ns TCKH SCK High Time 5 x TSYSCLK ns TCKL SCK Low Time 5 x TSYSCLK ns TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK ns TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK ns TSOH SCK Shift Edge to...

Page 286: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 286 Rev 1 4 NOTES ...

Page 287: ...ed or interrupt mode UART0 has two sources of interrupts a Transmit Interrupt flag TI0 SCON0 1 set when transmission of a data byte is complete and a Receive Interrupt flag RI0 SCON0 0 set when reception of a data byte is complete UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine they must be cleared manually by soft ware This allows software t...

Page 288: ... TI0 Transmit Interrupt Flag SCON0 1 is set at the end of the eighth bit time Data reception begins when the REN0 Receive Enable bit SCON0 4 is set to logic 1 and the RI0 Receive Interrupt Flag SCON0 0 is cleared One cycle after the eighth bit is shifted in the RI0 flag is set and reception stops until software clears the RI0 bit An inter rupt will occur if enabled when either TI0 or RI0 are set T...

Page 289: ...0 Mode 1 Timing Diagram The baud rate generated in Mode 1 is a function of timer overflow UART0 can use Timer 1 operating in 8 Bit Auto Reload Mode or Timer 2 3 or 4 operating in Auto reload Mode to generate the baud rate note that the TX and RX clocks are selected separately On each timer overflow event a rollover from all ones 0xFF for Timer 1 0xFFFF for Timer 2 3 or 4 to zero a clock is sent to...

Page 290: ... or 4 are selected as a baud rate source the baud rate is generated as shown in Equation 21 3 The overflow rate for Timer 2 3 or 4 is determined by the clock source for the timer TnCLK and the 16 bit reload value stored in the RCAPn register n 2 3 or 4 as shown in Equation 21 4 Equation 21 2 Timer 1 Overflow Rate Timer1_OverflowRate T1CLK 256 TH1 Equation 21 3 Mode 1 Baud Rate using Timer 2 3 or 4...

Page 291: ...op bit time Data reception can begin any time after the REN0 Receive Enable bit SCON0 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the following requirements are met 1 SM20 is logic 0 2 SM20 is logic 1 the received 9th bit is logic 1 and the received address matches the UART0 address as described in Sec...

Page 292: ... rate generation Mode 3 operation transmits 11 bits a start bit 8 data bits LSB first a programmable ninth data bit and a stop bit The baud rate is derived from Timer 1 or Timer 2 3 or 4 overflows as defined by Equation 21 1 and Equation 21 3 Multiprocessor communications and hardware address recognition are supported as described in Section 21 2 OR RS 232 C8051Fxxx RS 232 LEVEL XLTR TX RX C8051Fx...

Page 293: ...ddress and include a ninth bit that is logic 1 21 2 2 Broadcast Addressing Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The broadcast address is the logical OR of registers SADDR0 and SADEN0 and 0 s of the result are treated as don t cares Typically a br...

Page 294: ...ds 1 if user software writes data to the SBUF0 register while a transmit is in progress Modes 1 2 and 3 The Receive Overrun bit RXOV0 in register SSTA0 reads 1 if a new data byte is latched into the receive buffer before software has read the previous byte The Frame Error bit FE0 in register SSTA0 reads 1 if an invalid low STOP bit is detected Master Device Slave Device TX RX RX TX Slave Device RX...

Page 295: ...200 1 8432 16 0xFF 0xFFFF 115200 100 0 3472 0x27 0xFF27 28800 28802 99 5328 3456 0x28 0xFF28 28800 50 0 1744 0x93 0xFF93 28800 28670 49 7664 1728 0x94 0xFF94 28800 24 0 832 0xCC 0xFFCC 28800 28846 22 1184 768 0xD0 0xFFD0 28800 18 432 640 0xD8 0xFFD8 28800 11 0592 348 0xE8 0xFFE8 28800 3 6864 128 0xF8 0xFFF8 28800 1 8432 64 0xFC 0xFFFC 28800 100 0 10416 0xFD75 9600 9601 99 5328 10368 0xFD78 9600 50...

Page 296: ... used in Modes 0 and 1 Set or cleared by software as required Bit2 RB80 Ninth Receive Bit The bit is assigned the logic level of the ninth bit received in Modes 2 and 3 In Mode 1 if SM20 is logic 0 RB80 is assigned the logic level of the received stop bit RB8 is not used in Mode 0 Bit1 TI0 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART0 after the 8th bit i...

Page 297: ...UART0 baud rate logic for config urations described in the UART0 section 0 UART0 baud rate divide by two enabled 1 UART0 baud rate divide by two disabled Bits3 2 UART0 Transmit Baud Rate Clock Selection Bits Bits1 0 UART0 Receive Baud Rate Clock Selection Bits Note FE0 RXOV0 and TXCOL0 are flags only and no interrupt is generated by these conditions R W R W R W R W R W R W R W R W Reset Value FE0 ...

Page 298: ...FR Page 0x99 0 Bits7 0 SADDR0 7 0 UART0 Slave Address The contents of this register are used to define the UART0 slave address Register SADEN0 is a bit mask to determine which bits of SADDR0 are checked against a received address corresponding bits set to logic 1 in SADEN0 are checked corresponding bits set to logic 0 are don t cares R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 B...

Page 299: ...ister writing SBUF1 accesses the Transmit register With UART1 interrupts enabled an interrupt is generated each time a transmit is completed TI1 is set in SCON1 or a data byte has been received RI1 is set in SCON1 The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the c...

Page 300: ...load on page 311 The Timer 1 reload value should be set so that overflows will occur at two times the desired baud rate Note that Timer 1 may be clocked by one of five sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 or the external oscillator clock 8 For any given Timer 1 clock source the UART1 baud rate is determined by Equation 22 1 Where T1CLK is the frequency of the clock supplied to Timer 1 and T...

Page 301: ...eginning of the stop bit time Data recep tion can begin any time after the REN1 Receive Enable bit SCON1 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met RI1 must be logic 0 and if MCE1 is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latch...

Page 302: ...1 is set at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the REN1 Receive Enable bit SCON1 4 is set to 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met 1 RI1 must be logic 0 and 2 if MCE1 is logic 1 the 9th bit must be logic 1 when MCE1 is logic 0 the state of ...

Page 303: ...igned 8 bit address If the addresses match the slave should clear its MCE1 bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave should reset its MCE1 bit to ignore all ...

Page 304: ...ill be assigned to the ninth transmission bit in 9 bit UART Mode It is not used in 8 bit UART Mode Set or cleared by software as required Bit2 RB81 Ninth Receive Bit RB81 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 Bit1 TI1 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART1 after the 8th bit in 8 bit ...

Page 305: ...6 14400 0 15 1704 SYSCLK 12 00 0 0xB9 9600 0 32 2544 SYSCLK 12 00 0 0x96 2400 0 32 10176 SYSCLK 48 10 0 0x96 1200 0 15 20448 SYSCLK 48 10 0 0x2B X Don t care Note SCA1 SCA0 and T1M bit definitions can be found in Section 23 1 Bits7 0 SBUF1 7 0 Serial Data Buffer Bits 7 0 MSB LSB This SFR accesses two registers a transmit shift register and a receive latch register When data is written to SBUF1 it ...

Page 306: ... 0 0x5D X Don t care Note SCA1 SCA0 and T1M bit definitions can be found in Section 23 1 Table 22 3 Timer Settings for Standard Baud Rates Using an External 22 1184 MHz Oscillator Frequency 22 1184 MHz Target Baud Rate bps Baud Rate Error Oscilla tor Divide Factor Timer Clock Source SCA1 SCA0 pre scale select T1M Timer 1 Reload Value hex SYSCLK from External Osc 230400 0 00 96 SYSCLK XX 1 0xD0 115...

Page 307: ...5208 SYSCLK 12 00 0 0x27 2400 0 01 20832 SYSCLK 48 10 0 0x27 X Don t care Note SCA1 SCA0 and T1M bit definitions can be found in Section 23 1 Table 22 5 Timer Settings for Standard Baud Rates Using the PLL Frequency 100 0 MHz Target Baud Rate bps Baud Rate Error Oscilla tor Divide Factor Timer Clock Source SCA1 SCA0 pre scale select T1M Timer 1 Reload Value hex 230400 0 01 434 SYSCLK XX 1 0x27 115...

Page 308: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 308 Rev 1 4 NOTES ...

Page 309: ...odic but it should be held at a given logic level for at least two full system clock cycles to ensure the level is properly sampled 23 1 Timer 0 and Timer 1 Each timer is implemented as a 16 bit register accessed as two separate 8 bit SFRs a low byte TL0 or TL1 and a high byte TH0 or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate their status ...

Page 310: ...tting GATE0 to 1 allows the timer to be controlled by the external input signal INT0 see Section 11 3 5 Interrupt Register Descriptions on page 157 facilitating pulse width mea surements Setting TR0 does not force the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as ...

Page 311: ...r in TL0 is reloaded from TH0 If Timer 0 interrupts are enabled an interrupt will occur when the TF0 flag is set The reload value in TH0 is not changed TL0 must be initialized to the desired value before enabling the timer for the first count to be cor rect When in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 S...

Page 312: ... interrupt Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled th...

Page 313: ... be cleared by software but is automatically cleared when the CPU vectors to the External Inter rupt 1 service routine if IT1 1 This flag is the inverse of the INT1 signal Bit2 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be falling edge sensitive or active low 0 INT1 is level triggered active low 1 INT1 is edge triggered falling edge Bit1 IE0 External In...

Page 314: ...1 Timer 0 enabled only when TR0 1 AND INT0 logic 1 Bit2 C T0 Counter Timer Select 0 Timer Function Timer 0 incremented by clock defined by T0M bit CKCON 3 1 Counter Function Timer 0 incremented by high to low transitions on external input pin T0 Bits1 0 T0M1 T0M0 Timer 0 Mode Select These bits select the Timer 0 operation mode R W R W R W R W R W R W R W R W Reset Value GATE1 C T1 T1M1 T1M0 GATE0 ...

Page 315: ...ite don t care Bits1 0 SCA1 SCA0 Timer 0 1 Prescale Bits These bits control the division of the clock supplied to Timer 0 and or Timer 1 if configured to use prescaled clock inputs R W R W R W R W R W R W R W R W Reset Value T1M T0M SCA1 SCA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x8E 0 SCA1 SCA0 Prescaled Clock 0 0 System clock divided by 12 0 1 System clock divide...

Page 316: ...t Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x8B 0 Bits 7 0 TH0 Timer 0 High Byte The TH0 register is the high byte of the 16 bit Timer 0 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0x8C 0 Bits 7 0 TH1 Timer 1 High Byte The TH1 register is the high byte of the 16 bit Timer 1 R W R W R W R W R W ...

Page 317: ...r timer register Timer 3 and Timer 2 share the T2 input pin Refer to Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 238 for information on selecting and configuring external I O pins for digital peripherals such as the Tn pin Timer 2 3 and 4 can use either SYSCLK SYSCLK divided by 2 SYSCLK divided by 12 an external clock divided by 8 or high to low transitions on the Tn i...

Page 318: ... is set to 1 and an interrupt will occur if the interrupt is enabled The timer can be config ured to count down by setting the Decrement Enable Bit TMRnCF 0 to 1 This will cause the timer to decrement with every timer clock count event and underflow when the timer transitions from 0x0000 to 0xFFFF Just as in overflows the Overflow Underflow Flag TFn will be set to 1 and an interrupt will occur if ...

Page 319: ...r 2 See Section 23 2 1 for information concerning configuration of a timer to count down When counting down the counter timer will set its overflow underflow flag TFn and cause an interrupt if enabled when the value in the TMRnH and TMRnL registers matches the 16 bit value in the Reload Cap ture Registers RCAPnH and RCAPnL This is considered an underflow event and will cause the timer to load the ...

Page 320: ... reload value To output a square wave the timer is placed in reload mode the Capture Reload Select Bit in TMRnCN and the Timer Counter Select Bit in TMRnCN are cleared to 0 The timer output is enabled by setting the Timer Output Enable Bit in TMRnCF to 1 The timer should be configured via the timer clock source and reload underflow values such that the timer overflow underflows at 1 2 the desired ...

Page 321: ... TnEX will determine if the timer counts up or down when in Auto reload Mode If EXENn 1 TnEX should be configured as a digital input 0 Transitions on the TnEX pin are ignored 1 Transitions on the TnEX pin cause capture reload or control the direction of timer count up or down as follows Capture Mode 1 to 0 Transition on TnEX pin causes RCAPnH RCAPnL to capture timer value Auto Reload Mode DCENn 0 ...

Page 322: ... assigned external port pin NOTE A timer is configured for Square Wave Output as follows CP RLn 0 C Tn 0 TnOE 1 Load RCAPnH RCAPnL See Square Wave Frequency Timer 2 and Timer 4 Only on page 320 Configure Port Pin to output squarewave See Section 18 Port Input Output on page 235 0 Output of toggle mode not available at Timers s assigned port pin 1 Output of toggle mode available at Timers s assigne...

Page 323: ...0xCA RCAP4L 0xCA SFR Page RCAP2L page 0 RCAP3L page 1 RCAP4L page 2 Bits 7 0 RCAP2 3 and 4H Timer 2 3 and 4 Capture Register High Byte The RCAP2 3 and 4H register captures the high byte of Timer 2 3 and 4 when Timer 2 3 and 4 is configured in capture mode When Timer 2 3 and 4 is configured in auto reload mode it holds the high byte of the reload value R W R W R W R W R W R W R W R W Reset Value 00...

Page 324: ...ts 7 0 TH2 3 and 4 Timer 2 3 and 4 High Byte The TH2 3 and 4 register contains the high byte of the 16 bit Timer 2 3 and 4 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address TMR2H 0xCD TMR3H 0xCD TMR4H 0xCD SFR Page TMR2H page 0 TMR3H page 1 TMR4H page 2 ...

Page 325: ... divided by four system clock divided by twelve the external oscillator clock source divided by 8 Timer 0 overflow or an external clock signal on the ECI line Each capture compare module may be configured to operate inde pendently in one of six modes Edge Triggered Capture Software Timer High Speed Output Frequency Output 8 Bit PWM or 16 Bit PWM each is described in Section 24 2 The PCA is configu...

Page 326: ...lly cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Note PCA0 interrupts must be globally enabled before CF interrupts are recognized PCA0 inter rupts are globally enabled by setting the EA bit IE 7 and the EPCA0 bit in EIE1 to logic 1 Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is...

Page 327: ...of counter overflows the following steps should be taken when performing a bit wise operation on the PCA0CN register Step 1 Disable global interrupts Step 2 Read PCA0L This will latch the value of PCA0H Step 3 Read PCA0H saving the value Step 4 Execute the bit wise operation on CCFn for example CLR CCF0 or CCF0 0 Step 5 Read PCA0L Step 6 Read PCA0H saving the value Step 7 If the value of PCA0H rea...

Page 328: ...ing the ECCFn bit in a PCA0CPMn register enables the module s CCFn interrupt Note PCA0 interrupts must be globally enabled before individual CCFn interrupts are rec ognized PCA0 interrupts are globally enabled by setting the EA bit IE 7 and the EPCA0 bit EIE1 3 to logic 1 See Figure 24 3 for details on the PCA interrupt configuration Figure 24 3 PCA Interrupt Block Diagram PCA0CN C F C R C C F 0 C...

Page 329: ...ors to the interrupt service routine and must be cleared by software Figure 24 4 PCA Capture Mode Diagram Note The signal at CEXn must be high or low for at least 2 system clock cycles in order to be valid Table 24 2 PCA0CPM Register Settings for PCA Capture Compare Modules PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF Operation Mode X X 1 0 0 0 0 X Capture triggered by positive edge on CEXn X X 0 1 0 0 0...

Page 330: ...ed by software Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 24 5 PCA Software Timer Mode Diagram Match 16 bit Comp...

Page 331: ...ompare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 24 6 PCA High Speed Output Mode Diagram Match 16 bit Comparator PCA0H PCA0CPHn Enable PCA0L PCA Timebase PCA0CPLn PCA Interrupt 0 1 0 0 0 x ENB ENB 0 1 Write to PCA0CPLn Write to PCA0C...

Page 332: ... high byte is added to the matched value in PCA0CPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCA0CPMn reg ister Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 24...

Page 333: ...flows from 0xFF to 0x00 PCA0CPLn is reloaded automatically with the value stored in the counter timer s high byte PCA0H with out software intervention Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8 Bit Pulse Width Modulator mode The duty cycle for 8 Bit PWM Mode is given by Equation 24 2 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capt...

Page 334: ... PWMn and PWM16n bits in the PCA0CPMn register For a varying duty cycle CCFn should also be set to logic 1 to enable match inter rupts The duty cycle for 16 Bit PWM Mode is given by Equation 24 3 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 w...

Page 335: ...s bit is not automatically cleared by hardware and must be cleared by software Bit3 CCF3 PCA0 Module 3 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF interrupt is enabled setting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit2 CCF2 PCA0 Module ...

Page 336: ...unter Bit0 ECF PCA Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCA0 Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCA0 Counter Timer Overflow interrupt request when CF PCA0CN 7 is set R W R W R W R W R W R W R W R W Reset Value CIDL CPS2 CPS1 CPS0 ECF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xD9 0 CPS2 CPS1 CPS0...

Page 337: ...bles disables the toggle function for PCA0 module n When enabled matches of the PCA0 counter with a module s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module operates in Frequency Output Mode 0 Disabled 1 Enabled Bit1 PWMn Pulse Width Modulation Mode Enable This bit enables disables the PWM function for PCA0 module n When en...

Page 338: ...0 Bits 7 0 PCA0H PCA0 Counter Timer High Byte The PCA0H register holds the high byte MSB of the 16 bit PCA0 Counter Timer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0xFA 0 Bits7 0 PCA0CPLn PCA0 Capture Module Low Byte The PCA0CPLn register holds the low byte LSB of the 16 bit capture module n R W R W R W R W R W R W R W R W Res...

Page 339: ...CA0CPHn register holds the high byte MSB of the 16 bit capture module n R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address PCA0CPH0 0xFC PCA0CPH1 0xFD PCA0CPH2 0xEA PCA0CPH3 0xEC PCA0CPH4 0xEE PCA0CPH5 0xE2 SFR Page PCA0CPH0 page 0 PCA0CPH1 page 0 PCA0CPH2 page 0 PCA0CPH3 page 0 PCA0CPH4 page 0 PCA0CPH5 page 0 ...

Page 340: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 340 Rev 1 4 NOTES ...

Page 341: ...d There are three DR s associated with JTAG Boundary Scan and four associated with Flash read write operations on the MCU JTAG Register Definition 25 1 IR JTAG Instruction Register Reset Value 0x0000 Bit15 Bit0 IR Value Instruction Description 0x0000 EXTEST Selects the Boundary Data Register for control and observability of all device pins 0x0002 SAMPLE PRELOAD Selects the Boundary Data Register f...

Page 342: ...18 20 Capture P0 n output enable from MCU e g Bit6 P0 0 Bit8 P0 1 etc Update P0 n output enable to pin e g Bit6 P0 0oe Bit8 P0 1oe etc 7 9 11 13 15 17 19 21 Capture P0 n input from pin e g Bit7 P0 0 Bit9 P0 1 etc Update P0 n output to pin e g Bit7 P0 0 Bit9 P0 1 etc 22 24 26 28 30 32 34 36 Capture P1 n output enable from MCU Update P1 n output enable to pin 23 25 27 29 31 33 35 37 Capture P1 n inp...

Page 343: ...r 25 1 4 IDCODE Instruction The IDCODE instruction is accessed via the IR It provides access to the 32 bit Device ID register JTAG Register Definition 25 2 DEVICEID JTAG Device ID Bit Action Target 103 105 107 109 111 113 115 117 Capture P6 n input from pin Update P6 n output to pin 118 120 122 124 126 128 130 132 Capture P7 n output enable from MCU Update P7 n output enable to pin 119 121 123 125...

Page 344: ... bits can be written If the register to be written contains fewer than 18 bits the data in Write Data should be left justified i e its MSB should occupy bit 17 above This allows shorter registers to be written in fewer JTAG clock cycles For example an 8 bit register could be written by shifting only 10 bits After a Write is initiated the Busy bit should be polled to determine when the next operati...

Page 345: ... address by the FLASHADR register FLASHADR is incremented by one when complete 010 A FLASHDAT write initiates an erasure sets all bytes to 0xFF of the Flash page containing the address in FLASHADR The data written must be 0xA5 for the erase to occur FLASHADR is not affected If FLASHADR 0x1FBFE 0x1FBFF the entire user space will be erased i e entire Flash memory except for Reserved area 0x1FC00 0x1...

Page 346: ...vious Flash memory operation failed Usually indicates the associated memory loca tion was locked Bit0 BUSY Flash Busy Bit 0 Flash interface logic is not busy 1 Flash interface logic is processing a request Reads or writes while BUSY 1 will not initi ate another operation Reset Value 0000000000 Bit9 Bit0 This register holds the address for all JTAG Flash read write and erase operations This registe...

Page 347: ... channels are required All the digital and analog peripherals are functional and work correctly remain synchronized while debugging The Watch dog Timer WDT is disabled when the MCU is halted during single stepping or at a breakpoint The C8051F120DK is a development kit with all the hardware and software necessary to develop applica tion code and perform in circuit debug with each MCU in the C8051F...

Page 348: ...C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 348 Rev 1 4 NOTES ...

Page 349: ...scillator Diagram Corrected location of IOSCEN arrow CIP51 Chapter Section 11 3 Added note describing EA change behavior when followed by single cycle instruction CIP51 Chapter Interrupt Summary Table Added SFRPAGE column and SFRPAGE value for each interrupt source CIP 51 Chapter Figure 11 2 Memory Map Corrected on chip XRAM size to 8192 Bytes Port I O Chapter Crossbar Priority Figures Character f...

Page 350: ...or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons...