C8051F12x-DK
8
Rev. 0.6
7.6. PORT I/O Connectors (J12 - J19)
In addition to all port I/O signals being routed to the 96-pin expansion connector, each of the eight parallel ports of
the C8051F120 has its own 10-pin header connector. Each connector provides a pin for the corresponding port
pins 0-7, +3.3 VDC and digital ground. Table 5 defines the pins for the port connectors. The same pin-out order is
used for all of the port connectors.
7.7. VDD Monitor Disable (J23)
The VDD Monitor of the C8051F120 may be disabled by moving the shorting block on J23 from pins 1-2 to pins 2-
3, as shown in Figure 4.
Pin #
Description
1
Pn.0
2
Pn.1
3
Pn.2
4
Pn.3
5
Pn.4
6
Pn.5
7
Pn.6
8
Pn.7
9
+3 VD (+3.3 VDC)
10
GND (Ground)
Table 5. J12- J19 Port Connector Pin Descriptions
1
3
2
MONEN
Figure 4. VDD Monitor Hardware Setup
