Silicon Laboratories C8051F12X User Manual Download

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C8051F12x-DK

Rev. 0.6

7.8. Expansion I/O Connector (J24)

The 96-pin expansion I/O connector J24 is used to connect daughter boards to the main target board. J24 provides
access to many C8051F120 signal pins. Pins for +3 V, digital ground, analog ground and the unregulated power
supply (VUNREG) are also available. The VUNREG pin is connected directly to the unregV pin of the P1
power connector. See Table 6 for a complete list of pins available at J24.

The J24 socket connector is manufactured by Hirose Electronic Co. Ltd, part number PCN13-96S-2.54DS, Digi-
Key part number H7096-ND. The corresponding plug connector is also manufactured by Hirose Electronic Co. Ltd,
part number PCN10-96P-2.54DS, Digi-Key part number H5096-ND.

Pin #

Description

Pin #

Description

Pin #

Description

A-1

+3 VD2 (+3.3 VDC)

B-1

DGND (Digital Gnd)

C-1

XTAL1

A-2

MONEN

B-2

P1.7

C-2

P1.6

A-3

P1.5

B-3

P1.4

C-3

P1.3

A-4

P1.2

B-4

P1.1

C-4

P1.0

A-5

P2.7

B-5

P2.6

C-5

P2.5

A-6

P2.4

B-6

P2.3

C-6

P2.2

A-7

P2.1

B-7

P2.0

C-7

P3.7

A-8

P3.6

B-8

P3.5

C-8

P3.4

A-9

P3.3

B-9

P3.2

C-9

P3.1

A-10

P3.0

B-10

P0.7

C-10

P0.6

A-11

P0.5

B-11

P0.4

C-11

P0.3

A-12

P0.2

B-12

P0.1

C-12

P0.0

A-13

P7.7

B-13

P7.6

C-13

P7.5

A-14

P7.4

B-14

P7.3

C-14

P7.2

A-15

P7.1

B-15

P7.0

C-15

P6.7

A-16

P6.6

B-16

P6.5

C-16

P6.4

A-17

P6.3

B-17

P6.2

C-17

P6.1

A-18

P6.0

B-18

P5.7

C-18

P5.6

A-19

P5.5

B-19

P5.4

C-19

P5.3

A-20

P5.2

B-20

P5.1

C-20

P5.0

A-21

P4.7

B-21

P4.6

C-21

P4.5

A-22

P4.4

B-22

P4.3

C-22

P4.2

A-23

P4.1

B-23

P4.0

C-23

TMS

A-24

TCK

B-24

TDI

C-24

TDO

A-25

/RST

B-25 DGND (Digital Gnd)

C-25

VUNREG

A-26 AGND (Analog Gnd)

B-26

DAC1

C-26

DAC0

A-27

CP1-

B-27

CP1+

C-27

CP0-

A-28

CP0+

B-28

VREF

C-28

VREFD

A-29

VREF0

B-29

VREF1

C-29

AIN0.7

A-30

AIN0.6

B-30

AIN0.5

C-30

AIN0.4

A-31

AIN0.3

B-31

AIN0.2

C-31

AIN0.1

A-32

AIN0.0

B-32 AGND (Analog Gnd)

C-32 AV+ (+3.3 VDC Analog)

Table 6. J24 Pin Descriptions

Summary of Contents for C8051F12X

Page 1: ...able 2 Hardware Setup using an EC2 Serial Adapter Connect the target board to a PC running the Silicon Laboratories IDE via the Serial Adapter as shown in Figure 1 1 Connect one end of the RS232 serial cable to a serial COM port on the PC 2 Connect the other end of the RS232 serial cable to the DB 9 connector on the Serial Adapter 3 Connect the Serial Adapter to the JTAG connector on the target bo...

Page 2: ...ment IDE Keil software 8051 tools and additional documentation Insert the CD ROM into your PC s CD ROM drive An installer will auto matically launch allowing you to install the IDE software or read documentation by clicking buttons on the Installa tion Panel If the installer does not automatically start when you insert the CD ROM run autorun exe found in the root directory of the CD ROM Refer to t...

Page 3: ...ing the Silicon Laboratories IDE project manager you must first create a project A project consists of a set of files IDE configuration debug views and a target build configuration list of files and tool configurations used as input to the assembler compiler and linker when building an output object file The following sections illustrate the steps necessary to manually create a project with one or...

Page 4: ...6 Example Source Code Example source code and register definition files are provided in the SiLabs MCU Examples C8051F12x directory during IDE installation These files may be used as a template for code development Example applications include a blinking LED example which configures the green LED on the target board to blink at a fixed rate 6 1 Register Definition Files Register definition files C...

Page 5: ... 7 pin J3 Connects LED D3 to P1 6 pin J4 JTAG connector for Debug Adapter interface J5 DB 9 connector for UART0 RS232 interface J6 Connector for UART0 TX P0 0 J8 Connector for UART0 RTS P4 0 J9 Connector for UART0 RX P0 1 J10 Connector for UART0 CTS P4 1 J11 Analog loopback connector J12 J19 Port 0 7 connectors J20 Analog I O terminal block J22 VREF connector J23 VDD Monitor Disable J24 96 pin Exp...

Page 6: ...lock from the header to disconnect SW2 from the port pins The port pin signal is also routed to a pin on the J24 I O connector See Table 1 for the port pins and headers corresponding to each switch Two LEDs are also provided on the target board The red LED labeled PWR is used to indicate a power connection to the target board The green LED labeled with a port pin name is connected to the C8051F120...

Page 7: ... J10 Install shorting block to connect UART0 CTS P4 1 to the transceiver 7 5 Analog I O J11 J20 Several C8051F120 analog signals are routed to the J20 terminal block and the J11 header The J11 connector provides the ability to connect DAC0 and DAC1 outputs to several different analog inputs by installing a shorting block between a DAC output and an analog input on adjacent pins of J11 Refer to Tab...

Page 8: ... 3 VDC and digital ground Table 5 defines the pins for the port connectors The same pin out order is used for all of the port connectors 7 7 VDD Monitor Disable J23 The VDD Monitor of the C8051F120 may be disabled by moving the shorting block on J23 from pins 1 2 to pins 2 3 as shown in Figure 4 Pin Description 1 Pn 0 2 Pn 1 3 Pn 2 4 Pn 3 5 Pn 4 6 Pn 5 7 Pn 6 8 Pn 7 9 3 VD 3 3 VDC 10 GND Ground Ta...

Page 9: ...d C 1 XTAL1 A 2 MONEN B 2 P1 7 C 2 P1 6 A 3 P1 5 B 3 P1 4 C 3 P1 3 A 4 P1 2 B 4 P1 1 C 4 P1 0 A 5 P2 7 B 5 P2 6 C 5 P2 5 A 6 P2 4 B 6 P2 3 C 6 P2 2 A 7 P2 1 B 7 P2 0 C 7 P3 7 A 8 P3 6 B 8 P3 5 C 8 P3 4 A 9 P3 3 B 9 P3 2 C 9 P3 1 A 10 P3 0 B 10 P0 7 C 10 P0 6 A 11 P0 5 B 11 P0 4 C 11 P0 3 A 12 P0 2 B 12 P0 1 C 12 P0 0 A 13 P7 7 B 13 P7 6 C 13 P7 5 A 14 P7 4 B 14 P7 3 C 14 P7 2 A 15 P7 1 B 15 P7 0 C...

Page 10: ...Silicon Laboratories JTAG and C2 debug interfaces All Serial Adapters may be powered from the tar get board but the EC1 and EC2 Serial Adapter units cannot provide power to the target board Table 7 shows the pin definitions for the Serial Adapter s DEBUG connector Notes When powering the Serial Adapter via the DEBUG connector the input voltage to the DEBUG connector s power pin must be 3 0 to 3 6 ...

Page 11: ... USB connection to the PC The USB Debug Adapter is capable of providing power to a circuit board via pin 10 of the DEBUG connector The C8051F120 Tar get Board is not designed to be powered from this source Table 8 shows the pin definitions for the DEBUG ribbon cable connector Notes The USB Debug Adapter requires a target system clock of 32 KHz or greater With the default settings the USB Debug Ada...

Page 12: ...C8051F12x DK 12 Rev 0 6 10 Schematic Figure 7 C8051F120 Target Board Schematic ...

Page 13: ... Hardware Setup using a USB Debug Adapter Section 5 4 2 changed step 2 to include new instructions Section 7 J4 changed Serial Adapter to Debug Adapter Target Board DEBUG Interface Section added USB Debug Adapter DEBUG Connector Pin Descriptions Table changed pin 4 to C2D Changed jumper to header EC2 Serial Adapter section added EC2 to the section title table title and figure title EC2 Serial Adap...

Page 14: ...y for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and speci...

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