Silicon Laboratories C8051F300, Manual

Page 1: ...ure executes 70 of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz clock Expanded interrupt handler Memory 256 bytes internal data RAM Up to 8 kB F300 1 2 3 4 kB F304 or 2 kB F305 Flash 512 bytes are reserved in the 8 kB devices Digital Peripherals 8 Port I O All 5 V tolerant with high sink current Hardware enhanced UART and SMBus serial ports Three general purpose 16 bit...

Page 2: ...C8051F300 1 2 3 4 5 2 Rev 2 9 NOTES ...

Page 3: ...mperature Sensor 36 5 3 Modes of Operation 39 5 3 1 Starting a Conversion 39 5 3 2 Tracking Modes 40 5 3 3 Settling Time Requirements 41 5 4 Programmable Window Detector 45 5 4 1 Window Detector In Single Ended Mode 45 5 4 2 Window Detector In Differential Mode 46 6 Voltage Reference C8051F300 2 49 7 Comparator0 51 8 CIP 51 Microcontroller 57 8 1 Instruction Set 58 8 1 1 Instruction and CPU Timing...

Page 4: ... 2 Non Volatile Data Storage 90 10 3 Security Options 90 10 4 Flash Write and Erase Guidelines 94 10 4 1 VDD Maintenance and the VDD monitor 94 10 4 2 PSWE Maintenance 94 10 4 3 System Clock 95 11 Oscillators 97 11 1 Programmable Internal Oscillator 97 11 2 External Oscillator Drive Circuit 99 11 3 System Clock Selection 99 11 4 External Crystal Example 101 11 5 External RC Example 102 11 6 Extern...

Page 5: ...ounter Timer 145 15 1 3 Mode 2 8 bit Counter Timer with Auto Reload 145 15 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only 146 15 2 Timer 2 151 15 2 1 16 bit Timer with Auto Reload 151 15 2 2 8 bit Timers with Auto Reload 152 16 Programmable Counter Array 155 16 1 PCA Counter Timer 156 16 2 Capture Compare Modules 157 16 2 1 Edge triggered Capture Mode 158 16 2 2 Software Timer Compare Mode 159 1...

Page 6: ...C8051F300 1 2 3 4 5 6 Rev 2 9 NOTES ...

Page 7: ...ng Diagram 31 Figure 4 5 SOIC 14 Pinout Diagram Top View 32 Figure 4 6 SOIC 14 Package Drawing 33 Figure 4 7 SOIC 14 PCB Land Pattern 34 5 ADC0 8 Bit ADC C8051F300 2 Figure 5 1 ADC0 Functional Block Diagram 35 Figure 5 2 Typical Temperature Sensor Transfer Function 37 Figure 5 3 Temperature Sensor Error with 1 Point Calibration VREF 2 40 V 38 Figure 5 4 8 Bit ADC Track and Conversion Example Timin...

Page 8: ...ART0 Block Diagram 131 Figure 14 2 UART0 Baud Rate Logic 132 Figure 14 3 UART Interconnect Diagram 133 Figure 14 4 8 Bit UART Timing Diagram 133 Figure 14 5 9 Bit UART Timing Diagram 134 Figure 14 6 UART Multi Processor Mode Interconnect Diagram 135 15 Timers Figure 15 1 T0 Mode 0 Block Diagram 144 Figure 15 2 T0 Mode 2 Block Diagram 145 Figure 15 3 T0 Mode 3 Block Diagram 146 Figure 15 4 Timer 2 ...

Page 9: ...cteristics 55 8 CIP 51 Microcontroller Table 8 1 CIP 51 Instruction Set Summary 59 Table 8 2 Special Function Register SFR Memory Map 66 Table 8 3 Special Function Registers 66 Table 8 4 Interrupt Summary 74 9 Reset Sources Table 9 1 User Code Space Address Limits 86 Table 9 2 Reset Electrical Characteristics 86 10 Flash Memory Table 10 1 Flash Electrical Characteristics 90 Table 10 2 Security Byt...

Page 10: ...or 140 Table 14 5 Timer Settings for Standard Baud Rates Using an External 11 0592 MHz Oscillator 141 Table 14 6 Timer Settings for Standard Baud Rates Using an External 3 6864 MHZ Oscillator 142 15 Timers 16 Programmable Counter Array Table 16 1 PCA Timebase Input Options 156 Table 16 2 PCA0CPM Register Settings for PCA Capture Compare Modules 157 Table 16 3 Watchdog Timer Timeout Intervals 166 1...

Page 11: ... 1 77 SFR Definition 8 10 EIP1 Extended Interrupt Priority 1 78 SFR Definition 8 11 IT01CF INT0 INT1 Configuration 79 SFR Definition 8 12 PCON Power Control 81 SFR Definition 9 1 RSTSRC Reset Source 87 SFR Definition 10 1 PSCTL Program Store R W Control 92 SFR Definition 10 2 FLKEY Flash Lock and Key 93 SFR Definition 10 3 FLSCL Flash Scale 93 SFR Definition 11 1 OSCICL Internal Oscillator Calibra...

Page 12: ...igh Byte 154 SFR Definition 16 1 PCA0CN PCA Control 167 SFR Definition 16 2 PCA0MD PCA Mode 168 SFR Definition 16 3 PCA0CPMn PCA Capture Compare Mode 169 SFR Definition 16 4 PCA0L PCA Counter Timer Low Byte 170 SFR Definition 16 5 PCA0H PCA Counter Timer High Byte 170 SFR Definition 16 6 PCA0CPLn PCA Capture Module Low Byte 171 SFR Definition 16 7 PCA0CPHn PCA Capture Module High Byte 171 C2 Regis...

Page 13: ...imer and clock oscillator the C8051F300 1 2 3 4 5 devices are truly stand alone System on a Chip solutions The Flash memory can be reprogrammed even in circuit providing non volatile data storage and also allowing field upgrades of the 8051 firmware User software has complete control of all peripherals and may individually shut down any or all peripherals for power savings The on chip Silicon Labo...

Page 14: ...ad free RoHS compliant Package C8051F300 GM 25 8 k 256 3 8 1 QFN 11 C8051F300 GS 25 8 k 256 3 8 1 SOIC 14 C8051F301 GM 25 8 k 256 3 8 1 QFN 11 C8051F301 GS 25 8 k 256 3 8 1 SOIC 14 C8051F302 GM 25 8 k 256 3 8 1 QFN 11 C8051F302 GS 25 8 k 256 3 8 1 SOIC 14 C8051F303 GM 25 8 k 256 3 8 1 QFN 11 C8051F303 GS 25 8 k 256 3 8 1 SOIC 14 C8051F304 GM 25 4 k 256 3 8 1 QFN 11 C8051F304 GS 25 4 k 256 3 8 1 SO...

Page 15: ...Digital Power Debug HW VDD ADC Config Control SMBus x2 x4 x2 C2D C2D CP0 PGA Temp CP0 P0 0 VREF P0 1 P0 2 XTAL1 P0 3 XTAL2 P0 4 TX P0 5 RX P0 6 CNVSTR P0 7 C2D VDD GND RST C2CK Brown Out VDD CNVSTR Port 0 Latch UART 8k 4k 2k byte FLASH 256 byte SRAM POR SFR Bus 8 0 5 1 C o r e Timer 0 1 PCA WDT P 0 D r v X B A R Port I O Mode Config XBAR Control Reset XTAL1 XTAL2 External Oscillator Circuit System...

Page 16: ...ction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 MHz By contrast the CIP 51 core exe cutes 70 of its instructions in one or two system clock cycles with only four instructions taking more than four system clock cycles The CIP 51 has a total of 109 ins...

Page 17: ... WDT may be permanently enabled in software after a power on reset during MCU initialization The internal oscillator is available as a factory calibrated 24 5 MHz 2 C8051F300 1 devices an uncal ibrated version is available on C8051F302 3 4 5 devices On all C8051F300 1 2 3 4 5 devices the internal oscillator period may be user programmed in 0 5 increments An external oscillator drive circuit is als...

Page 18: ...le The C8051F300 1 2 3 includes 8k bytes of Flash program memory the C8051F304 includes 4k bytes the C8051F305 includes 2k bytes This memory may be reprogrammed in system in 512 byte sectors and requires no special off chip programming voltage See Figure 1 5 for the C8051F300 1 2 3 system memory map Figure 1 5 On chip Memory Map C8051F300 1 2 3 Shown PROGRAM MEMORY Direct and Indirect Addressing 0...

Page 19: ...bug adapter It also has a target application board with the associated MCU installed and large prototyping area plus the nec essary communication cables and wall mount power supply The Development Kit requires a computer with Windows 98 SE or later The Silicon Labs IDE interface is a vastly superior developing and debug ging configuration compared to standard MCU emulators that use onboard ICE Chi...

Page 20: ... the exact mix of general purpose Port I O and digital resources needed for the particular application Figure 1 7 Digital Crossbar Diagram 1 5 Serial Ports The C8051F300 1 2 3 4 5 Family includes an SMBus I2C interface and a full duplex UART with enhanced baud rate configuration Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP 51 s interrupts thus requir...

Page 21: ...lity where the PCA is clocked by an external source while the internal oscillator drives the system clock Each capture compare module can be configured to operate in one of six modes Edge Triggered Capture Software Timer High Speed Output 8 or 16 bit Pulse Width Modulator or Frequency Output Additionally Capture Compare Module 2 offers watchdog timer WDT capabilities Following a system reset Modul...

Page 22: ...a software command an overflow of Timer 0 1 or 2 or an exter nal convert start signal This flexibility allows the start of conversion to be triggered by software events a periodic signal timer overflows or external HW signals Conversion completions are indicated by a status bit and an interrupt if enabled The resulting 8 bit data word is latched into an SFR upon completion of a conversion Window c...

Page 23: ...output Comparator response time is programmable allowing the user to select between high speed and low power modes Positive and negative hysteresis is also configurable Comparator interrupts may be generated on rising falling or both edges When in IDLE mode these inter rupts may be used as a wake up source The comparator may also be configured as a reset source Figure 1 11 Comparator Block Diagram...

Page 24: ...ND 0 3 4 2 V Maximum Total current through VDD and GND 500 mA Maximum output current sunk by RST or any Port pin 100 mA Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is ...

Page 25: ...upply Current CPU Active Normal Mode fetching instructions from Flash IDD Note 3 VDD 3 6 V F 25 MHz 9 4 10 2 mA VDD 3 0 V F 25 MHz 6 6 7 2 mA VDD 3 0 V F 1 MHz 0 45 mA VDD 3 0 V F 80 kHz 36 µA IDD Supply Sensitivity Note 3 F 25 MHz 69 V F 1 MHz 51 V IDD Frequency Sensitivity Note 3 Note 4 VDD 3 0 V F 15 MHz T 25 C 0 45 mA MHz VDD 3 0 V F 15 MHz T 25 C 0 16 mA MHz VDD 3 6 V F 15 MHz T 25 C 0 69 mA ...

Page 26: ...ensitivity number for that range When using these numbers to estimate IDD for 15 MHz the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number For example VDD 3 0 V F 20 MHz IDD 6 6 mA 25 MHz 20 MHz x 0 16 mA MHz 5 8 mA 5 Idle IDD can be estimated for frequencies 1 MHz by simply multiplying the frequency of interest by the frequency ...

Page 27: ...or res onator this pin is the excitation driver This pin is the external clock input for CMOS capacitor or RC network configurations See Section 11 2 Port 0 3 See Section 12 for complete description P0 4 6 12 D I O or A In Port 0 4 See Section 12 for complete description P0 5 7 13 D I O or A In Port 0 5 See Section 12 for complete description C2CK RST 8 14 D I O D I O Clock signal for the C2 Devel...

Page 28: ...C8051F300 1 2 3 4 5 28 Rev 2 9 Figure 4 1 QFN 11 Pinout Diagram Top View VREF P0 0 P0 1 VDD XTAL1 P0 2 XTAL2 P0 3 P0 4 P0 5 C2CK RST P0 6 CNVSTR C2D P0 7 GND ...

Page 29: ...a 0 15 D 3 00 BSC bbb 0 15 D2 1 30 1 35 1 40 ddd 0 05 e 0 50 BSC eee 0 08 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC outline MO 243 variation VEED except for custom features D2 E2 and L which are toleranced per supplier designation 4 Recommended card reflow profile is per the JEDEC I...

Page 30: ... 1 2 3 4 5 30 Rev 2 9 Figure 4 3 Typical QFN 11 Solder Paste Mask 0 50 mm LT e E D e LB k D2 b L D4 0 10 mm 0 50 mm 0 35 mm 0 30 mm 0 10 mm 0 20 mm 0 30 mm 0 20 mm 0 60 mm 0 70 mm D4 b 0 30 mm 0 35 mm E2 0 20 mm ...

Page 31: ... between the solder mask and the metal pad is to be 60 µm minimum all the way around the pad Notes Stencil Design 1 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pads 4 A 3 x 1 array o...

Page 32: ...C8051F300 1 2 3 4 5 32 Rev 2 9 Figure 4 5 SOIC 14 Pinout Diagram Top View 2 1 4 3 5 6 7 13 14 11 12 10 9 8 TOP VIEW C2D P0 7 P0 6 GND N C P0 0 P0 1 VDD P0 3 P0 5 C2CK RST P0 4 N C N C P0 2 ...

Page 33: ...SC b 0 33 0 51 Q 0 8 c 0 17 0 25 aaa 0 10 D 8 65 BSC bbb 0 20 E 6 00 BSC ccc 0 10 E1 3 90 BSC ddd 0 25 e 1 27 BSC Notes 1 All dimensions shown are in millimeters mm 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC outline MS012 variation AB 4 Recommended card reflow profile is per the JEDEC IPC J STD 020C specification for Small Body Components ...

Page 34: ...C8051F300 1 2 3 4 5 34 Rev 2 9 Figure 4 7 SOIC 14 PCB Land Pattern Table 4 5 SOIC 14 PCB Land Pattern Dimensions Dimension Min Max C1 5 30 5 40 E 1 27 BSC X1 0 50 0 60 Y1 1 45 1 55 ...

Page 35: ...onfigured to measure any Port pin the Temperature Sensor output or VDD with respect to any Port pin or GND The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register ADC0CN is set to logic 1 The ADC0 sub system is in low power shutdown when this bit is logic 0 Figure 5 1 ADC0 Functional Block Diagram AMUX0 X VDD ADC0CF AMP0GN0 AMP0GN1 AD0SC0 AD0SC1 AD0SC2 AD0SC3 AD0SC4 8 Bi...

Page 36: ...27 128 Example codes are shown below Important Note About ADC0 Input Configuration Port pins selected as ADC0 inputs should be config ured as analog inputs and should be skipped by the Digital Crossbar To configure a Port pin for analog input set to 0 the corresponding bit in register P0MDIN To force the Crossbar to skip a Port pin set to 1 the corresponding bit in register XBR0 See Section 12 Por...

Page 37: ...n Step 2 Power the device and delay for a few seconds to allow for self heating Step 3 Perform an ADC conversion with the temperature sensor selected as the positive input and GND selected as the negative input Step 4 Calculate the offset and or gain characteristics and store these values in non volatile memory for use with subsequent temperature sensor measurements Figure 5 3 shows the typical te...

Page 38: ...perature Sensor Error with 1 Point Calibration VREF 2 40 V 40 00 20 00 0 00 20 00 40 00 60 00 80 00 Temperature degrees C Error degrees C 5 00 4 00 3 00 2 00 1 00 0 00 1 00 2 00 3 00 4 00 5 00 5 00 4 00 3 00 2 00 1 00 0 00 1 00 2 00 3 00 4 00 5 00 ...

Page 39: ...and During conversion the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete The falling edge of AD0BUSY triggers an interrupt when enabled and sets the ADC0 interrupt flag AD0INT Note When polling for ADC conversion completions the ADC0 interrupt flag AD0INT should be used Converted data is available in the ADC0 data register ADC0 when bit AD0INT is logic 1 Note th...

Page 40: ...s on the rising edge of CNVSTR see Figure 5 4 Tracking can also be disabled shutdown when the device is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX or PGA settings are frequently changed due to the settling time requirements described in Section 5 3 3 Settling Time Requirements on page 41 Figure 5 4 8 Bit ADC Track and Conversion Example Timing Write ...

Page 41: ...nt time constant for both input circuits is the same The required ADC0 settling time for a given settling accuracy SA may be approximated by Equation 5 1 When measuring the Temperature Sensor output or VDD with respect to GND RTOTAL reduces to RMUX See Table 5 1 for ADC0 minimum settling time track hold time requirements Equation 5 1 ADC0 Settling Time Requirements Where SA is the settling accurac...

Page 42: ...AMX0P3 0 AMUX0 Positive Input Selection 0000 1001b ADC0 Positive Input selected per the chart below 1010 1111b RESERVED R W R W R W R W R W R W R W R W Reset Value AMX0N3 AMX0N2 AMX0N1 AMX0N0 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xBB AMX0N3 0 ADC0 Negative Input 0000 P0 0 0001 P0 1 0010 P0 2 0011 P0 3 0100 P0 4 0101 P0 5 0110 P0 6 0111 P0 7 1xxx ...

Page 43: ...n t care Bits1 0 AMP0GN1 0 ADC0 Internal Amplifier Gain PGA 00 Gain 0 5 01 Gain 1 10 Gain 2 11 Gain 4 R W R W R W R W R W R W R W R W Reset Value AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AMP0GN1 AMP0GN0 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xBC AD0SC SYSCLK CLKSAR 1 Bits7 0 ADC0 Data Word ADC0 holds the output data byte from the last ADC0 conversion When in Single ended mode ADC0...

Page 44: ...arison Data match has occurred Bits2 0 AD0CM2 0 ADC0 Start of Conversion Mode Select When AD0TM 0 000 ADC0 conversion initiated on every write of 1 to AD0BUSY 001 ADC0 conversion initiated on overflow of Timer 0 010 ADC0 conversion initiated on overflow of Timer 2 011 ADC0 conversion initiated on overflow of Timer 1 1xx ADC0 conversion initiated on rising edge of external CNVSTR When AD0TM 1 000 T...

Page 45: ...e contents of the ADC0LT and ADC0GT registers 5 4 1 Window Detector In Single Ended Mode Figure 5 6 shows two example window comparisons for Single ended mode with ADC0LT 0x20 and ADC0GT 0x10 Notice that in Single ended mode the codes vary from 0 to VREF x 255 256 and are represented as 8 bit unsigned integers In the left example an AD0WINT interrupt will be generated if the ADC0 conversion word A...

Page 46: ...ow Compare Examples Differential Mode SFR Definition 5 5 ADC0GT ADC0 Greater Than Data Byte C8051F300 2 SFR Definition 5 6 ADC0LT ADC0 Less Than Data Byte C8051F300 2 0x7F 127d 0x11 17d 0x10 16d 0x0F 15d 0x00 0d 0xFF 1d 0xFE 2d 0x80 128d REF Input Voltage P0 x P0 y REF x 127 128 REF x 16 128 REF x 1 256 0x7F 127d 0x11 17d 0x10 16d 0x0F 15d 0x00 0d 0xFF 1d 0xFE 2d 0x80 128d REF Input Voltage P0 x P...

Page 47: ...oise Plus Distortion 45 48 dB Total Harmonic Distortion Up to the 5th harmonic 56 dB Spurious Free Dynamic Range 58 dB Conversion Rate SAR Conversion Clock 6 MHz Conversion Time in SAR Clocks 11 clocks Track Hold Acquisition Time 300 ns Throughput Rate 500 ksps Analog Inputs Input Voltage Range 0 VREF V Input Capacitance 5 pF Temperature Sensor Linearity1 2 3 0 5 C Gain1 2 3 3350 110 µV C Offset1 ...

Page 48: ...C8051F300 1 2 3 4 5 48 Rev 2 9 NOTES ...

Page 49: ...d as the external VREF input When using an external voltage reference P0 0 should be configured as analog input and skipped by the Digital Crossbar To configure P0 0 as analog input set to 1 Bit0 in register P0MDIN To configure the Crossbar to skip P0 0 set to 1 Bit0 in register XBR0 Refer to Section 12 Port Input Output on page 103 for complete Port I O configuration details The external referenc...

Page 50: ...EFSL Voltage Reference Select This bit selects the source for the internal voltage reference 0 VREF input pin used as voltage reference 1 VDD used as voltage reference Bit2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor off 1 Internal Temperature Sensor on Bit1 BIASE Internal Analog Bias Generator Enable Bit Must be 1 if using ADC 0 Internal Bias Generator off 1 Internal Bias Ge...

Page 51: ...e see Section 9 5 Comparator0 Reset on page 85 The inputs for Comparator0 are selected in the CPT0MX register SFR Definition 7 2 The CMX0P1 CMX 0P0 bits select the Comparator0 positive input the CMX0N1 CMX0N0 bits select the Comparator0 nega tive input Important Note About Comparator Inputs The Port pins selected as comparator inputs should be con figured as analog inputs in their associated Port ...

Page 52: ...unt of power con sumed by Comparator0 See Table 7 1 for complete timing and power consumption specifications Figure 7 2 Comparator Hysteresis Plot The hysteresis of Comparator0 is software programmable via its Comparator0 Control register CPT0CN The user can program both the amount of hysteresis voltage referred to the input voltage and the positive and negative going symmetry of this hysteresis a...

Page 53: ...put State Flag 0 Voltage on CP0 CP0 1 Voltage on CP0 CP0 Bit5 CP0RIF Comparator0 Rising Edge Interrupt Flag 0 No Comparator0 Rising Edge Interrupt has occurred since this flag was last cleared 1 Comparator0 Rising Edge Interrupt has occurred Bit4 CP0FIF Comparator0 Falling Edge Interrupt Flag 0 No Comparator0 Falling Edge Interrupt has occurred since this flag was last cleared 1 Comparator0 Fallin...

Page 54: ...rator0 positive input R W R W R W R W R W R W R W R W Reset Value CMX0N1 CMX0N0 CMX0P1 CMX0P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x9F CMX0N1 CMX0N0 Negative Input 0 0 P0 1 0 1 P0 3 1 0 P0 5 1 1 P0 7 CMX0P1 CMX0P0 Positive Input 0 0 P0 0 0 1 P0 2 1 0 P0 4 1 1 P0 6 Bits7 2 UNUSED Read 000000b Write don t care Bits1 0 CP0MD1 CP0MD0 Comparator0 Mode Select These bits select t...

Page 55: ... mV V Positive Hysteresis 1 CP0HYP1 0 00 0 1 mV Positive Hysteresis 2 CP0HYP1 0 01 3 5 7 mV Positive Hysteresis 3 CP0HYP1 0 10 7 10 15 mV Positive Hysteresis 4 CP0HYP1 0 11 15 20 25 mV Negative Hysteresis 1 CP0HYN1 0 00 0 1 mV Negative Hysteresis 2 CP0HYN1 0 01 3 5 7 mV Negative Hysteresis 3 CP0HYN1 0 10 7 10 15 mV Negative Hysteresis 4 CP0HYN1 0 11 15 20 25 mV Inverting or Non Inverting Input Vol...

Page 56: ...C8051F300 1 2 3 4 5 56 Rev 2 9 NOTES ...

Page 57: ... The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability see Figure 8 1 for a block diagram The CIP 51 includes the following features Figure 8 1 CIP 51 Block Diagram Fully Compatible with MCS 51 Instruction Set Extended Interrupt Handler 25 MIPS Peak Throughput with 25 MHz Clock Reset...

Page 58: ...ebugging is completely non intrusive requiring no RAM Stack timers or other on chip resources C2 details can be found in Section 17 C2 Interface on page 173 The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs pro vides an integrated development environment IDE including editor macro assembler debugger and pro grammer The IDE s debugger and programmer...

Page 59: ...dd direct byte to A 2 2 ADD A Ri Add indirect RAM to A 1 2 ADD A data Add immediate to A 2 2 ADDC A Rn Add register to A with carry 1 1 ADDC A direct Add direct byte to A with carry 2 2 ADDC A Ri Add indirect RAM to A with carry 1 2 ADDC A data Add immediate to A with carry 2 2 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 2 SUBB A Ri Su...

Page 60: ...te A right 1 1 RRC A Rotate A right through Carry 1 1 SWAP A Swap nibbles of A 1 1 Data Transfer MOV A Rn Move Register to A 1 1 MOV A direct Move direct byte to A 2 2 MOV A Ri Move indirect RAM to A 1 2 MOV A data Move immediate to A 2 2 MOV Rn A Move A to Register 1 1 MOV Rn direct Move direct byte to Register 2 2 MOV Rn data Move immediate to Register 2 2 MOV direct A Move A to direct byte 2 2 ...

Page 61: ...ent direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 ANL C bit AND complement of direct bit to Carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to Carry 2 2 MOV C bit Move direct bit to Carry 2 2 MOV bit C Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2 3 JNC rel Jump if Carry is not set 2 2 3 JB bit rel Jump if direct bit is set 3 3 4 JNB bit r...

Page 62: ...f the currently selected register bank Ri Data RAM location addressed indirectly through R0 or R1 rel 8 bit signed two s complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant...

Page 63: ...rage The C8051F304 implements 4096 bytes of reprogrammable Flash program memory space the C8051F305 implements 2048 bytes of reprogramma ble Flash program memory space Figure 8 2 shows the program memory maps for C8051F300 1 2 3 4 5 devices Figure 8 2 Program Memory Maps Program memory is normally assumed to be read only However the CIP 51 can write to program memory by setting the Program Store W...

Page 64: ...upper 128 bytes of data memory space or the SFRs Instructions that use direct addressing will access the SFR space Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory Figure 8 3 illustrates the data memory organization of the CIP 51 Figure 8 3 Data Memory Map 8 2 3 General Purpose Registers The lower 32 bytes of data memory locations 0x00 through 0x1F may be...

Page 65: ...efore the first value pushed on the stack is placed at location 0x08 which is also the first register R0 of register bank 1 Thus if more than one register bank is to be used the SP should be initialized to a location in the data memory not being used for data storage The stack depth can extend up to 256 bytes 8 2 6 Special Function Registers The direct access data memory locations from 0x80 to 0xF...

Page 66: ...bit addressable Table 8 3 Special Function Registers Register Address Description Page No ACC 0xE0 Accumulator 71 ADC0CF 0xBC ADC0 Configuration 43 ADC0CN 0xE8 ADC0 Control 44 ADC0GT 0xC4 ADC0 Greater Than Compare Word 46 ADC0LT 0xC6 ADC0 Less Than Compare Word 46 ADC0 0xBE ADC0 Data Word 43 AMX0SL 0xBB ADC0 Multiplexer Channel Select 42 B 0xF0 B Register 71 CKCON 0x8E Clock Control 149 CPT0CN 0xF...

Page 67: ... PCA Capture 2 Low 171 PCA0CPM0 0xDA PCA Module 0 Mode Register 169 PCA0CPM1 0xDB PCA Module 1 Mode Register 169 PCA0CPM2 0xDC PCA Module 2 Mode Register 169 PCA0H 0xFA PCA Counter High 170 PCA0L 0xF9 PCA Counter Low 170 PCON 0x87 Power Control 81 PSCTL 0x8F Program Store R W Control 92 PSW 0xD0 Program Status Word 70 REF0CN 0xD1 Voltage Reference Control 49 RSTSRC 0xEF Reset Source Configuration ...

Page 68: ...1 Low 150 TMOD 0x89 Timer Counter Mode 148 TMR2RLH 0xCB Timer Counter 2 Reload High 154 TMR2RLL 0xCA Timer Counter 2 Reload Low 154 TMR2H 0xCD Timer Counter 2 High 154 TMR2L 0xCC Timer Counter 2 Low 154 XBR0 0xE1 Port I O Crossbar Control 0 107 XBR1 0xE2 Port I O Crossbar Control 1 107 XBR2 0xE3 Port I O Crossbar Control 2 108 0x97 0xAE 0xAF 0xB4 0xB6 0xBF 0xCE 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xDD 0...

Page 69: ...ddressed Flash memory R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x83 Bits7 0 SP Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incremented before every PUSH operation The SP register defaults to 0x07 after reset R W R W R W R W R W R W R W R W Reset Value 00000111 Bit7 Bit6 Bit5 Bit4 Bit...

Page 70: ...sed during register accesses Bit2 OV Overflow Flag This bit is set to 1 under the following circumstances An ADD ADDC or SUBB instruction causes a sign change overflow A MUL instruction results in an overflow result is greater than 255 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases Bit1 F1 User Flag 1 ...

Page 71: ...R W R W Reset Value ACC 7 ACC 6 ACC 5 ACC 4 ACC 3 ACC 2 ACC 1 ACC 0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address bit addressable 0xE0 Bits7 0 B B Register This register serves as a second accumulator for certain arithmetic operations R W R W R W R W R W R W R W R W Reset Value B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address bit addressab...

Page 72: ...interrupt enable settings Note Any instruction that clears the EA bit should be immediately followed by an instruction that has two or more opcode bytes For example in C EA 0 clear EA bit EA 0 followed by another 2 byte opcode in assembly CLR EA clear EA bit CLR EA followed by another 2 byte opcode If an interrupt is posted during the execution phase of a CLR EA opcode or any instruction which cle...

Page 73: ...rce can be individually programmed to one of two priority levels low or high A low prior ity interrupt service routine can be preempted by a high priority interrupt A high priority interrupt cannot be preempted Each interrupt has an associated interrupt priority bit in an SFR IP or EIP1 used to configure its priority level Low priority is the default If two interrupts are recognized simultaneously...

Page 74: ...01B 3 TF1 TCON 7 Y Y ET1 IE 3 PT1 IP 3 UART0 0x0023 4 RI0 SCON0 0 TI0 SCON0 1 Y N ES0 IE 4 PS0 IP 4 Timer 2 Overflow 0x002B 5 TF2H TMR2CN 7 TF2L TMR2CN 6 Y N ET2 IE 5 PT2 IP 5 SMBus Interface 0x0033 6 SI SMB0CN 0 Y N ESMB0 EIE1 0 PSMB0 EIP1 0 ADC0 Window Compare 0x003B 7 AD0WINT ADC0CN 3 Y N EWADC0 EIE1 1 PWADC0 EIP1 1 ADC0 Conversion Com plete 0x0043 8 AD0INT ADC0CN 5 Y N EADC0C EIE1 2 PADC0C EIP...

Page 75: ...1 Enable interrupt requests generated by the TF2L or TF2H flags Bit4 ES0 Enable UART0 Interrupt This bit sets the masking of the UART0 interrupt 0 Disable UART0 interrupt 1 Enable UART0 interrupt Bit3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable all Timer 1 interrupt 1 Enable interrupt requests generated by the TF1 flag Bit2 EX1 Enable External Interrup...

Page 76: ...rity level 1 Timer 1 interrupts set to high priority level Bit2 PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority level 1 External Interrupt 1 set to high priority level Bit1 PT0 Timer 0 Interrupt Priority Control This bit sets the priority of the Timer 0 interrupt 0 Timer 0 interrupts set to low pr...

Page 77: ...errupts 0 Disable all PCA0 interrupts 1 Enable interrupt requests generated by PCA0 Bit2 EADC0C Enable ADC0 Conversion Complete Interrupt This bit sets the masking of the ADC0 Conversion Complete interrupt 0 Disable ADC0 Conversion Complete interrupt 1 Enable interrupt requests generated by the AD0INT flag Bit1 EWADC0 Enable Window Comparison ADC0 Interrupt This bit sets the masking of ADC0 Window...

Page 78: ...PCA0 interrupt set to low priority level 1 PCA0 interrupt set to high priority level Bit2 PADC0C ADC0 Conversion Complete Interrupt Priority Control This bit sets the priority of the ADC0 Conversion Complete interrupt 0 ADC0 Conversion Complete interrupt set to low priority level 1 ADC0 Conversion Complete interrupt set to high priority level Bit1 PWADC0 ADC0 Window Comparator Interrupt Priority C...

Page 79: ...igh Bits2 0 INT0SL2 0 INT0 Port Pin Selection Bits These bits select which Port pin is assigned to INT0 Note that this pin assignment is inde pendent of the Crossbar INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin acco...

Page 80: ...errupt is asserted or a reset occurs The assertion of an enabled interrupt will cause the Idle Mode Selection bit PCON 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Idle mode is terminated by...

Page 81: ...ernal reset and thereby terminate the Stop mode The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 µsec SFR Definition 8 12 PCON Power Control Bits7 2 GF5 GF0 General Purpose Flags 5 0 These are general purpose flags for use under software control Bit1 STOP Stop Mode Select Setting this bit will place the CIP 51 in Stop mode...

Page 82: ...C8051F300 1 2 3 4 5 82 Rev 2 9 NOTES ...

Page 83: ...ing and after the reset For VDD Monitor and power on resets the RST pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator Refer to Section 11 Oscillators on page 97 for information on selecting and configuring the system clock source The Watchdog Timer is enabled with the syste...

Page 84: ...nt of internal data mem ory should be assumed to be undefined after a power on reset The VDD monitor is disabled following a power on reset Figure 9 2 Power On and VDD Monitor Reset Timing 9 2 Power Fail Reset VDD Monitor When a power down transition or power irregularity causes VDD to drop below VRST the power supply monitor will drive the RST pin low and hold the CIP 51 in a reset state see Figu...

Page 85: ... the MCD as the reset source otherwise this bit reads 0 Writing a 1 to the MCDRSF bit enables the Missing Clock Detector writing a 0 disables it The state of the RST pin is unaffected by this reset 9 5 Comparator0 Reset Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag RSTSRC 5 Com parator0 should be enabled and allowed to settle prior to writing to C0RSEF to preven...

Page 86: ... Software Reset Software may force a reset by writing a 1 to the SWRSF bit RSTSRC 4 The SWRSF bit will read 1 fol lowing a software forced reset The state of the RST pin is unaffected by this reset Table 9 1 User Code Space Address Limits Device User Code Space Address Limit C8051F300 1 2 3 0x1DFF C8051F304 0x0FFF C8051F305 0x07FF Table 9 2 Reset Electrical Characteristics 40 to 85 C unless otherw...

Page 87: ...s a WDT timeout Bit2 MCDRSF Missing Clock Detector Flag Write 0 Missing Clock Detector disabled 1 Missing Clock Detector enabled triggers a reset if a missing clock condition is detected Read 0 Source of last reset was not a Missing Clock Detector timeout 1 Source of last reset was a Missing Clock Detector timeout Bit1 PORSF Power On Reset Force and Flag This bit is set anytime a power on reset oc...

Page 88: ...C8051F300 1 2 3 4 5 88 Rev 2 9 NOTES ...

Page 89: ...tim ing does not matter but the codes must be written in order If the key codes are written out of order or the wrong codes are written Flash writes and erases will be disabled until the next system reset Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been writ ten properly The Flash lock resets after each write or erase the key codes...

Page 90: ...protect the Flash memory from inadvertent modification by soft ware as well as to prevent the viewing of proprietary program code and constants The Program Store Write Enable bit PSWE in register PSCTL and the Program Store Erase Enable bit PSEE in register PSCTL bits protect the Flash memory from accidental modification by software PSWE must be explicitly set to 1 before software can modify the F...

Page 91: ...he Lock Byte is always permitted only if no pages are locked 5 Locking additional pages changing 1 s to 0 s in the Lock Byte is not permitted 6 Unlocking Flash pages changing 0 s to 1 s in the Lock Byte requires the C2 Device Erase com mand which erases all Flash pages including the page containing the Lock Byte and the Lock Byte itself 7 The Reserved Area cannot be read written or erased Table 10...

Page 92: ...only be read or written An erase attempt on the page containing the Lock Byte will result in a Flash Error device reset 4 Reading the contents of the Lock Byte is always permitted 5 Locking additional pages changing 1 s to 0 s in the Lock Byte is not permitted 6 Unlocking Flash pages changing 0 s to 1 s in the Lock Byte is not permitted 7 The Reserved Area cannot be read written or erased Any atte...

Page 93: ...have been written correctly Read When read bits 1 0 indicate the current Flash lock state 00 Flash is write erase locked 01 The first key code has been written 0xA5 10 Flash is unlocked writes erases allowed 11 Flash writes erases disabled until the next reset R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xB7 Bits7 FOSE Flash One shot Ena...

Page 94: ...g the VDD monitor and enabling the VDD monitor as a reset source Code examples showing this can be found in AN201 Writing to Flash from Firmware available from the Silicon Laboratories web site 4 As an added precaution explicitly enable the VDD monitor and enable the VDD monitor as a reset source inside the functions that write and erase Flash memory The VDD monitor enable instructions should be p...

Page 95: ... Flash 10 4 3 System Clock 12 If operating from an external crystal be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature If the system is operating in an electrically noisy environment use the internal oscillator or use an external CMOS clock 13 If operating from the external oscillator switch to the internal oscilla...

Page 96: ...C8051F300 1 2 3 4 5 96 Rev 2 9 NOTES ...

Page 97: ...The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 11 1 On C8051F300 1 devices OSCICL is factory calibrated to obtain a 24 5 MHz frequency On C8051F302 3 4 5 devices the oscillator frequency is a nominal 20 MHz and may vary 20 from device to device Electrical specifications for the precision internal oscillator are given in Table 11 1 on page 99 The...

Page 98: ...ernal Oscillator Frequency Ready Flag 0 Internal Oscillator is not running at programmed frequency 1 Internal Oscillator is running at programmed frequency Bit3 CLKSL System Clock Source Select Bit 0 SYSCLK derived from the Internal Oscillator and scaled as per the IFCN bits 1 SYSCLK derived from the External Oscillator circuit Bit2 IOSCEN Internal Oscillator Enable Bit 0 Internal Oscillator Disab...

Page 99: ...figured as analog inputs In CMOS clock mode the associated pin should be configured as a digital input See Section 12 2 Port I O Initialization on page 106 for details on Port input mode selection 11 3 System Clock Selection The CLKSL bit in register OSCICN selects which oscillator is used as the system clock CLKSL must be set to 1 for the system clock to run from the external oscillator however t...

Page 100: ...uit from Figure 11 1 Option 2 XOSCMD 10x Choose XFCN value to match frequency range f 1 23 103 R x C where f frequency of oscillation in MHz C capacitor value in pF R Pull up resistor value in kΩ C MODE Circuit from Figure 11 1 Option 3 XOSCMD 10x Choose K Factor KF for the oscillation frequency desired f KF C x VDD where f frequency of oscillation in MHz C capacitor value the XTAL2 pin in pF VDD ...

Page 101: ...XTAL1 and XTAL2 as analog inputs Step 3 Enable the external oscillator Step 4 Wait at least 1 ms Step 5 Poll for XTLVLD 1 Step 6 Switch the system clock to the external oscillator Note Tuning fork crystals may require additional settling time before XTLVLD returns a valid result The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for corr...

Page 102: ...efinition 11 3 the required XFCN setting is 010b 11 6 External Capacitor Example If a capacitor is used as an external oscillator for the MCU the circuit should be configured as shown in Figure 11 1 Option 3 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To determine the required Ext...

Page 103: ...n the Priority Decoder Figure 12 3 and Figure 12 4 The registers XBR0 XBR1 and XBR2 defined in SFR Definition 12 1 SFR Definition 12 2 and SFR Definition 12 3 are used to select internal digital functions All Port I Os are 5 V tolerant refer to Figure 12 2 for the Port cell circuit The Port I O cells are configured as either push pull or open drain in the Port0 Output Mode register P0MDOUT Complet...

Page 104: ... to P0 0 if VREF is enabled P0 3 and or P0 2 if the external oscillator circuit is enabled P0 6 if the ADC is configured to use the external conversion start signal CNVSTR and any selected ADC or Comparator inputs The Crossbar skips selected pins as if they were already assigned and moves to the next unassigned pin Figure 12 3 shows the Crossbar Decoder priority with no Port pins skipped XBR0 0x00...

Page 105: ...always assigned to P0 5 Standard Port I Os appear contiguously after the prioritized functions have been assigned For example if assigned functions that take the first 3 Port I O P0 2 0 5 Port I O are left for analog or GPIO use VREF x1 x2 CNVSTR 0 1 2 3 4 5 6 7 0 0 1 0 0 0 1 0 Port pin potentially available to peripheral Port pin skipped by CrossBar ECI Signals Unavailable CEX0 CEX1 Special Funct...

Page 106: ...efault to digital inputs on reset See SFR Defini tion 12 5 for the P0MDIN register details The output driver characteristics of the I O pins are defined using the Port0 Output Mode register P0MD OUT see SFR Definition 12 6 Each Port Output driver can be configured as either open drain or push pull This selection is required even for the digital resources selected in the XBRn registers and is not a...

Page 107: ...le I 0 Enable Bits 00 All PCA I O unavailable at Port pins 01 CEX0 routed to Port pin 10 CEX0 CEX1 routed to Port pins 11 CEX0 CEX1 CEX2 routed to Port pins Bit5 CP0AOEN Comparator0 Asynchronous Output Enable 0 Asynchronous CP0 unavailable at Port pin 1 Asynchronous CP0 routed to Port pin Bit4 CP0OEN Comparator0 Output Enable 0 CP0 unavailable at Port pin 1 CP0 routed to Port pin Bit3 SYSCKE SYSCL...

Page 108: ...ead modify write instructions The read modify write instructions when operating on a Port SFR are the following ANL ORL XRL JBC CPL INC DEC DJNZ and MOV CLR or SET when the destination is an individual bit in a Port SFR For these instructions the value of the register not the pin is read modified and written back to the SFR Bit7 WEAKPUD Port I O Weak Pull up Disable 0 Weak Pull ups enabled except ...

Page 109: ...P0 n pin is logic low 1 P0 n pin is logic high R W R W R W R W R W R W R W R W Reset Value P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address bit addressable 0x80 Bits7 0 Input Configuration Bits for P0 7 P0 0 respectively Port pins configured as analog inputs have their weak pull up digital driver and digital receiver disabled 0 Corresponding P0 n...

Page 110: ...5 mA IOL 10 µA IOL 25 mA 1 0 0 6 0 1 V Input High Voltage 2 0 V Input Low Voltage 0 8 V Input Leakage Current Weak Pull up Off Weak Pull up On VIN 0 V 25 1 40 µA Bits7 0 Output Configuration Bits for P0 7 P0 0 respectively ignored if corresponding bit in regis ter P0MDIN is logic 0 0 Corresponding P0 n Output is open drain 1 Corresponding P0 n Output is push pull Note When SDA and SCL appear on an...

Page 111: ...master and or slave and may function on a bus with multiple mas ters The SMBus provides control of SDA serial data SCL serial clock generation and synchronization arbitration logic and START STOP control and generation Three SFRs are associated with the SMBus SMB0CF configures the SMBus SMB0CN controls the status of the SMBus and SMB0DAT is the data register used for both transmitting and receivin...

Page 112: ...Configuration 13 3 SMBus Operation Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave and multi...

Page 113: ...us Figure 13 3 illustrates a typical SMBus transaction Figure 13 3 SMBus Transaction 13 3 1 Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see Section 13 3 4 SCL High SMBus Free Timeout on page 114 In the event that two or more devices attempt to begin a transfer at the same ti...

Page 114: ...he timeout condition must reset the communi cation no later than 10 ms after detecting the timeout condition When the SMBTOE bit in SMB0CF is set Timer 2 is used to detect SCL low timeouts Timer 2 is forced to reload when SCL is high and allowed to count when SCL is low With Timer 2 enabled and configured to overflow after 25 ms and SMBTOE set the Timer 2 interrupt service routine can be used to r...

Page 115: ... that software may read the received ACK value when receiving data this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value See Section 13 5 SMBus Transfer Modes on page 123 for more details on transmission sequences Interrupts are also generated to indicate the beginning of a transfer when a master START generated or the end of a transfer when a slave ST...

Page 116: ... be shared by other peripherals so long as the timer is left running at all times For example Timer 1 overflows may generate the SMBus and UART baud rates simultaneously Timer configuration is covered in Section 15 Timers on page 143 Equation 13 1 Minimum SCL High and Low Times The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 13 1 When ...

Page 117: ...eload while SCL is high and allow Timer 2 to count when SCL is low The Timer 2 interrupt service rou tine should be used to reset SMBus communication by disabling and reenabling the SMBus Timer 2 con figuration is described in Section 15 2 Timer 2 on page 151 SMBus Free Timeout detection can be enabled by setting the SMBFTE bit When this bit is set the bus will be considered free if SDA and SCL re...

Page 118: ...TOE SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 2 to reload while SCL is high and allows Timer 2 to count when SCL goes low If Timer 2 is con figured in split mode T2SPLIT is set only the high byte of Timer 2 is held in reload while SCL is high Timer 2 should be programmed to generate interrupts at 25 ms and the Timer 2 int...

Page 119: ...generated As a receiver writing the ACK bit defines the outgoing ACK value as a transmitter reading the ACK bit indicates the value received on the last ACK cycle ACKRQ is set each time a byte is received indicating that an outgoing ACK value is needed When ACKRQ is set software should write the desired outgoing value to the ACK bit before clearing SI A NACK will be generated if software does not ...

Page 120: ... Trans mitter mode See Section 13 5 4 for details Read 0 No Stop condition detected 1 Stop condition detected if in Slave Mode or pending if in Master Mode Bit3 ACKRQ SMBus Acknowledge Request This read only bit is set to logic 1 when the SMBus has received a byte and needs the ACK bit to be written with the correct ACK response value Bit2 ARBLOST SMBus Arbitration Lost Indicator This read only bi...

Page 121: ...rbitration is lost due to a detected STOP A pending STOP is generated ACKRQ A byte has been received and an ACK response value is needed After each ACK cycle ARBLOST A repeated START is detected as a MASTER when STA is low unwanted repeated START SCL is sensed low while attempting to gener ate a STOP or repeated START condition SDA is sensed low while transmitting a 1 excluding ACK bits Each time ...

Page 122: ...fted in SMB0DAT always contains the last data byte present on the bus In the event of lost arbi tration the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT SFR Definition 13 3 SMB0DAT SMBus Data Bits7 0 SMB0DAT SMBus Data The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial inter face or a byte that has just bee...

Page 123: ...rates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 0 WRITE The master then transmits one or more bytes of serial data After each byte is transmitted an acknowledge bit is generated by the slave The transfer is ended when the STO bit is set and a STOP is generated Note tha...

Page 124: ...ge value Note writing a 1 to the ACK bit gen erates an ACK writing a 0 generates a NACK Software should write a 0 to the ACK bit after the last byte is received to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver Figure 13 6 s...

Page 125: ...ddress is acknowledged zero or more data bytes are received Software must write the ACK bit after each received byte to ACK or NACK the received byte The interface exits Slave Receiver Mode after receiving a STOP Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver see Section 13 5 4 for details on this procedure Figure 13 7 shows a typ...

Page 126: ...l for TXMODE 1 Step 7 Clear STO to 0 must be done before the next ACK cycle The interface enters Slave Transmitter Mode and transmits one or more bytes of data the above steps are only required before the first byte of the transfer After each byte is transmitted the master sends an acknowledge bit if the acknowledge bit is an ACK SMB0DAT should be written with the next data byte If the acknowledge...

Page 127: ...Table 13 4 SMBus Status Decoding Mode Values Read Current SMbus State Typical Response Options Values Written Status Vector ACKRQ ARBLOST ACK STA STO ACK Master Transmitter 1110 0 0 X A master START was generated Load slave address R W into SMB0DAT 0 0 X 1100 0 0 0 A master data or address byte was transmitted NACK received Set STA to restart transfer 1 0 X Abort transfer 0 1 X 0 0 1 A master data...

Page 128: ...witch to Master Transmitter Mode write to SMB0DAT before clearing SI 0 0 0 SLAVE TRANSMITTER 0100 0 0 0 A slave byte was transmitted NACK received No action required expect ing STOP condition 0 0 X 0 0 1 A slave byte was transmitted ACK received Load SMB0DAT with next data byte to transmit 0 0 X 0 1 X A Slave byte was transmitted error detected No action required expect ing Master to end transfer ...

Page 129: ... failed transfer do not acknowledge received address 1 0 0 0010 0 1 X Lost arbitration while attempting a repeated START Abort failed transfer 0 0 X Reschedule failed transfer 1 0 X 0001 1 1 X Lost arbitration while attempting a STOP No action required transfer complete aborted 0 0 0 0 0 X A STOP was detected while addressed as a Slave Transmitter or Slave Receiver Clear STO 0 0 X 0 1 X Lost arbit...

Page 130: ...C8051F300 1 2 3 4 5 130 Rev 2 9 NOTES ...

Page 131: ...r writing SBUF0 accesses the Transmit register With UART0 interrupts enabled an interrupt is generated each time a transmit is completed TI0 is set in SCON0 or a data byte has been received RI0 is set in SCON0 The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause...

Page 132: ...n page 145 The Timer 1 reload value should be set so that over flows will occur at two times the desired UART baud rate frequency Note that Timer 1 may be clocked by one of five sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 or the external oscillator clock 8 For any given Timer 1 clock source the UART0 baud rate is determined by Equation 14 1 Equation 14 1 UART0 Baud Rate Where T1CLK is the frequenc...

Page 133: ... the stop bit time Data recep tion can begin any time after the REN0 Receive Enable bit SCON0 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if the following conditions are met RI0 must be logic 0 and if MCE0 is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latched into the...

Page 134: ...t the end of the transmission the beginning of the stop bit time Data reception can begin any time after the REN0 Receive Enable bit SCON0 4 is set to 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if the following conditions are met 1 RI0 must be logic 0 and 2 if MCE0 is logic 1 the 9th bit must be logic 1 when MCE0 is logic 0 the state of the ninth ...

Page 135: ... bit address If the addresses match the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE0 bit to ignore all transmissions u...

Page 136: ...e assigned to the ninth transmission bit in 9 bit UART Mode It is not used in 8 bit UART Mode Set or cleared by software as required Bit2 RB80 Ninth Receive Bit RB80 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 Bit1 TI0 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART0 after the 8th bit in 8 bit UART ...

Page 137: ...smit shift register and a receive latch register When data is written to SBUF0 it goes to the transmit shift register and is held for serial transmis sion Writing a byte to SBUF0 is what initiates the transmission A read of SBUF0 returns the contents of the receive latch R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x99 ...

Page 138: ...e found in Section 15 1 2 X Don t care Table 14 2 Timer Settings for Standard Baud Rates Using an External 25 MHz Oscillator Frequency 25 0 MHz Target Baud Rate bps Baud Rate Error Oscillator Divide Factor Timer Clock Source SCA1 SCA0 pre scale select 1 T1M1 Timer 1 Reload Value hex SYSCLK from External Osc 230400 0 47 108 SYSCLK XX2 1 0xCA 115200 0 45 218 SYSCLK XX2 1 0x93 57600 0 01 434 SYSCLK X...

Page 139: ... 00 192 SYSCLK XX2 1 0xA0 57600 0 00 384 SYSCLK XX2 1 0x40 28800 0 00 768 SYSCLK 12 00 0 0xE0 14400 0 00 1536 SYSCLK 12 00 0 0xC0 9600 0 00 2304 SYSCLK 12 00 0 0xA0 2400 0 00 9216 SYSCLK 48 10 0 0xA0 1200 0 00 18432 SYSCLK 48 10 0 0x40 SYSCLK from Internal Osc 230400 0 00 96 EXTCLK 8 11 0 0xFA 115200 0 00 192 EXTCLK 8 11 0 0xF4 57600 0 00 384 EXTCLK 8 11 0 0xE8 28800 0 00 768 EXTCLK 8 11 0 0xD0 14...

Page 140: ... 00 160 SYSCLK XX2 1 0xB0 57600 0 00 320 SYSCLK XX2 1 0x60 28800 0 00 640 SYSCLK 4 01 0 0xB0 14400 0 00 1280 SYSCLK 4 01 0 0x60 9600 0 00 1920 SYSCLK 12 00 0 0xB0 2400 0 00 7680 SYSCLK 48 10 0 0xB0 1200 0 00 15360 SYSCLK 48 10 0 0x60 SYSCLK from Internal Osc 230400 0 00 80 EXTCLK 8 11 0 0xFB 115200 0 00 160 EXTCLK 8 11 0 0xF6 57600 0 00 320 EXTCLK 8 11 0 0xEC 28800 0 00 640 EXTCLK 8 11 0 0xD8 1440...

Page 141: ...00 0 00 96 SYSCLK XX2 1 0xD0 57600 0 00 192 SYSCLK XX2 1 0xA0 28800 0 00 384 SYSCLK XX2 1 0x40 14400 0 00 768 SYSCLK 12 00 0 0xE0 9600 0 00 1152 SYSCLK 12 00 0 0xD0 2400 0 00 4608 SYSCLK 12 00 0 0x40 1200 0 00 9216 SYSCLK 48 10 0 0xA0 SYSCLK from Internal Osc 230400 0 00 48 EXTCLK 8 11 0 0xFD 115200 0 00 96 EXTCLK 8 11 0 0xFA 57600 0 00 192 EXTCLK 8 11 0 0xF4 28800 0 00 384 EXTCLK 8 11 0 0xE8 1440...

Page 142: ...15200 0 00 32 SYSCLK XX2 1 0xF0 57600 0 00 64 SYSCLK XX2 1 0xE0 28800 0 00 128 SYSCLK XX2 1 0xC0 14400 0 00 256 SYSCLK XX2 1 0x80 9600 0 00 384 SYSCLK XX2 1 0x40 2400 0 00 1536 SYSCLK 12 00 0 0xC0 1200 0 00 3072 SYSCLK 12 00 0 0x80 SYSCLK from Internal Osc 230400 0 00 16 EXTCLK 8 11 0 0xFF 115200 0 00 32 EXTCLK 8 11 0 0xFE 57600 0 00 64 EXTCLK 8 11 0 0xFC 28800 0 00 128 EXTCLK 8 11 0 0xF8 14400 0 ...

Page 143: ...erly sam pled 15 1 Timer 0 and Timer 1 Each timer is implemented as 16 bit register accessed as two separate bytes a low byte TL0 or TL1 and a high byte TH0 or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate their status Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register Section 8 3 5 Interrupt Register Descriptions on ...

Page 144: ...3 5 Interrupt Register Descriptions on page 75 facilitating pulse width measurements Setting TR0 does not force the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as described above for TL0 and TH0 Timer 1 is configured and controlled using the relevant TCON and TMOD ...

Page 145: ...hanged TL0 must be initialized to the desired value before enabling the timer for the first count to be correct When in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TR0 bit TCON 4 enables the timer when either GATE0 TMOD 3 is logic 0 or when the input signal INT0 is active as defined by bit IN0PL in...

Page 146: ...nactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode set ting...

Page 147: ...his flag is set to 1 when INT1 is active as defined by bit IN1PL in register IT01CF see SFR Definition 8 11 Bit2 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in the IT01CF register see SFR Definition 8 11 0 INT1 is level triggered 1 INT1 is edge triggered Bit1 IE0 External I...

Page 148: ...er 0 enabled only when TR0 1 AND INT0 is active as defined by bit IN0PL in regis ter IT01CF see SFR Definition 8 11 Bit2 C T0 Counter Timer Select 0 Timer Function Timer 0 incremented by clock defined by T0M bit CKCON 3 1 Counter Function Timer 0 incremented by high to low transitions on external input pin T0 Bits1 0 T0M1 T0M0 Timer 0 Mode Select These bits select the Timer 0 operation mode R W R ...

Page 149: ...ored when C T1 is set to logic 1 0 Timer 1 uses the clock defined by the prescale bits SCA1 SCA0 1 Timer 1 uses the system clock Bit3 T0M Timer 0 Clock Select This bit selects the clock source supplied to Timer 0 T0M is ignored when C T0 is set to logic 1 0 Counter Timer 0 uses the clock defined by the prescale bits SCA1 SCA0 1 Counter Timer 0 uses the system clock Bit2 UNUSED Read 0b Write don t ...

Page 150: ...8A Bits 7 0 TL1 Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8B Bits 7 0 TH0 Timer 0 High Byte The TH0 register is the high byte of the 16 bit Timer 0 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8C Bits ...

Page 151: ...rates as a 16 bit timer with auto reload Timer 2 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from 0xFFFF to 0x0000 the 16 bit value in the Timer 2 reload registers TMR2RLH and TMR2RLL is loaded into the Timer 2 register as shown in Figure 15 4 and the Timer 2 High Byte Overflow Flag TMR2CN ...

Page 152: ...tem clock to operate in this mode The TF2H bit is set when TMR2H overflows from 0xFF to 0x00 the TF2L bit is set when TMR2L overflows from 0xFF to 0x00 When Timer 2 interrupts are enabled IE 5 an interrupt is generated each time TMR2H overflows If Timer 2 interrupts are enabled and TF2LEN TMR2CN 5 is set an interrupt is gener ated each time either TMR2L or TMR2H overflows When TF2LEN is enabled so...

Page 153: ... 2 Low Byte interrupts disabled 1 Timer 2 Low Byte interrupts enabled Bit4 UNUSED Read 0b Write don t care Bit3 T2SPLIT Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with auto reload 0 Timer 2 operates in 16 bit auto reload mode 1 Timer 2 operates as two 8 bit auto reload timers Bit2 TR2 Timer 2 Run Control This bit enables disables Timer 2 In 8 bit mode this ...

Page 154: ...H holds the high byte of the reload value for Timer 2 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xCB Bits 7 0 TMR2L Timer 2 Low Byte In 16 bit mode the TMR2L register contains the low byte of the 16 bit Timer 2 In 8 bit mode TMR2L contains the 8 bit low byte timer value R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit...

Page 155: ...ured to operate independently in one of six modes Edge Triggered Capture Software Timer High Speed Output Fre quency Output 8 Bit PWM or 16 Bit PWM each mode is described in Section 16 2 Capture Compare Modules on page 157 The external oscillator clock option is ideal for real time clock RTC functionality allowing the PCA to be clocked by a precision external oscillator while the internal oscillat...

Page 156: ...A0MD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Note PCA0 interrupts must be globally enabled before CF interrupts are recognized PCA0 inter rupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1 Clearing the CIDL bit...

Page 157: ...abled by setting the EA bit and the EPCA0 bit to logic 1 See Figure 16 3 for details on the PCA interrupt configuration Figure 16 3 PCA Interrupt Block Diagram Table 16 2 PCA0CPM Register Settings for PCA Capture Compare Modules PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF Operation Mode X X 1 0 0 0 0 X Capture triggered by positive edge on CEXn X X 0 1 0 0 0 X Capture triggered by negative edge on CEXn ...

Page 158: ... and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software If both CAPPn and CAPNn bits are set to logic 1 then the state of the Port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused the capture ...

Page 159: ...leared by software Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 16 5 PCA Software Timer Mode Diagram Match 16 bit ...

Page 160: ... Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 16 6 PCA High Speed Output Mode Diagram Match 16 bit Comparator PCA0H PCA0CPHn Enable PCA0L PCA Timebase PCA0CPLn 0 1 0 0 0 x ENB ENB 0 1 Write to PCA0CPLn Write to PCA0CPHn Reset PC...

Page 161: ...e PCA mode register PCA0MD The lower byte of the capture compare module is compared to the PCA counter low byte on a match CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCA0CPMn reg ister Figure 16 7 PCA Frequency Output Mode FCEXn FPCA 2 PCA0CPHn 8 bit Comparator PCA0L ...

Page 162: ...A0CPHn without software intervention Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8 bit Pulse Width Modulator mode The duty cycle for 8 bit PWM Mode is given by Equation 16 2 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 wr...

Page 163: ...re compare register writes The duty cycle for 16 bit PWM Mode is given by Equation 16 3 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Equation 16 3 16 Bit PWM Duty Cycle Using Equation 16 3 the largest duty ...

Page 164: ...CA0L and PCA0H are not allowed PCA clock source bits CPS2 CPS0 are frozen PCA Idle control bit CIDL is frozen Module 2 is forced into software timer mode Writes to the module 2 mode register PCA0CPM2 are disabled While the WDT is enabled writes to the CR bit will not change the PCA counter state the counter will run until the WDT is disabled The PCA counter run control CR will read zero if the WDT...

Page 165: ...to the WDTE bit Select the desired PCA clock source with the CPS2 CPS0 bits Load PCA0CPL2 with the desired WDT update offset value Configure the PCA Idle mode set CIDL if the WDT should be suspended while the CPU is in Idle mode Enable the WDT by setting the WDTE bit to 1 Reload the WDT by writing any value to PCA0CPH2 The PCA clock source and Idle mode select cannot be changed while the WDT is en...

Page 166: ... 5 11 059 200 255 71 1 11 059 200 128 35 8 11 059 200 32 9 2 3 062 5002 255 257 3 062 5002 128 129 5 3 062 5002 32 33 1 32 000 255 24576 32 000 128 12384 32 000 32 3168 Notes 1 Assumes SYSCLK 12 as the PCA clock source and a PCA0L value of 0x00 at the update time 2 Internal oscillator reset frequency for devices with a calibrated internal oscillator The reset system clock for devices with an uncal...

Page 167: ...set by hardware when a match or capture occurs When the CCF2 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit1 CCF1 PCA Module 1 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF1 interrupt is enabled setting this bit ca...

Page 168: ...ounter Timer Pulse Select These bits select the clock source for the PCA counter Bit0 ECF PCA Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCA Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCA Counter Timer Overflow interrupt when CF PCA0CN 7 is set Note When the WDTE bit is set to 1 the PCA0MD register cannot be modified To change the conten...

Page 169: ...PCA0MD register to be set to logic 1 0 Disabled 1 Enabled Bit2 TOGn Toggle Function Enable This bit enables disables the toggle function for PCA Module n When enabled matches of the PCA counter with a module s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module operates in Frequency Output Mode 0 Disabled 1 Enabled Bit1 PWMn Pu...

Page 170: ...ster holds the low byte LSB of the 16 bit PCA Counter Timer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xF9 Bits 7 0 PCA0H PCA Counter Timer High Byte The PCA0H register holds the high byte MSB of the 16 bit PCA Counter Timer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xFA ...

Page 171: ...holds the low byte LSB of the 16 bit capture Module n R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xFB 0xE9 0xEB PCA0CPHn Address PCA0CPH0 0xFC n 0 PCA0CPH1 0xEA n 1 PCA0CPH2 0xEC n 2 Bits7 0 PCA0CPHn PCA Capture Module High Byte The PCA0CPHn register holds the high byte MSB of the 16 bit capture Module n R W R W R W R W R W R W R W R W ...

Page 172: ...C8051F300 1 2 3 4 5 172 Rev 2 9 NOTES ...

Page 173: ...r Definition 17 2 DEVICEID C2 Device ID Bits7 0 The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address Description 0x00 Selects the Device ID register for Data Read instructions 0x01 Selects the Revision ID register for Data Read instructions 0x02 Selects th...

Page 174: ...Flash programming via the C2 interface To enable C2 Flash programming the following codes must be written in order 0x02 0x01 Note that once C2 Flash programming is enabled a system reset must be issued to resume normal operation Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 FPDAT C2 Flash Programming Data Register This register is used to pass Flash commands addresses and da...

Page 175: ...afely borrow the C2CK normally RST and C2D normally P0 7 pins In most applications external resistors are required to isolate C2 interface traffic from the user appli cation A typical isolation configuration is shown in Figure 17 1 Figure 17 1 Typical C2 Pin Sharing The configuration in Figure 17 1 assumes the following 1 The user input b cannot change state while the target device is halted 2 The...

Page 176: ...ter Clarified external capacitor example SMBus chapter Figure 14 5 SMB0CF regis ter Added a description of the behavior of Timer 3 in split mode if SMBTOE is set Timers chapter Changed references to TL2 and TH2 to TMR2L and TMR2H respec tively Revision 2 4 to Revision 2 5 Fixed variables and applied formatting changes Revision 2 5 to Revision 2 6 Updated Table 1 1 Product Selection Guide to includ...

Page 177: ...C8051F300 1 2 3 4 5 Rev 2 9 177 NOTES ...

Page 178: ...or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons...