Silicon Laboratories C8051F340 Product Manual Download | Manualshive

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Rev. 1.3

227

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

20.5. Serial Clock Timing

Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 20.5. For slave mode, the clock and
data relationships are shown in Figure 20.6 and Figure 20.7.

The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 20.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in
4-wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.

Figure 20.5. Master Mode Data/Clock Timing

SCK
(CKPOL=0, CKPHA=0)

SCK
(CKPOL=0, CKPHA=1)

SCK
(CKPOL=1, CKPHA=0)

SCK
(CKPOL=1, CKPHA=1)

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MISO/MOSI

NSS (Must Remain High
in Multi-Master Mode)

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Summary of Contents for C8051F340

Page 1: ...gh Speed 8051 µC Core Pipelined instruction architecture executes 70 of Instructions in 1 or 2 system clocks 48 MIPS and 25 MIPS versions available Expanded interrupt handler Memory 4352 or 2304 Bytes RAM 64 or 32 kB Flash In system programmable in 512 byte sectors Digital Peripherals 40 25 Port I O All 5 V tolerant with high sink current Hardware enhanced SPI SMBus and one or two enhanced UART se...

Page 2: ...C8051F340 1 2 3 4 5 6 7 8 9 A B C D 2 Rev 1 4 ...

Page 3: ... Only 57 7 Comparators 59 8 Voltage Regulator REG0 69 8 1 Regulator Mode Selection 69 8 2 VBUS Detection 69 9 CIP 51 Microcontroller 73 9 1 Instruction Set 74 9 1 1 Instruction and CPU Timing 74 9 1 2 MOVX Instruction and Program Memory 75 9 2 Memory Organization 79 9 2 1 Program Memory 80 9 2 2 Data Memory 81 9 2 3 General Purpose Registers 81 9 2 4 Bit Addressable Locations 81 9 2 5 Stack 81 9 2...

Page 4: ...16 13 4 Port Configuration 116 13 5 Multiplexed and Non multiplexed Selection 119 13 5 1 Multiplexed Configuration 119 13 5 2 Non multiplexed Configuration 120 13 6 Memory Mode Selection 120 13 6 1 Internal XRAM Only 121 13 6 2 Split Mode without Bank Select 121 13 6 3 Split Mode with Bank Select 122 13 6 4 External Only 122 13 7 Timing 122 13 7 1 Non multiplexed Mode 124 13 7 2 Multiplexed Mode 1...

Page 5: ... 10 1 Endpoint0 SETUP Transactions 177 16 10 2 Endpoint0 IN Transactions 177 16 10 3 Endpoint0 OUT Transactions 178 16 11 Configuring Endpoints1 3 180 16 12 Controlling Endpoints1 3 IN 180 16 12 1 Endpoints1 3 IN Interrupt or Bulk Mode 180 16 12 2 Endpoints1 3 IN Isochronous Mode 181 16 13 Controlling Endpoints1 3 OUT 183 16 13 1 Endpoints1 3 OUT Interrupt or Bulk Mode 183 16 13 2 Endpoints1 3 OUT...

Page 6: ...l Clock SCK 223 20 1 4 Slave Select NSS 223 20 2 SPI0 Master Mode Operation 224 20 3 SPI0 Slave Mode Operation 226 20 4 SPI0 Interrupt Sources 226 20 5 Serial Clock Timing 227 20 6 SPI Special Function Registers 229 21 Timers 235 21 1 Timer 0 and Timer 1 235 21 1 1 Mode 0 13 bit Counter Timer 235 21 1 2 Mode 1 16 bit Counter Timer 236 21 1 3 Mode 2 8 bit Counter Timer with Auto Reload 237 21 1 4 M...

Page 7: ...1 22 2 5 8 Bit Pulse Width Modulator Mode 262 22 2 6 16 Bit Pulse Width Modulator Mode 263 22 3 Watchdog Timer Mode 264 22 3 1 Watchdog Timer Operation 264 22 3 2 Watchdog Timer Usage 265 22 4 Register Descriptions for PCA 266 23 C2 Interface 271 23 1 C2 Interface Registers 271 23 2 C2 Pin Sharing 273 Document Change List 274 Contact Information 276 ...

Page 8: ...onversion Example Timing 46 Figure 5 5 ADC0 Equivalent Input Circuits 47 Figure 5 6 ADC Window Compare Example Right Justified Single Ended Data 54 Figure 5 7 ADC Window Compare Example Left Justified Single Ended Data 54 Figure 5 8 ADC Window Compare Example Right Justified Differential Data 55 Figure 5 9 ADC Window Compare Example Left Justified Differential Data 55 6 Voltage Reference C8051F340...

Page 9: ...gure 15 2 Port I O Cell Block Diagram 143 Figure 15 3 Peripheral Availability on Port I O Pins 144 Figure 15 4 Crossbar Priority Decoder in Example Configuration No Pins Skipped 145 Figure 15 5 Crossbar Priority Decoder in Example Configuration 3 Pins Skipped 146 16 Universal Serial Bus Controller USB0 Figure 16 1 USB0 Block Diagram 159 Figure 16 2 USB0 Register Access Scheme 162 Figure 16 3 USB F...

Page 10: ...33 Figure 20 11 SPI Slave Timing CKPHA 1 233 21 Timers Figure 21 1 T0 Mode 0 Block Diagram 236 Figure 21 2 T0 Mode 2 Block Diagram 237 Figure 21 3 T0 Mode 3 Block Diagram 238 Figure 21 4 Timer 2 16 Bit Mode Block Diagram 243 Figure 21 5 Timer 2 8 Bit Mode Block Diagram 244 Figure 21 6 Timer 2 Capture Mode T2SPLIT 0 245 Figure 21 7 Timer 2 Capture Mode T2SPLIT 1 246 Figure 21 8 Timer 3 16 Bit Mode ...

Page 11: ...cteristics 58 7 Comparators Table 7 1 Comparator Electrical Characteristics 68 8 Voltage Regulator REG0 Table 8 1 Voltage Regulator Electrical Specifications 69 9 CIP 51 Microcontroller Table 9 1 CIP 51 Instruction Set Summary 75 Table 9 2 Special Function Register SFR Memory Map 82 Table 9 3 Special Function Registers 83 Table 9 4 Interrupt Summary 90 11 Reset Sources Table 11 1 Reset Electrical ...

Page 12: ...aud Rates Using the Internal Oscillator 212 19 UART1 C8051F340 1 4 5 8 A B C Only Table 19 1 Baud Rate Generator Settings for Standard Baud Rates 214 20 Enhanced Serial Peripheral Interface SPI0 Table 20 1 SPI Slave Timing Parameters 234 22 Programmable Counter Array PCA0 Table 22 1 PCA Timebase Input Options 256 Table 22 2 PCA0CPM Register Settings for PCA Capture Compare Modules 257 Table 22 3 W...

Page 13: ... Data Pointer Low Byte 86 SFR Definition 9 2 DPH Data Pointer High Byte 86 SFR Definition 9 3 SP Stack Pointer 86 SFR Definition 9 4 PSW Program Status Word 87 SFR Definition 9 5 ACC Accumulator 87 SFR Definition 9 6 B B Register 88 SFR Definition 9 7 IE Interrupt Enable 91 SFR Definition 9 8 IP Interrupt Priority 92 SFR Definition 9 9 EIE1 Extended Interrupt Enable 1 93 SFR Definition 9 10 EIP1 E...

Page 14: ... Mode 155 SFR Definition 15 19 P3SKIP Port3 Skip 156 SFR Definition 15 20 P4 Port4 Latch 156 SFR Definition 15 21 P4MDIN Port4 Input Mode 157 SFR Definition 15 22 P4MDOUT Port4 Output Mode 157 SFR Definition 16 1 USB0XCN USB0 Transceiver Control 161 SFR Definition 16 2 USB0ADR USB0 Indirect Address 163 SFR Definition 16 3 USB0DAT USB0 Data 164 USB Register Definition 16 4 INDEX USB0 Endpoint Index...

Page 15: ...inition 20 1 SPI0CFG SPI0 Configuration 229 SFR Definition 20 2 SPI0CN SPI0 Control 230 SFR Definition 20 3 SPI0CKR SPI0 Clock Rate 231 SFR Definition 20 4 SPI0DAT SPI0 Data 231 SFR Definition 21 1 TCON Timer Control 239 SFR Definition 21 2 TMOD Timer Mode 240 SFR Definition 21 3 CKCON Clock Control 241 SFR Definition 21 4 TL0 Timer 0 Low Byte 242 SFR Definition 21 5 TL1 Timer 1 Low Byte 242 SFR D...

Page 16: ... PCA0CPHn PCA Capture Module High Byte 270 C2 Register Definition 23 1 C2ADD C2 Address 271 C2 Register Definition 23 2 DEVICEID C2 Device ID 271 C2 Register Definition 23 3 REVID C2 Revision ID 272 C2 Register Definition 23 4 FPCTL C2 Flash Programming Control 272 C2 Register Definition 23 5 FPDAT C2 Flash Programming Data 272 ...

Page 17: ...5 V tolerant With on chip Power On Reset VDD monitor Voltage Regulator Watchdog Timer and clock oscillator C8051F340 1 2 3 4 5 6 7 8 9 A B C D devices are truly stand alone System on a Chip solutions The Flash memory can be reprogrammed in circuit providing non volatile data storage and also allowing field upgrades of the 8051 firmware User software has complete control of all peripherals and may ...

Page 18: ...52 1 4 25 2 LQFP32 C8051F342 GM 48 64k 4352 1 4 25 2 QFN32 C8051F343 GQ 48 32k 2304 1 4 25 2 LQFP32 C8051F343 GM 48 32k 2304 1 4 25 2 QFN32 C8051F344 GQ 25 64k 4352 2 4 40 2 TQFP48 C8051F345 GQ 25 32k 2304 2 4 40 2 TQFP48 C8051F346 GQ 25 64k 4352 1 4 25 2 LQFP32 C8051F346 GM 25 64k 4352 1 4 25 2 QFN32 C8051F347 GQ 25 32k 2304 1 4 25 2 LQFP32 C8051F347 GM 25 32k 2304 1 4 25 2 QFN32 C8051F348 GQ 25 ...

Page 19: ...rt 1 Drivers Port 2 Drivers Port 3 Drivers Port 4 Drivers P1 0 P1 1 P1 2 P1 3 P1 4 CNVSTR P1 5 VREF P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 P4 0 P4 1 P4 2 P4 3 P4 4 P4 5 P4 6 P4 7 Supply Monitor System Clock Setup External Oscillator Internal Oscillator XTAL1 XTAL2 Low Freq Oscillator Clock Multiplier Clock Recovery USB Peripheral Controller 1k Byt...

Page 20: ...P0 2 XTAL1 P0 3 XTAL2 P0 4 P0 5 P0 6 CNVSTR P0 7 VREF Port 1 Drivers Port 2 Drivers Port 3 Drivers P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 C2D Supply Monitor System Clock Setup External Oscillator Internal Oscillator XTAL1 XTAL2 Low Freq Oscillator Clock Multiplier Clock Recovery USB Peripheral Controller 1 kB RAM Full Low Speed Transceiver SFR Bus Volt...

Page 21: ...1 3 P1 4 CNVSTR P1 5 VREF P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 P4 0 P4 1 P4 2 P4 3 P4 4 P4 5 P4 6 P4 7 Supply Monitor System Clock Setup External Oscillator Internal Oscillator XTAL1 XTAL2 Low Freq Oscillator Clock Multiplier Clock Recovery USB Peripheral Controller 1k Byte RAM Full Low Speed Transceiver External Memory Interface Control Address...

Page 22: ...7 VREF Port 1 Drivers Port 2 Drivers Port 3 Drivers P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 C2D Supply Monitor System Clock Setup External Oscillator Internal Oscillator XTAL1 XTAL2 Low Freq Oscillator Clock Multiplier Clock Recovery USB Peripheral Controller 1 kB RAM Full Low Speed Transceiver SFR Bus Voltage Regulator D D VBUS VDD VREG GND C2CK RST Re...

Page 23: ...3 PCA WDT SMBus SPI P0 1 P0 2 XTAL1 P0 3 XTAL2 P0 4 P0 5 P0 6 CNVSTR P0 7 VREF Port 1 Drivers Port 2 Drivers Port 3 Drivers P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 C2D Supply Monitor System Clock Setup External Oscillator Internal Oscillator XTAL1 XTAL2 Low Freq Oscillator Clock Multiplier Clock Recovery USB Peripheral Controller 1 kB RAM Full Low Speed...

Page 24: ...ect to GND 0 3 4 2 V Maximum Total current through VDD and GND 500 mA Maximum output current sunk by RST or any Port pin 100 mA Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specifica...

Page 25: ...D 3 6 V SYSCLK 48 MHz VDD 3 6 V SYSCLK 24 MHz 25 9 13 9 0 69 55 29 7 15 9 28 5 15 7 32 3 18 mA mA mA µA mA mA IDD Supply Sensitivity3 4 SYSCLK 1 MHz relative to VDD 3 3 V SYSCLK 24 MHz relative to VDD 3 3 V 47 46 V V IDD Frequency Sensitivity3 5 VDD 3 3 V SYSCLK 30 MHz T 25 ºC VDD 3 3 V SYSCLK 30 MHz T 25 ºC VDD 3 6 V SYSCLK 30 MHz T 25 ºC VDD 3 6 V SYSCLK 30 MHz T 25 ºC 0 69 0 44 0 80 0 50 mA MHz...

Page 26: ...r than those specified can be calculated using the IDD Supply Sensitivity For example if the VDD is 3 0 V instead of 3 3 V at 24 MHz IDD 13 9 mA typical at 3 3 V and SYSCLK 24 MHz From this IDD 13 9 mA 0 46 x 3 0 V 3 3 V 13 76 mA at 3 0 V and SYSCLK 24 MHz 5 IDD can be estimated for frequencies 30 MHz by multiplying the frequency of interest by the frequency sensitivity number for that range When ...

Page 27: ...e Electrical Characteristics 58 Comparator Electrical Characteristics 68 Voltage Regulator Electrical Specifications 69 Reset Electrical Characteristics 106 Flash Electrical Characteristics 109 AC Parameters for External Memory Interface 130 Oscillator Electrical Characteristics 141 Port I O DC Electrical Characteristics 158 USB Transceiver Electrical Characteristics 187 ...

Page 28: ... data signal for the C2 Debug Interface P3 0 C2D 10 D I O D I O Port 3 0 See Section 15 for a complete description of Port 3 Bi directional data signal for the C2 Debug Interface REGIN 11 7 Power In 5 V Regulator Input This pin is the input to the on chip volt age regulator VBUS 12 8 D In VBUS Sense Input This pin should be connected to the VBUS signal of a USB network A 5 V signal on this pin ind...

Page 29: ... I O or A In Port 2 0 See Section 15 for a complete description of Port 2 P2 1 37 17 D I O or A In Port 2 1 P2 2 36 16 D I O or A In Port 2 2 P2 3 35 15 D I O or A In Port 2 3 P2 4 34 14 D I O or A In Port 2 4 P2 5 33 13 D I O or A In Port 2 5 P2 6 32 12 D I O or A In Port 2 6 P2 7 31 11 D I O or A In Port 2 7 P3 0 30 D I O or A In Port 3 0 See Section 15 for a complete description of Port 3 P3 1 ...

Page 30: ...O or A In Port 4 0 See Section 15 for a complete description of Port 4 P4 1 21 D I O or A In Port 4 1 P4 2 20 D I O or A In Port 4 2 P4 3 19 D I O or A In Port 4 3 P4 4 18 D I O or A In Port 4 4 P4 5 17 D I O or A In Port 4 5 P4 6 16 D I O or A In Port 4 6 P4 7 15 D I O or A In Port 4 7 Table 4 1 Pin Definitions for the C8051F340 1 2 3 4 5 6 7 8 9 A B C D Continued Name Pin Numbers Type Descriptio...

Page 31: ...7 26 25 48 47 46 45 44 43 42 41 40 39 38 37 VBUS P2 2 P2 0 P1 7 P1 6 P1 2 P2 4 P2 3 P3 5 P3 4 P3 2 P3 1 P2 1 P0 6 P3 3 P0 7 P0 2 D REGIN P0 3 P3 0 P1 4 P1 5 P0 5 P1 1 P1 0 P0 4 P1 3 13 14 15 16 17 18 19 20 21 22 23 24 P2 6 P2 5 C8051F340 1 4 5 8 C GQ Top View GND D P0 1 P0 0 VDD P2 7 P3 6 P4 1 P4 0 P3 7 P4 2 P4 5 P4 4 P4 3 P4 6 RST C2CK C2D P4 7 ...

Page 32: ...9 00 BSC D1 7 00 BSC e 0 50 BSC E 9 00 BSC E1 7 00 BSC L 0 45 0 60 0 75 aaa 0 20 bbb 0 20 ccc 0 08 ddd 0 08 0 3 5 7 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC outline MS 026 variation ABC 4 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Bod...

Page 33: ...etal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 µm minimum all the way around the pad Stencil Design 4 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125 mm 5 mils 6 The ratio of stencil aperture to land pad size sh...

Page 34: ...iew 1 VBUS P1 2 P1 7 P1 4 P1 3 P1 5 D D GND P0 1 P0 0 P2 0 P2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 P1 6 C8051F342 3 6 7 9 A B D GQ Top View VDD REGIN RST C2CK P3 0 C2D P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P1 1 P1 0 P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 ...

Page 35: ...9 00 BSC D1 7 00 BSC e 0 80 BSC E 9 00 BSC E1 7 00 BSC L 0 45 0 60 0 75 aaa 0 20 bbb 0 20 ccc 0 10 ddd 0 20 0 3 5 7 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC outline MS 026 variation BBA 4 The recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Bod...

Page 36: ...etal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 µm minimum all the way around the pad Stencil Design 4 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125 mm 5 mils 6 The ratio of stencil aperture to land pad size sh...

Page 37: ... P1 1 17 P2 1 16 P2 2 8 VBUS 32 31 30 29 28 27 26 1 2 3 4 5 6 7 9 10 11 12 13 14 15 24 23 22 21 20 19 18 GND optional C8051F342 3 6 7 9 A B GM Top View P1 0 P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 GND D D VDD REGIN RST C2CK P3 0 C2D P2 7 P2 6 P2 5 P2 4 P2 3 P2 0 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 ...

Page 38: ...00 BSC E2 3 20 3 30 3 40 L 0 30 0 40 0 50 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 variation VHHD except for custom features D2 E2 and L which are toleranced per supplier designation 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 spe...

Page 39: ...mensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 variation VHHD except for custom features D2 E2 and L which are toleranced per supplier designation 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components ...

Page 40: ... NSMD Clearance between the solder mask and the metal pad is to be 60 m minimum all the way around the pad Stencil Design 4 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125 mm 5 mils 6 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pins 7 A 3x3 a...

Page 41: ...ions for AMUX0 are detailed in SFR Definition 5 1 and SFR Definition 5 2 The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register ADC0CN is set to logic 1 The ADC0 sub system is in low power shutdown when this bit is logic 0 Figure 5 1 ADC0 Functional Block Diagram ADC0CF AD0LJST AD0SC0 AD0SC1 AD0SC2 AD0SC3 AD0SC4 10 Bit SAR ADC REF SYSCLK ADC0H 32 ADC0CN AD0CM0 AD0CM1 AD...

Page 42: ...d bits in the ADC0H and ADC0L registers are set to 0 When in Differential Mode conversion codes are represented as 10 bit signed 2 s complement numbers Inputs are measured from VREF to VREF x 511 512 Example codes are shown below for both right jus tified and left justified data For right justified data the unused MSBs of ADC0H are a sign extension of the data word For left justified data the unus...

Page 43: ...cally a 1 point offset calibration includes the following steps Step 1 Control measure the ambient temperature this temperature must be known Step 2 Power the device and delay for a few seconds to allow for self heating Step 3 Perform an ADC conversion with the temperature sensor selected as the positive input and GND selected as the negative input Step 4 Calculate the offset characteristics and s...

Page 44: ...erature Sensor Error with 1 Point Calibration VREF 2 40 V 40 00 20 00 0 0 0 20 0 0 40 0 0 60 0 0 80 0 0 Temperature degrees C Error degrees C 5 00 4 00 3 00 2 00 1 00 0 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 5 00 4 00 3 00 2 00 1 00 0 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 ...

Page 45: ...uring conversion the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conver sion is complete The falling edge of AD0BUSY triggers an interrupt when enabled and sets the ADC0 interrupt flag AD0INT Note When polling for ADC conversion completions the ADC0 interrupt flag AD0INT should be used Converted data is available in the ADC0 data registers ADC0H ADC0L when bit AD0INT is logic 1 Not...

Page 46: ...so be disabled shutdown when the device is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX set tings are frequently changed due to the settling time requirements described in Section 5 3 3 Settling Time Requirements on page 47 Figure 5 4 10 Bit ADC Track and Conversion Example Timing Write 1 to AD0BUSY Timer 0 Timer 2 Timer 1 Timer 3 Overflow AD0CM 2 0 00...

Page 47: ...ended modes Notice that the equivalent time constant for both input circuits is the same The required ADC0 settling time for a given settling accuracy SA may be approximated by Equation 5 1 When measuring the Temperature Sensor output or VDD with respect to GND RTOTAL reduces to RMUX See Table 5 1 for ADC0 minimum settling time requirements Equation 5 1 ADC0 Settling Time Requirements Where SA is ...

Page 48: ...t0 SFR Address 0xBB AMX0P4 0 ADC0 Positive Input 32 pin Package ADC0 Positive Input 48 pin Package 00000 P1 0 P2 0 00001 P1 1 P2 1 00010 P1 2 P2 2 00011 P1 3 P2 3 00100 P1 4 P2 5 00101 P1 5 P2 6 00110 P1 6 P3 0 00111 P1 7 P3 1 01000 P2 0 P3 4 01001 P2 1 P3 5 01010 P2 2 P3 7 01011 P2 3 P4 0 01100 P2 4 P4 3 01101 P2 5 P4 4 01110 P2 6 P4 5 01111 P2 7 P4 6 10000 P3 0 RESERVED 10001 P0 0 P0 3 10010 P0 ...

Page 49: ...0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xBA AMX0N4 0 ADC0 Negative Input 32 pin Package ADC0 Negative Input 48 pin Package 00000 P1 0 P2 0 00001 P1 1 P2 1 00010 P1 2 P2 2 00011 P1 3 P2 3 00100 P1 4 P2 5 00101 P1 5 P2 6 00110 P1 6 P3 0 00111 P1 7 P3 1 01000 P2 0 P3 4 01001 P2 1 P3 5 01010 P2 2 P3 7 01011 P2 3 P4 0 01100 P2 4 P4 3 01101 P2 5 P4 4 01110 ...

Page 50: ... W R W R W R W R W R W Reset Value AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xBC AD0SC SYSCLK CLKSAR 1 Bits7 0 ADC0 Data Word High Order Bits For AD0LJST 0 Bits 7 2 are the sign extension of Bit1 Bits 1 0 are the upper 2 bits of the 10 bit ADC0 Data Word For AD0LJST 1 Bits 7 0 are the most significant bits of the 10 bit ADC0 Data Word ...

Page 51: ...son Data match has occurred Bits2 0 AD0CM2 0 ADC0 Start of Conversion Mode Select When AD0TM 0 000 ADC0 conversion initiated on every write of 1 to AD0BUSY 001 ADC0 conversion initiated on overflow of Timer 0 010 ADC0 conversion initiated on overflow of Timer 2 011 ADC0 conversion initiated on overflow of Timer 1 100 ADC0 conversion initiated on rising edge of external CNVSTR 101 ADC0 conversion i...

Page 52: ...r flag can be programmed to indicate when mea sured data is inside or outside of the user programmed limits depending on the contents of the ADC0 Less Than and ADC0 Greater Than registers The Window Detector registers must be written with the same format left right justified signed unsigned as that of the current ADC configuration left right justified single ended differential SFR Definition 5 7 A...

Page 53: ...0 Less Than Data Low Byte Bits7 0 High byte of ADC0 Less Than Data Word R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xC6 Bits7 0 Low byte of ADC0 Less Than Data Word R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xC5 ...

Page 54: ... ADC0GT and ADC0LT register settings Figure 5 6 ADC Window Compare Example Right Justified Single Ended Data Figure 5 7 ADC Window Compare Example Left Justified Single Ended Data 0x03FF 0x0081 0x0080 0x007F 0x0041 0x0040 0x003F 0x0000 0 Input Voltage Px x GND VREF x 1023 1024 VREF x 128 1024 VREF x 64 1024 AD0WINT 1 AD0WINT not affected AD0WINT not affected ADC0LTH ADC0LTL ADC0GTH ADC0GTL 0x03FF ...

Page 55: ...ata with equivalent ADC0GT and ADC0LT register set tings Figure 5 8 ADC Window Compare Example Right Justified Differential Data Figure 5 9 ADC Window Compare Example Left Justified Differential Data 0x01FF 0x0041 0x0040 0x003F 0x0000 0xFFFF 0xFFFE 0x0200 VREF Input Voltage Px x Px x VREF x 511 512 VREF x 64 512 VREF x 1 512 0x01FF 0x0041 0x0040 0x003F 0x0000 0xFFFF 0xFFFE 0x0200 VREF Input Voltag...

Page 56: ...to the 5th harmonic 67 dB Spurious Free Dynamic Range 78 dB Conversion Rate SAR Conversion Clock 3 MHz Conversion Time in SAR Clocks 10 clocks Track Hold Acquisition Time 300 ns Throughput Rate 200 ksps Analog Inputs ADC Input Voltage Range Single Ended AIN GND Differential AIN AIN 0 VREF VREF VREF V V Absolute Pin Voltage with respect to GND Single Ended or Differential 0 VDD V Input Capacitance ...

Page 57: ...ence and bias circuits are given in Table 6 1 Important Note About the VREF Pin The VREF pin when not using the on chip voltage reference or an external precision reference can be configured as a GPIO Port pin When using an external voltage refer ence or the on chip reference the VREF pin should be configured as analog pin and skipped by the Digital Crossbar To configure the VREF pin for analog mo...

Page 58: ...Input Current Sample Rate 200 ksps VREF 3 0 V 12 µA Bias Generators ADC Bias Generator BIASE 1 100 µA Reference Bias Generator 40 µA Bits7 3 UNUSED Read 00000b Write don t care Bit3 REFSL Voltage Reference Select This bit selects the source for the internal voltage reference 0 VREF pin used as voltage reference 1 VDD used as voltage reference Bit2 TEMPE Temperature Sensor Enable Bit 0 Internal Tem...

Page 59: ...operate and generate an output with the device in STOP mode When assigned to a Port pin the Comparator outputs may be configured as open drain or push pull see Section 15 2 Port I O Initialization on page 147 Comparator0 may also be used as a reset source see Section 11 5 Comparator0 Reset on page 103 The Comparator0 inputs are selected in the CPT0MX register SFR Definition 7 2 The CMX0P1 CMX0P0 b...

Page 60: ...he digital Crossbar Comparator inputs can be externally driven from 0 25 V to VDD 0 25 V without damage or upset The complete Comparator elec trical specifications are given in Table 7 1 Comparator response time may be configured in software via the CPTnMD registers see SFR Definition 7 3 and SFR Definition 7 6 Selecting a longer response time reduces the Comparator supply current See Table 7 1 fo...

Page 61: ... and falling edge output transitions For Inter rupt enable and priority control see Section 9 3 Interrupt Handler on page 88 The CPnFIF flag is set to 1 upon a Comparator falling edge and the CPnRIF flag is set to 1 upon the Comparator rising edge Once set these bits remain set until cleared by software The output state of the Comparator can be obtained at any time by reading the CPnOUT bit The Co...

Page 62: ...0 No Comparator0 Falling Edge has occurred since this flag was last cleared 1 Comparator0 Falling Edge Interrupt has occurred Bits3 2 CP0HYP1 0 Comparator0 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 20 mV Bits1 0 CP0HYN1 0 Comparator0 Negative Hysteresis Control Bits 00 Negative Hysteresis Disable...

Page 63: ... used as the Comparator0 positive input Note that the port pins used by the comparator depend on the package type 32 pin or 48 pin R W R W R W R W R W R W R W R W Reset Value CMX0N2 CMX0N1 CMX0N0 CMX0P2 CMX0P1 CMX0P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x9F CMX0N1 CMX0N1 CMX0N0 Negative Input 32 pin Package Negative Input 48 pin Package 0 0 0 P1 1 P2 1 0 0 1 P1 5 P2 6 0 1 ...

Page 64: ...e Interrupt Enable 0 Comparator0 falling edge interrupt disabled 1 Comparator0 falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CP0MD1 CP0MD0 Comparator0 Mode Select These bits select the response time for Comparator0 See Table 7 1 for response time parameters R W R W R W R W R W R W R W R W Reset Value CP0RIE CP0FIE CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bi...

Page 65: ...Flag 0 No Comparator1 Falling Edge has occurred since this flag was last cleared 1 Comparator1 Falling Edge has occurred Bits3 2 CP1HYP1 0 Comparator1 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 20 mV Bits1 0 CP1HYN1 0 Comparator1 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 ...

Page 66: ... used as the Comparator1 positive input Note that the port pins used by the comparator depend on the package type 32 pin or 48 pin R W R W R W R W R W R W R W R W Reset Value CMX1N2 CMX1N1 CMX1N0 CMX1P2 CMX1P1 CMX1P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x9E CMX1N2 CMX1N1 CMX1N0 Negative Input 32 pin Package Negative Input 48 pin Package 0 0 0 P1 3 P2 3 0 0 1 P1 7 P3 1 0 1 ...

Page 67: ...parator1 Falling Edge Interrupt Enable 0 Comparator1 falling edge interrupt disabled 1 Comparator1 falling edge interrupt enabled Bits1 0 CP1MD1 CP1MD0 Comparator1 Mode Select These bits select the response time for Comparator1 See Table 7 1 for response time parameters R W R W R W R W R W R W R W R W Reset Value CP1RIE CP1FIE CP1MD1 CP1MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Addr...

Page 68: ...0 100 mV 5200 ns Common Mode Rejection Ratio 1 5 4 mV V Positive Hysteresis 1 CP0HYP1 0 00 0 1 mV Positive Hysteresis 2 CP0HYP1 0 01 2 5 10 mV Positive Hysteresis 3 CP0HYP1 0 10 7 10 20 mV Positive Hysteresis 4 CP0HYP1 0 11 15 20 30 mV Negative Hysteresis 1 CP0HYN1 0 00 0 1 mV Negative Hysteresis 2 CP0HYN1 0 01 2 5 10 mV Negative Hysteresis 3 CP0HYN1 0 10 7 10 20 mV Negative Hysteresis 4 CP0HYN1 0...

Page 69: ...e VBSTAT bit register REG0CN indicates the current logic level of the VBUS signal If enabled a VBUS interrupt will be gener ated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN The VBUS interrupt is level sensitive and has no associated interrupt pending flag The VBUS interrupt will be active as long as the VBUS signal matches the polarity selected by VBPOL S...

Page 70: ...owered Figure 8 2 REG0 Configuration USB Self Powered Voltage Regulator REG0 5 V In 3 V Out VBUS Sense REGIN VBUS From VBUS To 3 V Power Net Device Power Net VDD Voltage Regulator REG0 5 V In 3 V Out VBUS Sense REGIN VBUS To 3 V Power Net Device Power Net VDD From 5 V Power Net From VBUS ...

Page 71: ... Regulator Disabled Figure 8 4 REG0 Configuration No USB Connection Voltage Regulator REG0 5 V In 3 V Out VBUS Sense REGIN VBUS From 3 V Power Net Device Power Net VDD From VBUS Voltage Regulator REG0 5 V In 3 V Out VBUS Sense REGIN VBUS To 3 V Power Net Device Power Net VDD From 5 V Power Net ...

Page 72: ...t This bit selects the VBUS interrupt polarity 0 VBUS interrupt active when VBUS is low 1 VBUS interrupt active when VBUS is high Bit4 REGMOD Voltage Regulator Mode Select This bit selects the Voltage Regulator mode When REGMOD is set to 1 the voltage regu lator operates in low power suspend mode 0 USB0 Voltage Regulator in normal mode 1 USB0 Voltage Regulator in low power mode Bits3 0 Reserved Re...

Page 73: ...ol system solution in a single integrated circuit The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability see Figure 9 1 for a block diagram The CIP 51 includes the following features Figure 9 1 CIP 51 Block Diagram Fully Compatible with MCS 51 Instruction Set 0 to 48 MHz Clock Frequen...

Page 74: ... occupying package pins C2 details can be found in Section 23 C2 Interface on page 271 The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs pro vides an integrated development environment IDE including editor debugger and programmer The IDE s debugger and programmer interface to the CIP 51 via the C2 interface to provide fast and efficient in system d...

Page 75: ...D A data Add immediate to A 2 2 ADDC A Rn Add register to A with carry 1 1 ADDC A direct Add direct byte to A with carry 2 2 ADDC A Ri Add indirect RAM to A with carry 1 2 ADDC A data Add immediate to A with carry 2 2 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 2 SUBB A Ri Subtract indirect RAM from A with borrow 1 2 SUBB A data Subtra...

Page 76: ...ister 2 2 MOV direct A Move A to direct byte 2 2 MOV direct Rn Move Register to direct byte 2 2 MOV direct direct Move direct byte to direct byte 3 3 MOV direct Ri Move indirect RAM to direct byte 2 2 MOV direct data Move immediate to direct byte 3 3 MOV Ri A Move A to indirect RAM 1 2 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate to indirect RAM 2 2 MOV DPTR data16...

Page 77: ...5 Program Branching ACALL addr11 Absolute subroutine call 2 4 LCALL addr16 Long subroutine call 3 5 RET Return from subroutine 1 6 RETI Return from interrupt 1 6 AJMP addr11 Absolute jump 2 4 LJMP addr16 Long jump 3 5 SJMP rel Short jump relative address 2 4 JMP A DPTR Jump indirect relative to DPTR 1 4 JZ rel Jump if A equals zero 2 2 4 JNZ rel Jump if A does not equal zero 2 2 4 CJNE A direct re...

Page 78: ...ress This could be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2K byte page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP...

Page 79: ... Memory Map for 64 kB Devices PROGRAM DATA MEMORY FLASH Direct and Indirect Addressing 0x00 0x7F Upper 128 RAM Indirect Addressing Only 0x80 0xFF Special Function Register s Direct Addressing Only DATA MEMORY RAM General Purpose Registers 0x1F 0x20 0x2F Bit Addressable Lower 128 RAM Direct and Indirect Addressing 0x30 INTERNAL DATA ADDRESS SPACE EXTERNAL DATA ADDRESS SPACE XRAM 4096 Bytes Accessab...

Page 80: ... pro vides a mechanism for the CIP 51 to update program code and use the program memory space for non volatile data storage Refer to Section 12 Flash Memory on page 107 for further details PROGRAM DATA MEMORY FLASH Direct and Indirect Addressing 0x00 0x7F Upper 128 RAM Indirect Addressing Only 0x80 0xFF Special Function Register s Direct Addressing Only DATA MEMORY RAM General Purpose Registers 0x...

Page 81: ...3 and RS1 PSW 4 select the active register bank see description of the PSW in SFR Definition 9 4 This allows fast context switching when entering subroutines and interrupt service routines Indirect addressing modes use registers R0 and R1 as index registers 9 2 4 Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 throu...

Page 82: ... use Accessing these areas will have an indeterminate effect and should be avoided Refer to the corresponding pages of the datasheet as indicated in Table 9 3 for a detailed description of each register Table 9 2 Special Function Register SFR Memory Map F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN F0 B P0MDIN P1MDIN P2MDIN P3MDIN P4MDIN EIP1 EIP2 E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA...

Page 83: ...on 63 CPT1CN 0x9A Comparator1 Control 65 CPT1MD 0x9C Comparator1 Mode Selection 67 CPT1MX 0x9E Comparator1 MUX Selection 66 DPH 0x83 Data Pointer High 86 DPL 0x82 Data Pointer Low 86 EIE1 0xE6 Extended Interrupt Enable 1 93 EIE2 0xE7 Extended Interrupt Enable 2 95 EIP1 0xF6 Extended Interrupt Priority 1 94 EIP2 0xF7 Extended Interrupt Priority 2 95 EMI0CN 0xAA External Memory Interface Control 117...

Page 84: ...re 1 Low 269 PCA0CPL2 0xEB PCA Capture 2 Low 269 PCA0CPL3 0xED PCA Capture 3 Low 269 PCA0CPL4 0xFD PCA Capture 4 Low 269 PCA0CPM0 0xDA PCA Module 0 Mode Register 268 PCA0CPM1 0xDB PCA Module 1 Mode Register 268 PCA0CPM2 0xDC PCA Module 2 Mode Register 268 PCA0CPM3 0xDD PCA Module 3 Mode Register 268 PCA0CPM4 0xDE PCA Module 4 Mode Register 268 PCA0H 0xFA PCA Counter High 269 PCA0L 0xF9 PCA Counter...

Page 85: ...2H 0xCD Timer Counter 2 High 248 TMR2L 0xCC Timer Counter 2 Low 248 TMR2RLH 0xCB Timer Counter 2 Reload High 248 TMR2RLL 0xCA Timer Counter 2 Reload Low 248 TMR3CN 0x91 Timer Counter 3Control 253 TMR3H 0x95 Timer Counter 3 High 254 TMR3L 0x94 Timer Counter 3Low 254 TMR3RLH 0x93 Timer Counter 3 Reload High 254 TMR3RLL 0x92 Timer Counter 3 Reload Low 254 VDM0CN 0xFF VDD Monitor Control 102 USB0ADR 0...

Page 86: ...inition 9 3 SP Stack Pointer Bits7 0 DPL Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indirectly addressed memory R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x82 Bits7 0 DPH Data Pointer High The DPH register is the high byte of the 16 bit DPTR DPTR is used to access indirectly addressed me...

Page 87: ...s An ADD ADDC or SUBB instruction causes a sign change overflow A MUL instruction results in an overflow result is greater than 255 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases Bit1 F1 User Flag 1 This is a bit addressable general purpose flag for use under software control Bit0 PARITY Parity Flag Th...

Page 88: ...f the individual interrupt enable settings Some interrupt pending flags are automatically cleared by the hardware when the CPU vectors to the ISR However most are not cleared by the hardware and must be cleared by software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generat...

Page 89: ...y level Low priority is the default If two interrupts are recognized simultaneously the interrupt with the higher priority is serviced first If both interrupts have the same priority level a fixed priority order is used to arbitrate given in Table 9 4 9 3 4 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs Pending interrupts are sampled and priorit...

Page 90: ...001B 3 TF1 TCON 7 Y Y ET1 IE 3 PT1 IP 3 UART0 0x0023 4 RI0 SCON0 0 TI0 SCON0 1 Y N ES0 IE 4 PS0 IP 4 Timer 2 Overflow 0x002B 5 TF2H TMR2CN 7 TF2L TMR2CN 6 Y N ET2 IE 5 PT2 IP 5 SPI0 0x0033 6 SPIF SPI0CN 7 WCOL SPI0CN 6 MODF SPI0CN 5 RXOVRN SPI0CN 4 Y N ESPI0 IE 6 PSPI0 IP 6 SMB0 0x003B 7 SI SMB0CN 0 Y N ESMB0 EIE1 0 PSMB0 EIP1 0 USB0 0x0043 8 Special N N EUSB0 EIE1 1 PUSB0 EIP1 1 ADC0 Window Compa...

Page 91: ...masking of the UART0 interrupt 0 Disable UART0 interrupt 1 Enable UART0 interrupt Bit3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable all Timer 1 interrupt 1 Enable interrupt requests generated by the TF1 flag Bit2 EX1 Enable External Interrupt 1 This bit sets the masking of External Interrupt 1 0 Disable external interrupt 1 1 Enable interrupt requests g...

Page 92: ... Priority Control This bit sets the priority of the Timer 1 interrupt 0 Timer 1 interrupt set to low priority level 1 Timer 1 interrupts set to high priority level Bit2 PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority level 1 External Interrupt 1 set to high priority level Bit1 PT0 Timer 0 Interrup...

Page 93: ...upts 1 Enable interrupt requests generated by PCA0 Bit3 EADC0 Enable ADC0 Conversion Complete Interrupt This bit sets the masking of the ADC0 Conversion Complete interrupt 0 Disable ADC0 Conversion Complete interrupt 1 Enable interrupt requests generated by the AD0INT flag Bit2 EWADC0 Enable Window Comparison ADC0 Interrupt This bit sets the masking of ADC0 Window Comparison interrupt 0 Disable AD...

Page 94: ... interrupt set to high priority level Bit3 PADC0 ADC0 Conversion Complete Interrupt Priority Control This bit sets the priority of the ADC0 Conversion Complete interrupt 0 ADC0 Conversion Complete interrupt set to low priority level 1 ADC0 Conversion Complete interrupt set to high priority level Bit2 PWADC0 ADC0 Window Comparator Interrupt Priority Control This bit sets the priority of the ADC0 Wi...

Page 95: ...enerated by VBUS level sense R W R W R W R W R W R W R W R W Reset Value ES1 EVBUS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xE7 Bits7 2 UNUSED Read 000000b Write don t care Bit1 PS1 UART1 Interrupt Priority Control This bit sets the priority of the UART1 interrupt 0 UART1 interrupt set to low priority level 1 UART1 interrupts set to high priority level Bit0 PVBUS VBUS Level In...

Page 96: ...active high Bits2 0 INT0SL2 0 INT0 Port Pin Selection Bits These bits select which Port pin is assigned to INT0 Note that this pin assignment is inde pendent of the Crossbar INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected ...

Page 97: ...n enabled interrupt is asserted or a reset occurs The assertion of an enabled interrupt will cause the Idle Mode Selection bit PCON 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Idle mode is ...

Page 98: ...s bit will always be read as 0 1 CPU goes into Stop mode internal oscillator stopped Bit0 IDLE Idle Mode Select Setting this bit will place the CIP 51 in Idle mode This bit will always be read as 0 1 CPU goes into Idle mode Shuts off clock to CPU but clock to Timers Interrupts Serial Ports and Analog Peripherals are still active R W R W R W R W R W R W R W R W Reset Value GF5 GF4 GF3 GF2 GF1 GF0 S...

Page 99: ...s how many clock cycles are used to read each set of two code bytes from FLASH When operating from a system clock of 25 MHz or less the FLRT bit should be set to 0 so that the prefetch engine takes only one clock cycle for each read When operating with a system clock of greater than 25 MHz up to 48 MHz the FLRT bit should be set to 1 so that each prefetch code read lasts for two clock cycles SFR D...

Page 100: ...r the reset For VDD Monitor and Power On Resets the RST pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator Refer to Section 14 Oscillators on page 131 for information on selecting and configuring the system clock source The Watchdog Timer is enabled with the system clock div...

Page 101: ...et all of the other reset flags in the RSTSRC Register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The content of internal data mem ory should be assumed to be undefined after a power on reset The VDD monitor is enabled followin...

Page 102: ...lemented between enabling the VDD monitor and selecting it as a reset source The procedure for configuring the VDD monitor as a reset source is shown below Step 1 Enable the VDD monitor VDM0CN 7 1 Step 2 If desired wait for the VDD monitor to stabilize see Table 11 1 for the VDD Monitor turn on time Step 3 Select the VDD monitor as a reset source RSTSRC 1 1 See Figure 11 2 for VDD monitor timing S...

Page 103: ...eset source otherwise this bit reads 0 The state of the RST pin is unaffected by this reset 11 6 PCA Watchdog Timer Reset The programmable Watchdog Timer WDT function of the Programmable Counter Array PCA can be used to prevent software from running out of control during a system malfunction The PCA WDT function can be enabled or disabled by software as described in Section 22 3 Watchdog Timer Mod...

Page 104: ...reset will be generated when either of the following occur 1 RESET signaling is detected on the USB network The USB Function Controller USB0 must be enabled for RESET signaling to be detected See Section 16 Universal Serial Bus Con troller USB0 on page 159 for information on the USB Function Controller 2 The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register REG0CN ...

Page 105: ...ock Detector timeout Write Missing Clock Detector disabled 1 Read Source of last reset was a Missing Clock Detector timeout Write Missing Clock Detector enabled triggers a reset if a missing clock condition is detected Bit1 PORSF Power On VDD Monitor Reset Flag This bit is set anytime a power on reset occurs Writing this bit selects deselects the VDD monitor as a reset source Note writing 1 to thi...

Page 106: ...VDD V RST Input Low Voltage 0 3 x VDD RST Input Pull Up Current RST 0 0 V 25 40 µA VDD POR Threshold VRST 2 40 2 55 2 70 V Missing Clock Detector Tim eout Time from last system clock ris ing edge to reset initiation 100 220 500 µs Reset Time Delay Delay between release of any reset source and code execution at location 0x0000 5 0 µs Minimum RST Low Time to Generate a System Reset 15 µs VDD Monitor...

Page 107: ... 0xA5 0xF1 The timing does not matter but the codes must be written in order If the key codes are written out of order or the wrong codes are written Flash writes and erases will be disabled until the next system reset Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly The Flash lock resets after each write or erase ...

Page 108: ...he 512 byte sector Step 8 Clear the PSWE bit Step 9 Re enable interrupts Steps 5 7 must be repeated for each byte to be written For block Flash writes the Flash write procedure is only performed after the last byte of each block is writ ten with the MOVX write instruction A Flash write block is two bytes long from even addresses to odd addresses Writes must be performed sequentially i e addresses ...

Page 109: ...gram code and data constants from being read or altered across the C2 interface A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program memory from access reads writes or erases by unprotected code or the C2 interface The Flash security mechanism allows the user to lock n 512 byte Flash pages starting at page 0 addresses 0x0000 to 0x01FF where n is ...

Page 110: ...mit set according to the FLASH security lock byte C8051F340 2 4 6 A C D 0x0000 0xFBFF Lock Byte Reserved 0xFBFE 0xFC00 FLASH memory organized in 512 byte pages 0xFA00 Unlocked FLASH Pages Locked when any other FLASH pages are locked C8051F341 3 5 7 8 9 B 0x0000 0x7FFF Lock Byte 0x7FFE 0x7E00 Unlocked FLASH Pages ...

Page 111: ... read written or erased 2 Locked pages cannot be read written or erased 3 The page containing the Lock Byte cannot be erased It may be read or written only if it is unlocked 4 Reading the contents of the Lock Byte is always permitted 5 Locking additional pages changing 1 s to 0 s in the Lock Byte is not permitted 6 Unlocking FLASH pages changing 0 s to 1 s in the Lock Byte is not permitted 7 The R...

Page 112: ... program memory disabled 1 Writes to Flash program memory enabled the MOVX write instruction targets Flash memory R W R W R W R W R W R W R W R W Reset Value Reserved PSEE PSWE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8F Bits 0 FLKEY Flash Lock and Key Register Write This register must be written to before Flash writes or erases can be performed Flash remains locked until thi...

Page 113: ...he Flash one shot will increase system power consumption 0 Flash one shot disabled 1 Flash one shot enabled Bits6 5 RESERVED Read 00b Must Write 00b Bit 4 FLRT FLASH Read Time This bit should be programmed to the smallest allowed value according to the system clock speed 0 SYSCLK 25 MHz 1 SYSCLK 48 MHz Bits3 0 RESERVED Read 0000b Must Write 0000b R W R W R W R W R W R W R W R W Reset Value FOSE Re...

Page 114: ...essing method The first method uses the Data Pointer DPTR a 16 bit register which contains the effective address of the XRAM location to be read from or written to The sec ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM address Examples of both of these methods are given below 13 1 1 16 Bit MOVX Example The 16 bit form of the MOVX instruction accesse...

Page 115: ...he MOVX instruction is increased when accessing USB FIFO space To access the FIFO RAM directly using MOVX instructions the following conditions must be met 1 the USBFAE bit in register EMI0CF must be set to 1 and 2 the USB clock must be greater than or equal to twice the SYSCLK USBCLK 2 x SYSCLK When this bit is set the USB FIFO space is mapped into XRAM space at addresses 0x0400 to 0x07FF The nor...

Page 116: ... 7 WR P1 6 RD and if multiplexed mode is selected P1 3 ALE using the P1SKIP register For more information about configuring the Crossbar see Section Figure 15 1 Port I O Functional Block Diagram Port 0 through Port 3 on page 142 The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off chip MOVX instruction Once the MOVX instruction has...

Page 117: ...e high byte of the 16 bit external data memory address when using an 8 bit MOVX command effectively selecting a 256 byte page of RAM 0x00 0x0000 to 0x00FF 0x01 0x0100 to 0x01FF 0xFE 0xFE00 to 0xFEFF 0xFF 0xFF00 to 0xFFFF R W R W R W R W R W R W R W R W Reset Value PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSEL0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xAA ...

Page 118: ...t Accesses below the on chip XRAM boundary are directed on chip Accesses above the on chip XRAM boundary are directed off chip 8 bit off chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte Note that in order to access off chip space EMI0CN must be set to a page that is not contained in the on chip address space 10 Split Mode with Bank Select...

Page 119: ...tion is shown in Figure 13 2 In Multiplexed mode the external MOVX operation can be broken into two phases delineated by the state of the ALE signal During the first phase ALE is high and the lower 8 bits of the Address Bus are pre sented to AD 7 0 During this phase the address latch is configured such that the Q outputs reflect the states of the D inputs When ALE falls signaling the beginning of ...

Page 120: ...d in one of four modes shown in Figure 13 4 based on the EMIF Mode bits in the EMI0CF register SFR Definition 13 2 These modes are summarized below More information about the different modes can be found in Section 13 7 Timing on page 122 Figure 13 4 EMIF Operating Modes ADDRESS BUS E M I F A 15 0 64K X 8 SRAM A 15 0 DATA BUS D 7 0 I O 7 0 VDD 8 WR RD OE WE CE Optional EMI0CF 3 2 00 0xFFFF 0x0000 ...

Page 121: ...wo areas on chip space and off chip space Effective addresses below the internal XRAM size boundary will access on chip XRAM space Effective addresses above the internal XRAM size boundary will access off chip space 8 bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on chip or off chip However in the No Bank Select mode an 8 bit MOVX operation will not drive...

Page 122: ...te the upper address bits at will by setting the Port state directly The lower 8 bits of the effective address A 7 0 are determined by the contents of R0 or R1 16 bit MOVX operations use the contents of DPTR to determine the effective address A 15 0 The full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 13 7 Timing The timing parameters of the External Memory Interfa...

Page 123: ...th 6 SYSCLK cycles 0110 WR and RD pulse width 7 SYSCLK cycles 0111 WR and RD pulse width 8 SYSCLK cycles 1000 WR and RD pulse width 9 SYSCLK cycles 1001 WR and RD pulse width 10 SYSCLK cycles 1010 WR and RD pulse width 11 SYSCLK cycles 1011 WR and RD pulse width 12 SYSCLK cycles 1100 WR and RD pulse width 13 SYSCLK cycles 1101 WR and RD pulse width 14 SYSCLK cycles 1110 WR and RD pulse width 15 SY...

Page 124: ...S 8 MSBs from DPH EMIF ADDRESS 8 LSBs from DPL P3 P2 P1 7 P1 6 P4 EMIF WRITE DATA P3 P2 P1 7 P1 6 P4 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 MSBs from DPH EMIF ADDRESS 8 LSBs from DPL P3 P2 P1 6 P1 7 P4 P3 P2 P1 6 P1 7 P4 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 16 bit WRITE Nonmuxed 16 bit READ ...

Page 125: ...EMIF ADDRESS 8 LSBs from R0 or R1 P3 P2 P1 7 P1 6 P4 EMIF WRITE DATA P3 P1 7 P1 6 P4 T ACH T WDH T ACW T ACS T WDS ADDR 15 8 ADDR 7 0 DATA 7 0 WR RD EMIF ADDRESS 8 LSBs from R0 or R1 P3 P2 P1 6 P1 7 P4 P3 P1 6 P1 7 P4 T ACH T RDH T ACW T ACS T RDS ADDR 15 8 ADDR 7 0 DATA 7 0 RD WR EMIF READ DATA Nonmuxed 8 bit WRITE without Bank Select Nonmuxed 8 bit READ without Bank Select ...

Page 126: ... 7 P1 6 P1 3 T ACH T WDH T ACW T ACS T WDS ALE WR RD EMIF ADDRESS 8 MSBs from EMI0CN EMIF WRITE DATA EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL P4 P3 P4 ADDR 15 8 AD 7 0 P3 P1 6 P1 7 P1 3 P1 6 P1 7 P1 3 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 MSBs from EMI0CN EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 8 bit WRITE with Bank Select Muxed 8 bit READ with ...

Page 127: ... 0 P3 P1 7 P1 6 P1 3 P1 7 P1 6 P1 3 T ACH T WDH T ACW T ACS T WDS ALE WR RD EMIF ADDRESS 8 MSBs from DPH EMIF WRITE DATA EMIF ADDRESS 8 LSBs from DPL T ALEH T ALEL P4 P3 P4 ADDR 15 8 AD 7 0 P3 P1 6 P1 7 P1 3 P1 6 P1 7 P1 3 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 MSBs from DPH EMIF ADDRESS 8 LSBs from DPL T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 16 bit WRITE Muxed 16 bit READ ...

Page 128: ...DDR 15 8 AD 7 0 P1 7 P1 6 P1 3 P1 7 P1 6 P1 3 T ACH T WDH T ACW T ACS T WDS ALE WR RD EMIF WRITE DATA EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL P4 P3 P4 ADDR 15 8 AD 7 0 P1 6 P1 7 P1 3 P1 6 P1 7 P1 3 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 8 bit WRITE Without Bank Select Muxed 8 bit READ Without Bank Select ...

Page 129: ... P1 6 P1 3 T ACH T WDH T ACW T ACS T WDS ALE WR RD EMIF ADDRESS 8 MSBs from EMI0CN EMIF WRITE DATA EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL P4 P3 P4 ADDR 15 8 AD 7 0 P3 P1 6 P1 7 P1 3 P1 6 P1 7 P1 3 T ACH T ACW T ACS ALE RD WR EMIF ADDRESS 8 MSBs from EMI0CN EMIF ADDRESS 8 LSBs from R0 or R1 T ALEH T ALEL T RDH T RDS EMIF READ DATA Muxed 8 bit WRITE with Bank Select Muxed 8 bit READ with Ba...

Page 130: ...SYSCLK 16 x TSYSCLK ns TACH Address Control Hold Time 0 3 x TSYSCLK ns TALEH Address Latch Enable High Time 1 x TSYSCLK 4 x TSYSCLK ns TALEL Address Latch Enable Low Time 1 x TSYSCLK 4 x TSYSCLK ns TWDS Write Data Setup Time 1 x TSYSCLK 19 x TSYSCLK ns TWDH Write Data Hold Time 0 3 x TSYSCLK ns TRDS Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns Note TSYSCLK is equal to one period of the...

Page 131: ... clock USBCLK can be derived from the internal oscillator external oscillator or 4x Clock Multiplier Oscillator electrical specifications are given in Table 14 1 Figure 14 1 Oscillator Diagram Clock Multiplier OSC Input Circuit XTLVLD XTAL1 XTAL2 Option 2 VDD XTAL2 Option 1 10M Option 3 XTAL2 Option 4 XTAL2 OSCXCN XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 CLKMUL MULEN MULINIT MULRDY MULSEL1...

Page 132: ...rity selected by the VBPOL bit in register REG0CN Sec tion 8 2 Note that the USB transceiver can still detect USB events when it is disabled SFR Definition 14 1 OSCICN Internal H F Oscillator Control Bit7 IOSCEN Internal H F Oscillator Enable Bit 0 Internal H F Oscillator Disabled 1 Internal H F Oscillator Enabled Bit6 IFRDY Internal H F Oscillator Frequency Ready Flag 0 Internal H F Oscillator is...

Page 133: ...sing edge Timer 3 of the low frequency oscillator s output will cause a capture event on the corresponding timer As a capture event occurs the current timer value TMRnH TMRnL is copied into the timer reload registers TMRnRLH TMRnRLL By recording the differ ence between two successive timer capture values the low frequency oscillator s period can be calcu lated The OSCLF bits can then be adjusted t...

Page 134: ...OSCLF 3 0 Internal L F Oscillator Frequency Control bits Fine tune control bits for the internal L F Oscillator frequency When set to 0000b the L F oscillator operates at its fastest setting When set to 1111b the L F oscillator operates at its slowest setting Bits1 0 OSCLD 1 0 Internal L F Oscillator Divider Select 00 Divide by 8 selected 01 Divide by 4selected 10 Divide by 2 selected 11 Divide by...

Page 135: ...election 14 3 1 Clocking Timers Directly Through the External Oscillator The external oscillator source divided by eight is a clock option for the timers Section 21 Timers on page 235 and the Programmable Counter Array PCA Section 22 Programmable Counter Array PCA0 on page 255 When the external oscillator is used to clock these peripherals but is not used as the system clock the external oscillato...

Page 136: ...ing in RC mode will improve frequency accuracy at an increased external oscillator supply cur rent 14 3 4 External Capacitor Example If a capacitor is used as an external oscillator for the MCU the circuit should be configured as shown in Figure 14 1 Option 3 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacit...

Page 137: ...it from Figure 14 1 Option 2 XOSCMD 10x Choose XFCN value to match frequency range f 1 23 103 R x C where f frequency of clock in MHz C capacitor value in pF R Pull up resistor value in k C MODE Circuit from Figure 14 1 Option 3 XOSCMD 10x Choose K Factor KF for the oscillation frequency desired f KF C x VDD where f frequency of clock in MHz C capacitor value the XTAL2 pin in pF VDD Power Supply o...

Page 138: ...l for MULRDY 1 Important Note When using an external oscillator as the input to the 4x Clock Multiplier the exter nal source must be enabled and stable before the Multiplier is initialized See Section 14 5 for details on selecting an external oscillator source SFR Definition 14 5 CLKMUL Clock Multiplier Control Bit7 MULEN Clock Multiplier Enable 0 Clock Multiplier disabled 1 Clock Multiplier enabl...

Page 139: ... on page 25 for system clock frequency specifications When operating with a sys tem clock of greater than 25 MHz up to 48 MHz the FLRT bit FLSCL 4 should be set to 1 See Section 10 Prefetch Engine on page 99 for more details 14 5 2 USB Clock Selection The USBCLK 2 0 bits in register CLKSEL select which oscillator source is used as the USB clock The USB clock may be derived from the 4x Clock Multip...

Page 140: ...m clock source When operating from a system clock of 25 MHz or less the FLRT bit should be set to 0 When operating with a system clock of greater than 25 MHz up to 48 MHz the FLRT bit FLSCL 4 should be set to 1 See Section 10 Prefetch Engine on page 99 for more details R W R W R W R W R W R W R W R W Reset Value USBCLK CLKSL 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xA9 USBCLK ...

Page 141: ...scillator Frequency IFCN 11b 11 82 12 00 12 18 MHz Oscillator Supply Current from VDD 24 ºC VDD 3 0 V OSCICN 7 1 685 µA Internal Low Frequency Oscillator Using Factory Calibrated Settings Oscillator Frequency OSCLD 11b 72 80 99 kHz Oscillator Supply Current from VDD 24 ºC VDD 3 0 V OSCLCN 7 1 7 0 µA External USB Clock Requirements USB Clock Frequency Full Speed Mode Low Speed Mode 47 88 5 91 48 6 ...

Page 142: ... Decoder Figure 15 3 and Figure 15 4 The registers XBR0 XBR1 and XBR2 defined in SFR Definition 15 1 SFR Definition 15 2 and SFR Definition 15 3 are used to select internal digital functions All Port I Os are 5 V tolerant refer to Figure 15 2 for the Port cell circuit The Port I O cells are configured as either push pull or open drain in the Port Output Mode registers PnMDOUT where n 0 1 2 3 4 Com...

Page 143: ...Rev 1 3 143 C8051F340 1 2 3 4 5 6 7 8 9 A B C D Figure 15 2 Port I O Cell Block Diagram GND PORT OUTENABLE PORT OUTPUT PUSH PULL VDD VDD W EAK PULLUP W EAK PORT PAD ANALOG INPUT Analog Select PORT INPUT ...

Page 144: ...nals and any selected ADC or Comparator inputs The PnSKIP registers may also be used to skip pins to be used as GPIO The Crossbar skips selected pins as if they were already assigned and moves to the next unas signed pin Figure 15 3 shows all the possible pins available to each peripheral Figure 15 4 shows the Crossbar Decoder priority with no Port pins skipped Figure 15 5 shows a Crossbar example...

Page 145: ...P1 T1 TX1 UART1 available only on C8051F340 1 4 5 8 A B devices 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Example XBR0 0x07 XBR1 0x43 P3 P3SKIP 0 7 SF Signals 48 pin Package P3 1 P3 7 unavailable on the 32 pin packages P2 CEX3 CEX4 P1SKIP 0 7 P1 CP1A CEX2 CEX0 CEX1 SYSCLK RX0 SDA SCL P0 SF Signals 32 pin Package PIN I O TX0 ECI T0 RX1 P2SKIP 0 7 Special Function Signals are n...

Page 146: ...f the NSSMD1 NSSMD0 bits in register SPI0CN According to the SPI mode the NSS signal may or may not be routed to a Port pin XTAL1 XTAL2 CNVSTR VREF XTAL1 XTAL2 ALE CNVSTR VREF RD WR 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK MISO MOSI NSS NSS is only pinned out in 4 wire SPI mode CP0 CP0A CP1 T1 TX1 UART1 available only on C8051F340 1 4 5 8 A B devices 0 0 1 1 0 0 0 0 1 0 ...

Page 147: ...ut and a 0 indicates an analog input All pins default to digital inputs on reset The output driver characteristics of the I O pins are defined using the Port Output Mode registers PnMD OUT Each Port Output driver can be configured as either open drain or push pull This selection is required even for the digital resources selected in the XBRn registers and is not automatic The only exception to thi...

Page 148: ...it4 CP0E Comparator0 Output Enable 0 CP0 unavailable at Port pin 1 CP0 routed to Port pin Bit3 SYSCKE SYSCLK Output Enable 0 SYSCLK unavailable at Port pin 1 SYSCLK output routed to Port pin Bit2 SMB0E SMBus I O Enable 0 SMBus I O unavailable at Port pins 1 SMBus I O routed to Port pins Bit1 SPI0E SPI I O Enable 0 SPI I O unavailable at Port pins 1 SPI I O routed to Port pins Bit0 URT0E UART0 I O ...

Page 149: ...Enable 0 ECI unavailable at Port pin 1 ECI routed to Port pin Bits2 0 PCA0ME PCA Module I O Enable Bits 000 All PCA I O unavailable at Port pins 001 CEX0 routed to Port pin 010 CEX0 CEX1 routed to Port pins 011 CEX0 CEX1 CEX2 routed to Port pins 100 CEX0 CEX1 CEX2 CEX3 routed to Port pins 101 CEX0 CEX1 CEX2 CEX3 CEX4 routed to Port pins 110 Reserved 111 Reserved R W R W R W R W R W R W R W R W Res...

Page 150: ...hen the destination is an individual bit in a Port SFR For these instructions the value of the register not the pin is read modified and written back to the SFR SFR Definition 15 4 P0 Port0 Latch SFR Definition 15 5 P0MDIN Port0 Input Mode Bits7 0 P0 7 0 Write Output appears on I O pins per Crossbar Registers when XBARE 1 0 Logic Low Output 1 Logic High Output high impedance if corresponding P0MDO...

Page 151: ...lue of P0MDOUT R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xA4 Bits7 0 P0SKIP 7 0 Port0 Crossbar Skip Enable Bits These bits select Port pins to be skipped by the Crossbar Decoder Port pins used as ana log inputs for ADC or Comparator or used as special functions VREF input external oscil lator circuit CNVSTR input should be skipped by ...

Page 152: ...0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address bit addressable 0x90 Bits7 0 Analog Input Configuration Bits for P1 7 P1 0 respectively Port pins configured as analog inputs have their weak pull up digital driver and digital receiver disabled 0 Corresponding P1 n pin is configured as an analog input 1 Corresponding P1 n pin is not configured as an analog input R W R W R W R W R W R ...

Page 153: ...e Output appears on I O pins per Crossbar Registers when XBARE 1 0 Logic Low Output 1 Logic High Output high impedance if corresponding P2MDOUT n bit 0 Read Always reads 0 if selected as analog input in register P2MDIN Directly reads Port pin when configured as digital input 0 P2 n pin is logic low 1 P2 n pin is logic high R W R W R W R W R W R W R W R W Reset Value P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P...

Page 154: ...Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xA6 Bits7 0 P2SKIP 7 0 Port2 Crossbar Skip Enable Bits These bits select Port pins to be skipped by the Crossbar Decoder Port pins used as ana log inputs for ADC or Comparator or used as special functions VREF input external oscil lator circuit CNVSTR input should be skipped by the Crossbar 0 Corresponding P2 n pin is not skipped ...

Page 155: ...it1 Bit0 SFR Address bit addressable 0xB0 Bits7 0 Analog Input Configuration Bits for P3 7 P3 0 respectively Port pins configured as analog inputs have their weak pull up digital driver and digital receiver disabled 0 Corresponding P3 n pin is configured as an analog input 1 Corresponding P3 n pin is not configured as an analog input Note P3 1 3 7 are only available on 48 pin devices R W R W R W R...

Page 156: ...n is skipped by the Crossbar Note P3 1 3 7 are only available on 48 pin devices R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xDF Bits7 0 P4 7 0 Write Output appears on I O pins 0 Logic Low Output 1 Logic High Output high impedance if corresponding P4MDOUT n bit 0 Read Always reads 0 if selected as analog input in register P4MDIN Directly...

Page 157: ...1 Corresponding P4 n pin is not configured as an analog input Note P4 is only available on 48 pin devices R W R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xF5 Bits7 0 Output Configuration Bits for P4 7 P4 0 respectively ignored if corresponding bit in regis ter P4MDIN is logic 0 0 Corresponding P4 n Output is open drain 1 Corresponding P4 n ...

Page 158: ...rameters Conditions Min Typ Max Units Output High Voltage IOH 3 mA Port I O push pull IOH 10 µA Port I O push pull IOH 10 mA Port I O push pull VDD 0 7 VDD 0 1 VDD 0 8 V Output Low Voltage IOL 8 5 mA IOL 10 µA IOL 25 mA 1 0 0 6 0 1 V Input High Voltage 2 0 V Input Low Voltage 0 8 V Input Leakage Current Weak Pull up Off Weak Pull up On VIN 0 V 25 1 50 µA ...

Page 159: ...The USB Function Controller and Transceiver is Universal Serial Bus Specification 2 0 compliant Figure 16 1 USB0 Block Diagram Important Note This document assumes a comprehensive understanding of the USB Protocol Terms and abbreviations used in this document are defined in the USB Specifi cation We encourage you to review the latest version of the USB Specification before pro ceeding Note The C80...

Page 160: ...ction and the on chip pull up resistor if enabled appears on the D pin When bit SPEED 0 USB0 operates as a Low Speed USB function and the on chip pull up resistor if enabled appears on the D pin Bits4 0 of register USB0XCN can be used for Transceiver testing as described in SFR Definition 16 1 The pull up resistor is enabled only when VBUS is present see Section 8 2 VBUS Detection on page 69 for d...

Page 161: ...led the internal pull up resistor appears on the D line Bits4 3 PHYTST1 0 Physical Layer Test These bits can be used to test the USB0 transceiver Bit2 DFREC Differential Receiver The state of this bit indicates the current differential value present on the D and D lines when PHYEN 1 0 Differential 0 signaling on the bus 1 Differential 1 signaling on the bus Bit1 Dp D Signal Status This bit indicat...

Page 162: ... end point number Once the target endpoint number is written to the INDEX register the control status registers associated with the target endpoint may be accessed See the Indexed Registers section of Table 16 2 for a list of endpoint control status registers Important Note The USB clock must be active when accessing USB registers Figure 16 2 USB0 Register Access Scheme USB Controller FIFO Access ...

Page 163: ...ss specified by the USBADDR bits Read 0 USB0DAT register data is valid 1 USB0 is busy accessing an indirect register USB0DAT register data is invalid Bit6 AUTORD USB0 Register Auto read Flag This bit is used for block FIFO reads 0 BUSY must be written manually for each USB0 indirect register read 1 The next indirect register read will automatically be initiated when software reads USB0DAT USBADDR ...

Page 164: ...ame USB0 register Read Procedure 1 Poll for BUSY USB 0ADR 7 0 2 Load the target USB0 register address into the USBADDR bits in register USB0ADR 3 Write 1 to the BUSY bit in register USB0ADR steps 2 and 3 can be performed in the same write 4 Poll for BUSY USB 0ADR 7 0 5 Read data from USB0DAT 6 Repeat from Step 2 Step 2 may be skipped when reading the same USB0 register Step 3 may be skipped when t...

Page 165: ...yte 172 INDEX 0x0E Endpoint Index Selection 165 CLKREC 0x0F Clock Recovery Control 166 FIFOn 0x20 0x23 Endpoints0 3 FIFOs 168 Indexed Registers E0CSR 0x11 Endpoint0 Control Status 179 EINCSRL Endpoint IN Control Status Low Byte 182 EINCSRH 0x12 Endpoint IN Control Status High Byte 183 EOUTCSRL 0x14 Endpoint OUT Control Status Low Byte 185 EOUTCSRH 0x15 Endpoint OUT Control Status High Byte 186 E0C...

Page 166: ...mode Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are pres ent on the USB network This mode is not required or recommended in typical USB environments USB Register Definition 16 5 CLKREC Clock Recovery Control Communication Speed USB Clock 4x Clock Multiplier Input Full Speed 4x Clock Multiplier Internal Oscillator Low Speed Internal Oscillator 2...

Page 167: ... Split Mode the upper 256 bytes 0x0540 to 0x063F are used by Endpoint3 IN and the lower 256 bytes 0x0440 to 0x053F are used by Endpoint3 OUT If an endpoint FIFO is not configured for Split Mode that endpoint IN OUT pair s FIFOs are combined to form a single IN or OUT FIFO In this case only one direction of the endpoint IN OUT pair may be used at a time The endpoint direction IN OUT is determined b...

Page 168: ... end point FIFO When an endpoint FIFO is configured for Split Mode a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO USB Register Definition 16 6 FIFOn USB0 Endpoint FIFO Access Table 16 3 FIFO Configurations Endpoint Number Split Mode Enabled Maximum IN Packet Size Dou ble Buffer Disabl...

Page 169: ...SRH EOUTCSRL EOUTCSRH 4 USB register INDEX is reset to 0x00 5 All USB interrupts excluding the Suspend interrupt are enabled and their corresponding flags cleared 6 A USB Reset interrupt is generated if enabled Writing a 1 to the USBRST bit will generate an asynchronous USB0 reset All USB registers are reset to their default values following this asynchronous reset Suspend Mode With Suspend Detect...

Page 170: ...pdate When software writes 1 to the ISOUP bit POWER 7 the ISO Update function is enabled With ISO Update enabled new packets written to an ISO IN endpoint will not be transmitted until a new Start Of Frame SOF is received If the ISO IN endpoint receives an IN token before a SOF USB0 will transmit a zero length packet When ISOUP 1 ISO Update is enabled for all ISO endpoints USB Enable USB0 is disab...

Page 171: ...Read 0 Reset signaling is not present on the bus 1 Reset signaling detected on the bus Bit2 RESUME Force Resume Software can force resume signaling on the bus to wake USB0 from suspend mode Writing a 1 to this bit while in Suspend mode SUSMD 1 forces USB0 to generate Resume sig naling on the bus a remote Wakeup event Software should write RESUME 0 after 10 ms to15 ms to end the Resume signaling An...

Page 172: ...is generated when any of the USB interrupt flags is set to 1 The USB0 interrupt is enabled via the EIE1 SFR see Section 9 3 Interrupt Handler on page 88 Important Note Reading a USB interrupt flag register resets all flags in that register to 0 Bits7 0 Frame Number Low This register contains bits7 0 of the last received frame number R R R R R R R R Reset Value Frame Number Low 00000000 Bit7 Bit6 B...

Page 173: ...pt pending Flag This bit is cleared when software reads the IN1INT register 0 Endpoint 0 interrupt inactive 1 Endpoint 0 interrupt active R R R R R R R R Reset Value IN3 IN2 IN1 EP0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address 0x02 Bits7 4 Unused Read 0000b Write don t care Bit3 OUT3 OUT Endpoint 3 Interrupt pending Flag This bit is cleared when software reads the OUT1INT register ...

Page 174: ...is detected on the bus This bit is cleared when software reads the CMINT register 0 Reset interrupt inactive 1 Reset interrupt active Bit1 RSUINT Resume Interrupt pending Flag Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend mode This bit is cleared when software reads the CMINT register 0 Resume interrupt inactive 1 Resume interrupt active Bit0 SUSINT Suspend ...

Page 175: ...0E Endpoint 0 Interrupt Enable 0 Endpoint 0 interrupt disabled 1 Endpoint 0 interrupt enabled R W R W R W R W R W R W R W R W Reset Value IN3E IN2E IN1E EP0E 00001111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address 0x07 Bits7 4 Unused Read 0000b Write don t care Bit3 OUT3E OUT Endpoint 3 Interrupt Enable 0 OUT Endpoint 3 interrupt disabled 1 OUT Endpoint 3 interrupt enabled Bit2 OUT2E OUT Endp...

Page 176: ... when 1 A data packet OUT or SETUP has been received and loaded into the Endpoint0 FIFO The OPRDY bit E0CSR 0 is set to 1 by hardware 2 An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the host INPRDY is reset to 0 by hardware 3 An IN transaction is completed this interrupt generated during the status stage of the transac tion 4 Hardware sets the STSTL bi...

Page 177: ...N Transactions When a SETUP request is received that requires USB0 to transmit data to the host one or more IN requests will be sent by the host For the first IN transaction firmware should load an IN packet into the Endpoint0 FIFO and set the INPRDY bit E0CSR 1 An interrupt will be generated when an IN packet is transmitted successfully Note that no interrupt will be generated if an IN request is...

Page 178: ... as reported to the host the host will send a zero length data packet signaling the end of the transfer Upon reception of the first OUT token for a particular control transfer Endpoint0 is said to be in Receive Mode In this mode only OUT tokens should be sent by the host to Endpoint0 The SUEND bit E0CSR 4 is set to 1 if a SETUP or IN token is received while Endpoint0 is in Receive Mode Endpoint0 w...

Page 179: ...it3 DATAEND Data End Software should write 1 to this bit 1 When writing 1 to INPRDY for the last outgoing data packet 2 When writing 1 to INPRDY for a zero length data packet 3 When writing 1 to SOPRDY after servicing the last incoming data packet This bit is automatically cleared by hardware Bit2 STSTL Sent Stall Hardware sets this bit to 1 after transmitting a STALL handshake signal This flag mu...

Page 180: ...ndpoints can be used for Interrupt Bulk or Isochronous transfers Isochronous ISO mode is enabled by writing 1 to the ISO bit in register EINCSRH Bulk and Interrupt transfers are handled identically by hardware An Endpoint1 3 IN interrupt is generated by any of the following conditions 1 An IN packet is successfully transferred to the host 2 Software writes 1 to the FLUSH bit EINCSRL 3 when the tar...

Page 181: ...Endpoints1 3 IN Isochronous Mode When the ISO bit EINCSRH 6 is set to 1 the target endpoint operates in Isochronous ISO mode Once an endpoint has been configured for ISO IN mode the host will send one IN token data request per frame the location of data within each frame may vary Because of this it is recommended that double buffering be enabled for ISO IN endpoints Hardware will automatically res...

Page 182: ...for each packet Hardware resets the FLUSH bit to 0 when the FIFO flush is complete Bit2 UNDRUN Data Underrun The function of this bit depends on the IN Endpoint mode Isochronous Set when a zero length packet is sent after an IN token is received while bit INPRDY 0 Interrupt Bulk This bit is not used in these modes and will always read a 0 This bit must be cleared by software Bit1 FIFONE FIFO Not E...

Page 183: ...g isters In response to this interrupt firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to 0 Bit7 DBIEN IN Endpoint Double buffer Enable 0 Double buffering disabled for the selected IN endpoint 1 Double buffering enabled for the selected IN endpoint Bit6 ISO Isochronous Transfer Enable This bit enables disables isochronous transfers on the current endpoint 0 Endpoin...

Page 184: ...int operates in Isochronous ISO mode Once an endpoint has been configured for ISO OUT mode the host will send exactly one data per USB frame the location of the data packet within each frame may vary however Because of this it is recom mended that double buffering be enabled for ISO OUT endpoints Each time a data packet is received hardware will load the received data packet into the endpoint FIFO...

Page 185: ...ket Instead the entire data packet should be read from the FIFO manually Bit3 DATERR Data Error In ISO mode this bit is set by hardware if a received packet has a CRC or bit stuffing error It is cleared when software clears OPRDY This bit is only valid in ISO mode Bit2 OVRUN Data Overrun This bit is set by hardware when an incoming data packet cannot be loaded into the OUT endpoint FIFO This bit i...

Page 186: ...rs Bits5 0 Unused Read 000000b Write don t care R W R W R W R W R R R R Reset Value DBOEN ISO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USB Address 0x15 Bits7 0 EOCL OUT Endpoint Count Low Byte EOCL holds the lower 8 bits of the 10 bit number of data bytes in the last received packet in the current OUT endpoint FIFO This number is only valid while OPRDY 1 R R R R R R R R Reset Value EOCL 00...

Page 187: ...nt VCRS 1 3 2 0 V Output Impedance ZDRV Driving High Driving Low 38 38 Pull up Resistance RPU Full Speed D Pull up Low Speed D Pull up 1 425 1 5 1 575 k Output Rise Time TR Low Speed Full Speed 75 4 300 20 ns Output Fall Time TF Low Speed Full Speed 75 4 300 20 ns Receiver Differential Input Sensitivity VDI D D 0 2 V Differential Input Common Mode Range VCM 0 8 2 5 V Input Leakage Current IL Pullu...

Page 188: ... master and or slave and may function on a bus with multiple mas ters The SMBus provides control of SDA serial data SCL serial clock generation and synchronization arbitration logic and START STOP control and generation Three SFRs are associated with the SMBus SMB0CF configures the SMBus SMB0CN controls the status of the SMBus and SMB0DAT is the data register used for both transmitting and receivi...

Page 189: ...al SMBus Configuration 17 3 SMBus Operation Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave ...

Page 190: ...ee the bus Figure 17 3 illustrates a typical SMBus transaction Figure 17 3 SMBus Transaction 17 3 1 Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see Section 17 3 4 SCL High SMBus Free Timeout on page 191 In the event that two or more devices attempt to begin a transfer at the...

Page 191: ...n the SMBFTE bit in SMB0CF is set the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods If the SMBus is waiting to generate a Master START the START will be generated following this timeout Note that a clock source is required for free timeout detection even in a slave only implementation 17 4 Using the SMBus The SMBus can operate in both Master and...

Page 192: ...ion of the current transfer The SMBCS1 0 bits select the SMBus clock source which is used only when operating as a master or when the Free Timeout detection is enabled When operating as a master overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 17 1 Note that the selected clock source may be shared by other peripherals so long as the ti...

Page 193: ...ary when SYSCLK is above 10 MHz With the SMBTOE bit set Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts see Section 17 3 3 SCL Low Timeout on page 191 The SMBus interface will force Timer 3 to reload while SCL is high and allow Timer 3 to count when SCL is low The Timer 3 interrupt service rou tine should be used to reset SMBus communication by disabling an...

Page 194: ...s disabled 1 SDA Extended Setup and Hold Times enabled Bit3 SMBTOE SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low Timer 3 should be programmed to generate interrupts at 25 ms and the Timer 3 interrupt service routine should reset SMBus communication Bi...

Page 195: ... indicates the value received on the last ACK cycle ACKRQ is set each time a byte is received indicating that an outgoing ACK value is needed When ACKRQ is set software should write the desired outgoing value to the ACK bit before clearing SI A NACK will be generated if software does not write the ACK bit before clearing SI SDA will reflect the defined ACK value immediately following a write to th...

Page 196: ...ndition is transmitted followed by a START condition Read 0 No Stop condition detected 1 Stop condition detected if in Slave Mode or pending if in Master Mode Bit3 ACKRQ SMBus Acknowledge Request This read only bit is set to logic 1 when the SMBus has received a byte and needs the ACK bit to be written with the correct ACK response value Bit2 ARBLOST SMBus Arbitration Lost Indicator This read only...

Page 197: ...t due to a detected STOP A pending STOP is generated ACKRQ A byte has been received and an ACK response value is needed After each ACK cycle ARBLOST A repeated START is detected as a MASTER when STA is low unwanted repeated START SCL is sensed low while attempting to gener ate a STOP or repeated START condition SDA is sensed low while transmitting a 1 excluding ACK bits Each time SI is cleared ACK...

Page 198: ...e interrupt is generated before the ACK cycle when operat ing as a receiver and after the ACK cycle when operating as a transmitter 17 5 1 Master Transmitter Mode Serial data is transmitted on SDA while the serial clock is output on SCL The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case t...

Page 199: ...9 A B C D Figure 17 5 Typical Master Transmitter Sequence A A A S W P Data Byte Data Byte SLA S START P STOP A ACK W WRITE SLA Slave Address Received by SMBus Interface Transmitted by SMBus Interface Interrupt Interrupt Interrupt Interrupt ...

Page 200: ...cknowledge value Note writing a 1 to the ACK bit gen erates an ACK writing a 0 generates a NACK Software should write a 0 to the ACK bit after the last byte is received to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver Figur...

Page 201: ...detected If the received slave address is acknowledged zero or more data bytes are received Software must write the ACK bit after each received byte to ACK or NACK the received byte The interface exits Slave Receiver Mode after receiving a STOP Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver Figure 17 7 shows a typical Slave Receiv...

Page 202: ...n to before SI is cleared Note an error condition may be gener ated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode The interface exits Slave Transmitter Mode after receiving a STOP Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt Figure 17 8 shows a typical Slave Transmitter sequence Two tr...

Page 203: ...AT 0 0 X End transfer with STOP 0 1 X End transfer with STOP and start another transfer 1 1 X Send repeated START 1 0 X Switch to Master Receiver Mode clear SI without writ ing new data to SMB0DAT 0 0 X Master Receiver 1000 1 0 X A master data byte was received ACK requested Acknowledge received byte Read SMB0DAT 0 0 1 Send NACK to indicate last byte and send STOP 0 1 0 Send NACK to indicate last ...

Page 204: ...acknowledge received address 0 0 0 Reschedule failed transfer do not acknowledge received address 1 0 0 0010 0 1 X Lost arbitration while attempting a repeated START Abort failed transfer 0 0 X Reschedule failed transfer 1 0 X 0001 1 1 X Lost arbitration while attempting a STOP No action required transfer complete aborted 0 0 0 0 0 X A STOP was detected while addressed as a Slave Transmitter or Sl...

Page 205: ... buffered Receive register it is not possible to read data from the Transmit register With UART0 interrupts enabled an interrupt is generated each time a transmit is completed TI0 is set in SCON0 or a data byte has been received RI0 is set in SCON0 The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software a...

Page 206: ...verflows will occur at two times the desired UART baud rate frequency Note that Timer 1 may be clocked by one of six sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 the external oscillator clock 8 or an exter nal input T1 For any given Timer 1 clock source the UART0 baud rate is determined by Equation 18 1 Equation 18 1 UART0 Baud Rate Where T1CLK is the frequency of the clock supplied to Timer 1 and ...

Page 207: ...0 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if the following conditions are met RI0 must be logic 0 and if MCE0 is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits are lost If these conditions are...

Page 208: ...tions 9 Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic...

Page 209: ...Rev 1 3 209 C8051F340 1 2 3 4 5 6 7 8 9 A B C D Figure 18 6 UART Multi Processor Mode Interconnect Diagram Master Device Slave Device TX RX RX TX Slave Device RX TX Slave Device RX TX V ...

Page 210: ...ll be assigned to the ninth transmission bit in 9 bit UART Mode It is not used in 8 bit UART Mode Set or cleared by software as required Bit2 RB80 Ninth Receive Bit RB80 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 Bit1 TI0 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART0 after the 8th bit in 8 bit U...

Page 211: ...sters a transmit shift register and a receive latch register When data is written to SBUF0 it goes to the transmit shift register and is held for serial transmis sion Writing a byte to SBUF0 initiates the transmission A read of SBUF0 returns the con tents of the receive latch R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x99 ...

Page 212: ...16 9984 SYSCLK 48 10 0 0x98 SYSCLK 24 MHz 230400 230769 0 16 104 SYSCLK XX 1 0xCC 115200 115385 0 16 208 SYSCLK XX 1 0x98 57600 57692 0 16 416 SYSCLK XX 1 0x30 28800 28846 0 16 832 SYSCLK 4 01 0 0x98 14400 14423 0 16 1664 SYSCLK 4 01 0 0x30 9600 9615 0 16 2496 SYSCLK 12 00 0 0x98 2400 2404 0 16 9984 SYSCLK 48 10 0 0x98 1200 1202 0 16 19968 SYSCLK 48 10 0 0x30 SYSCLK 48 MHz 230400 230769 0 16 208 S...

Page 213: ...ding Register Reads of SBUF1 always access the first byte of the Receive FIFO it is not possible to read data from the Transmit Holding Register With UART1 interrupts enabled an interrupt is generated each time a transmit is completed TI1 is set in SCON1 or a data byte has been received RI1 is set in SCON1 The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt ...

Page 214: ...ate for UART1 is defined in Equation 19 1 Equation 19 1 UART1 Baud Rate A quick reference for typical baud rates and system clock frequencies is given in Table 19 1 Table 19 1 Baud Rate Generator Settings for Standard Baud Rates Target Baud Rate bps Actual Baud Rate bps Baud Rate Error Oscillator Divide Factor SB1PS 1 0 Prescaler Bits Reload Value in SBRLH1 SBRLL1 SYSCLK 12 MHz 230400 230769 0 16 ...

Page 215: ...ured using the SMOD1 register shown in SFR Definition 19 2 Figure 19 2 shows the timing for a UART1 transaction without parity or an extra bit enabled Figure 19 3 shows the timing for a UART1 transaction with parity enabled PE1 1 Figure 19 4 is an example of a UART1 transaction when the extra bit is enabled XBE1 1 Note that the extra bit feature is not available when parity is enabled and the seco...

Page 216: ...he Transmit Holding Register until the current transmission is complete The TI1 Transmit Interrupt Flag SCON1 1 will be set at the end of any transmission the beginning of the stop bit time If enabled an interrupt will occur when TI1 is set If the extra bit function is enabled XBE1 1 and the parity function is disabled PE1 0 the value of the TBX1 SCON1 3 bit will be sent in the extra bit position ...

Page 217: ...ore slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its extra bit is logic 1 in a data byte the extra bit is always set to logic 0 Setting the MCE1 bit SMOD1 7 of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the extra bit is logic 1 RBX1 1 signifying an address b...

Page 218: ...it3 TBX1 Extra Transmission Bit The logic level of this bit will be assigned to the extra transmission bit when XBE1 is set to 1 This bit is not used when Parity is enabled Bit2 RBX1 Extra Receive Bit RBX1 is assigned the value of the extra bit when XBE1 is set to 1 If XBE1 is cleared to 0 RBX1 will be assigned the logic level of the first stop bit This bit is not valid when Parity is enabled Bit1...

Page 219: ...ing The parity type is selected by bits S1PT1 0 when parity is enabled 0 Hardware parity is disabled 1 Hardware parity is enabled Bits3 2 S1DL 1 0 Data Length 00 5 bit data 01 6 bit data 10 7 bit data 11 8 bit data Bit1 XBE1 Extra Bit Enable When enabled the value of TBX1 will be appended to the data field 0 Extra Bit Disabled 1 Extra Bit Enabled Bit0 SBL1 Stop Bit Length 0 Short Stop bit is activ...

Page 220: ...FIFO When read the oldest byte in the receive FIFO is returned and removed from the FIFO Up to three bytes may be held in the FIFO If there are additional bytes available in the FIFO the RI1 bit will remain at logic 1 even after being cleared by software R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xD3 Bit7 RESERVED Read 0b Must write 0b...

Page 221: ...te Bits7 0 SBRLH1 7 0 High Byte of reload value for UART1 Baud Rate Generator R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xB5 Bits7 0 SBRLL1 7 0 Low Byte of reload value for UART1 Baud Rate Generator R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xB4 ...

Page 222: ...re than one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional gen eral purpose port I O pins can be used to select multiple slave devices in master mode Figure 20 1 SPI Block Diagram SFR Bus Data Path Control SFR Bus Write SPI0DAT Receive Data Buffer SPI0DAT 0 1 2 3 4 5 6 7 Shift Register SPI CO...

Page 223: ...er The SCK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 20 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register There are three possible modes that can be selected with these bits 1 NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode SPI0 operates in 3 wire mode an...

Page 224: ...ulti master mode is active when NSSMD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 1 In this mode NSS is an input to the device and is used to disable the master SPI0 when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPI0CFG 6 and SPIEN SPI0CN 0 are set to 0 to disable the SPI master device and a Mode Fault is generated MODF SPI0CN 5 1 Mode Fault will generate an interrupt if e...

Page 225: ...nd Slave Mode Connection Diagram Figure 20 4 4 Wire Single Master Mode and Slave Mode Connection Diagram Master Device 2 Master Device 1 MOSI MISO SCK MISO MOSI SCK NSS GPIO NSS GPIO Slave Device Master Device MOSI MISO SCK MISO MOSI SCK Slave Device Master Device MOSI MISO SCK MISO MOSI SCK NSS NSS GPIO Slave Device MOSI MISO SCK NSS ...

Page 226: ...active when NSSMD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 0 NSS is not used in this mode and is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode SPI0 must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines whe...

Page 227: ...er the maximum data transfer rate bits sec is one half the system clock frequency or 12 5 MHz whichever is slower When the SPI is configured as a slave the maximum data transfer rate bits sec for full duplex operation is 1 10 the system clock frequency provided that the master issues SCK NSS in 4 wire slave mode and the serial input data synchronously with the slave s system clock If the master is...

Page 228: ... Timing CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI SCK CKPOL 0 CKPHA 0 SCK CKPOL 1 CKPHA 0 SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI ...

Page 229: ...tantaneous value at the NSS pin but rather a de glitched version of the pin input Bit 2 NSSIN NSS Instantaneous Pin Input read only This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched Bit 1 SRMT Shift Register Empty Valid in Slave Mode read only This bit will be set to logic 1 when all data has been transfe...

Page 230: ...interrupt when the receive buf fer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register This bit is not automatically cleared by hardware It must be cleared by software Bits 3 2 NSSMD1 NSSMD0 Slave Select Mode Selects between the following NSS operation modes See Section 20 2 SPI0 Master Mode Operation on page 224 and Sec...

Page 231: ...PI0CKR register for 0 SPI0CKR 255 Example If SYSCLK 2 MHz and SPI0CKR 0x04 R W R W R W R W R W R W R W R W Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xA2 fSCK 2000000 2 4 1 fSCK 200kHz fSCK SYSCLK 2 SPI0CKR 1 Bits 7 0 SPI0DAT SPI0 Transmit and Receive Data The SPI0DAT register is used to transmit and receive SPI0 data Writing d...

Page 232: ...ter Timing CKPHA 0 Figure 20 9 SPI Master Timing CKPHA 1 SCK T MCKH T MCKL MOSI T MIS MISO SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIH SCK T MCKH T MCKL MISO T MIH MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIS ...

Page 233: ...PI Slave Timing CKPHA 1 SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SEZ T SDZ SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SLH T SEZ T SDZ ...

Page 234: ...10 and Figure 20 11 TSE NSS Falling to First SCK Edge 2 x TSYSCLK ns TSD Last SCK Edge to NSS Rising 2 x TSYSCLK ns TSEZ NSS Falling to MISO Valid 4 x TSYSCLK ns TSDZ NSS Rising to MISO High Z 4 x TSYSCLK ns TCKH SCK High Time 5 x TSYSCLK ns TCKL SCK Low Time 5 x TSYSCLK ns TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK ns TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK ns TSOH SCK Shift Edge to M...

Page 235: ...ensure the level is properly sampled 21 1 Timer 0 and Timer 1 Each timer is implemented as a 16 bit register accessed as two separate bytes a low byte TL0 or TL1 and a high byte TH0 or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate status Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register Section 9 3 5 Interrupt Regist...

Page 236: ...rce the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as described above for TL0 and TH0 Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0 The input signal INT1 is used with Timer 1 the INT1 polarity is defined by bit IN1...

Page 237: ...t When in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TR0 bit TCON 4 enables the timer when either GATE0 TMOD 3 is logic 0 or when the input signal INT0 is active as defined by bit IN0PL in register INT01CF see Section 9 3 2 External Interrupts on page 88 for details on the external input signals I...

Page 238: ...nactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode set ting...

Page 239: ...IT1 0 this flag is set to 1 when INT1 is active as defined by bit IN1PL in register INT01CF see SFR Definition 9 13 Bit2 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in the IT01CF register see SFR Definition 9 13 0 INT1 is level triggered 1 INT1 is edge triggered Bit1 IE0 Ex...

Page 240: ...el 1 Timer 0 enabled only when TR0 1 AND INT0 is active as defined by bit IN0PL in register INT01CF see SFR Definition 9 13 Bit2 C T0 Counter Timer Select 0 Timer Function Timer 0 incremented by clock defined by T0M bit CKCON 2 1 Counter Function Timer 0 incremented by high to low transitions on external input pin T0 Bits1 0 T0M1 T0M0 Timer 0 Mode Select These bits select the Timer 0 operation mod...

Page 241: ...ct This bit selects the clock supplied to Timer 2 If Timer 2 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer 0 Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 low byte uses the system clock Bit3 T1M Timer 1 Clock Select This select the clock source supplied to Timer 1 T1M is ignored when C T1 is set to logic 1 0 Tim...

Page 242: ...dress 0x8A Bits 7 0 TL1 Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8B Bits 7 0 TH0 Timer 0 High Byte The TH0 register is the high byte of the 16 bit Timer 0 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x...

Page 243: ...1 16 bit Timer with Auto Reload When T2SPLIT 0 and T2CE 0 Timer 2 operates as a 16 bit timer with auto reload Timer 2 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from 0xFFFF to 0x0000 the 16 bit value in the Timer 2 reload registers TMR2RLH and TMR2RLL is loaded into the Timer 2 register as...

Page 244: ...F to 0x00 the TF2L bit is set when TMR2L overflows from 0xFF to 0x00 When Timer 2 interrupts are enabled an interrupt is generated each time TMR2H over flows If Timer 2 interrupts are enabled and TF2LEN TMR2CN 5 is set an interrupt is generated each time either TMR2L or TMR2H overflows When TF2LEN is enabled software must check the TF2H and TF2L flags to determine the source of the Timer 2 interru...

Page 245: ...scillator against the internal High Frequency Oscillator or an external clock source When T2SPLIT 0 Timer 2 counts up and overflows from 0xFFFF to 0x0000 Each time a capture event is received the contents of the Timer 2 registers TMR2H TMR2L are latched into the Timer 2 Reload registers TMR2RLH TMR2RLL A Timer 2 interrupt is generated if enabled Figure 21 6 Timer 2 Capture Mode T2SPLIT 0 External ...

Page 246: ...Timer 2 Reload registers TMR2RLH and TMR2RLL A Timer 2 interrupt is generated if enabled Figure 21 7 Timer 2 Capture Mode T2SPLIT 1 SYSCLK TCLK 0 1 TR2 External Clock 8 SYSCLK 12 0 1 1 0 TMR2H TMR2RLH TCLK TMR2L TMR2RLL To ADC SMBus To SMBus CKCON T 3 M H T 3 M L S C A 0 S C A 1 T 0 M T 2 M H T 2 M L T 1 M TMR2CN T F 2 H T F 2 L T 2 X C L K T 2 C S S T R 2 T F 2 L E N T 2 C E T 2 S P L I T Capture...

Page 247: ...s of the Timer 2 registers TMR2H and TMR2L are latched into the Timer 2 reload registers TMR2RLH and TMR2RLH and a Timer 2 interrupt is generated if enabled Bit3 T2SPLIT Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with auto reload 0 Timer 2 operates in 16 bit auto reload mode 1 Timer 2 operates as two 8 bit auto reload timers Bit2 TR2 Timer 2 Run Control Thi...

Page 248: ...e TMR2RLH holds the high byte of the reload value for Timer 2 when operating in auto reload mode or the captured value of the TMR2H register in capture mode R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xCB Bits 7 0 TMR2L Timer 2 Low Byte In 16 bit mode the TMR2L register contains the low byte of the 16 bit Timer 2 In 8 bit mode TMR2L con...

Page 249: ...k 21 3 1 16 bit Timer with Auto Reload When T3SPLIT TMR3CN 3 is 0 and T3CE 0 Timer 3 operates as a 16 bit timer with auto reload Timer 3 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from 0xFFFF to 0x0000 the 16 bit value in the Timer 3 reload registers TMR3RLH and TM3RLL is loaded into the T...

Page 250: ... from 0xFF to 0x00 the TF3L bit is set when TMR3L overflows from 0xFF to 0x00 When Timer 3 interrupts are enabled an interrupt is generated each time TMR3H over flows If Timer 3 interrupts are enabled and TF3LEN TMR3CN 5 is set an interrupt is generated each time either TMR3L or TMR3H overflows When TF3LEN is enabled software must check the TF3H and TF3L flags to determine the source of the Timer ...

Page 251: ...lator against the internal High Frequency Oscillator or an external clock source When T3SPLIT 0 Timer 3 counts up and overflows from 0xFFFF to 0x0000 Each time a capture event is received the contents of the Timer 3 registers TMR3H TMR3L are latched into the Timer 3 Reload registers TMR3RLH TMR3RLL A Timer 3 interrupt is generated if enabled Figure 21 10 Timer 3 Capture Mode T3SPLIT 0 External Clo...

Page 252: ...to the Timer 3 Reload registers TMR3RLH and TMR3RLL A Timer 3 interrupt is generated if enabled Figure 21 11 Timer 3 Capture Mode T3SPLIT 1 SYSCLK TCLK 0 1 TR3 External Clock 8 SYSCLK 12 0 1 1 0 TMR3H TMR3RLH TCLK TMR3L TMR3RLL To ADC CKCON T 3 M H T 3 M L S C A 0 S C A 1 T 0 M T 2 M H T 2 M L T 1 M TMR3CN T F 3 H T F 3 L T 3 X C L K T 3 C S S T R 3 T F 3 L E N T 3 C E T 3 S P L I T Capture Enable...

Page 253: ...e a capture event is received the contents of the Timer 3 registers TMR3H and TMR3L are latched into the Timer 3 reload registers TMR3RLH and TMR3RLH and a Timer 3 interrupt is generated if enabled Bit3 T3SPLIT Timer 3 Split Mode Enable When this bit is set Timer 3 operates as two 8 bit timers with auto reload 0 Timer 3 operates in 16 bit auto reload mode 1 Timer 3 operates as two 8 bit auto reloa...

Page 254: ...he TMR3RLH holds the high byte of the reload value for Timer 3 when operating in auto reload mode or the captured value of the TMR3H register when operating in capture mode R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x93 Bits 7 0 TMR3L Timer 3 Low Byte In 16 bit mode the TMR3L register contains the low byte of the 16 bit Timer 3 In 8 bi...

Page 255: ...te independently in one of six modes Edge Triggered Capture Software Timer High Speed Output Fre quency Output 8 Bit PWM or 16 Bit PWM each mode is described in Section 22 2 Capture Compare Modules on page 257 The external oscillator clock option is ideal for real time clock RTC functionality allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the...

Page 256: ...leared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Note PCA0 interrupts must be globally enabled before CF interrupts are recognized PCA0 inter rupts are globally enabled by setting the EA bit IE 7 and the EPCA0 bit in EIE1 to logic 1 Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in I...

Page 257: ...t and the EPCA0 bit to logic 1 See Figure 22 3 for details on the PCA interrupt configuration Figure 22 3 PCA Interrupt Block Diagram Table 22 2 PCA0CPM Register Settings for PCA Capture Compare Modules PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF Operation Mode X X 1 0 0 0 0 X Capture triggered by positive edge on CEXn X X 0 1 0 0 0 X Capture triggered by negative edge on CEXn X X 1 1 0 0 0 X Capture tr...

Page 258: ... and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software If both CAPPn and CAPNn bits are set to logic 1 then the state of the Port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused the capture ...

Page 259: ...leared by software Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 22 5 PCA Software Timer Mode Diagram Match 16 bit ...

Page 260: ... Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Figure 22 6 PCA High Speed Output Mode Diagram Match 16 bit Comparator PCA0H PCA0CPHn Enable PCA0L PCA Timebase PCA0CPLn 0 1 0 0 0 x ENB ENB 0 1 Write to PCA0CPLn Write to PCA0CPHn Reset PC...

Page 261: ...ower byte of the capture compare module is compared to the PCA counter low byte on a match CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn Fre quency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCA0CPMn register Figure 22 7 PCA Frequency Output Mode FCEXn FPCA 2 PCA0CPHn Note A value of 0x00 in the PCA0CPHn register is equal ...

Page 262: ...e PCA0CPHn without software intervention Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8 Bit Pulse Width Modulator mode The duty cycle for 8 Bit PWM Mode is given by Equation 22 2 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to ...

Page 263: ...ze the capture compare register writes The duty cycle for 16 Bit PWM Mode is given by Equation 22 3 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 Equation 22 3 16 Bit PWM Duty Cycle Using Equation 22 3 the l...

Page 264: ...re disabled While the WDT is enabled writes to the CR bit will not change the PCA counter state the counter will run until the WDT is disabled The PCA counter run control CR will read zero if the WDT is enabled but user software has not enabled the PCA counter If a match occurs between PCA0CPH4 and PCA0H while the WDT is enabled a reset will be generated To prevent a WDT reset the WDT may be updat...

Page 265: ...e select cannot be changed while the WDT is enabled The watchdog timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register When WDLCK is set the WDT cannot be disabled until the next system reset If WDLCK is not set the WDT is disabled by clearing the WDTE bit The WDT is enabled following any reset The PCA0 counter clock defaults to the system clock divided by 12 PCA0L defaults to ...

Page 266: ...set by hardware when a match or capture occurs When the CCF3 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit2 CCF2 PCA Module 2 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF2 interrupt is enabled setting this bit ca...

Page 267: ...A Counter Timer Pulse Select These bits select the timebase source for the PCA counter Bit0 ECF PCA Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCA Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCA Counter Timer Overflow interrupt request when CF PCA0CN 7 is set Note When the WDTE bit is set to 1 the PCA0MD register cannot be modified To cha...

Page 268: ...cause the CCFn bit in PCA0MD register to be set to logic 1 0 Disabled 1 Enabled Bit2 TOGn Toggle Function Enable This bit enables disables the toggle function for PCA module n When enabled matches of the PCA counter with a module s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module operates in Frequency Output Mode 0 Disabled ...

Page 269: ...Bit1 Bit0 SFR Address 0xF9 Bits 7 0 PCA0H PCA Counter Timer High Byte The PCA0H register holds the high byte MSB of the 16 bit PCA Counter Timer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xFA PCA0CPLn Address PCA0CPL0 0xFB n 0 PCA0CPL1 0xE9 n 1 PCA0CPL2 0xEB n 2 PCA0CPL3 0xED n 3 PCA0CPL4 0xFD n 4 Bits7 0 PCA0CPLn PCA Capture Module Lo...

Page 270: ...0xFC n 0 PCA0CPH1 0xEA n 1 PCA0CPH2 0xEC n 2 PCA0CPH3 0xEE n 3 PCA0CPH4 0xFE n 4 Bits7 0 PCA0CPHn PCA Capture Module High Byte The PCA0CPHn register holds the high byte MSB of the 16 bit capture module n R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xFC 0xEA 0xEC 0xEE 0xFE ...

Page 271: ...ough the C2 interface as described in the C2 Interface Spec ification C2 Register Definition 23 1 C2ADD C2 Address C2 Register Definition 23 2 DEVICEID C2 Device ID Bits7 0 The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address Description 0x00 Selects the D...

Page 272: ...Flash programming via the C2 interface To enable C2 Flash programming the following codes must be written in order 0x02 0x01 Note that once C2 Flash programming is enabled a system reset must be issued to resume normal operation Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7 0 FPDAT C2 Flash Programming Data Register This register is used to pass Flash commands addresses and da...

Page 273: ...CK RST and C2D P3 0 pins Note that the C2D pin is shared on the 32 pin packages only C8051F342 3 6 7 9 A B In most applications exter nal resistors are required to isolate C2 interface traffic from the user application A typical isolation configu ration is shown in Figure 23 1 Figure 23 1 Typical C2 Pin Sharing The configuration in Figure 23 1 assumes the following 1 The user input b cannot change...

Page 274: ...om 1 10th to 1 20th of the system clock in Section 17 SMBus on page 205 Corrected the descriptions for the following states and the corresponding typical response options in Table 17 4 SMBus Status Decoding on page 221 Slave Transmitter Status Vector 0101 Slave Receiver Status Vector 0001 Corrected the bit location of MSTEN from SPI0CN 6 to SPI0CFG 6 in Section 20 2 SPI0 Master Operation on page 2...

Page 275: ...Rev 1 3 275 C8051F340 1 2 3 4 5 6 7 8 9 A B C D NOTES ...

Page 276: ...ilicon Laboratories assumes no responsibility for the function ing of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the applicatio...

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