C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
46
Rev. 1.3
5.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initi-
ate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins
on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shutdown) when the device
is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX set-
tings are frequently changed, due to the settling time requirements described in
Section “5.3.3. Settling
Time Requirements” on page 47
.
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
AD0TM=1
Track
Convert
Low Power Mode
AD0TM=0
Track or
Convert
Convert
Track
Low Power
or Convert
SAR Clocks
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
SAR Clocks
B. ADC0 Timing for Internal Trigger Source
1
2
3
4
5
6
7
8
9
CNVSTR
(AD0CM[2:0]=100)
AD0TM=1
A. ADC0 Timing for External Trigger Source
SAR Clocks
Track or Convert
Convert
Track
AD0TM=0
Track
Convert
Low Power
Mode
Low Power
or Convert
10
11
13
14
10
11
