C 8 0 5 1 F 3 6 x - D K
6
Rev. 0.3
5. Target Board
The C8051F36x Development Kit includes a target board with a C8051F360 device pre-installed for evaluation and
preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping
using the target board. Refer to Figure 3 for the locations of the various I/O connectors.
P1
96-pin female connector
P2
Power connector (Accepts input from 7 to 15 VDC unregulated power adapter.)
P3
Analog I/O terminal block
P4
USB connector (for CP2102 USB-to-UART bridge)
J1
Power supply header (Selects power from the USB Debug Adapter, P1 Power Adapter, or USB
power if P4 is connected. Only one power option should be selected at one time.)
J2
Port 0 header
J3
Port 1 header
J4
Port 2 header
J5
Port 3 header
J6
Port 4 header
J7
Connects the +3 V supply net to the VDD supply net
J8
Supply signal header
J9
Debug connector for debug adapter interface
J10, J11External crystal port pin enable connectors
J12
Port I/O jumper configuration block
J13
Jumper connection for potentiometer to pin 2.5
J14
Jumper connection for potentiometer source to +3 V
J15
Jumper connection for pin 0.3 to capacitors (used when VREF is internally generated)
J16
Jumper connection for pin 0.4 to resistor/capacitor (used to convert IDAC output to a voltage)
J18
Connects the +3 V supply net to the AV+ supply net
Figure 3. C8051F360 Target Board
P1
P3.0
P3.1
RESET
P4
P2
DEBUG
J9
U3
F360
U1
USB
ACTIVE
D5
PWR
POWER
D3
D4
P3
SILICON LABS
www.silabs.com
J14
+3
VD
J13
P2
.5
PORT_1
J3
PORT_2
J4
PORT_3
J5
PORT_4
J6
PORT_0
J2
J8
J12
SW3.0
TX
P3.3_LED
RX
CTS
RTS
P3.2_LED
SW3.1
P3.0
P0.1
P3.3
P0.2
P3.5
P3.4
P3.2
P3.1
J1
P1_PWR
SE
R_PWR
VB
US
RE
G
_
IN
RE
G
_
IN
RE
G
_
IN
J15
J16
J10
J11
C8051F360 TB
SA-TB52PCB
R10
GND
GND
VDD
VBUS
AV+
+3VD
P0.3
P0.4
VREF
IDAC
P3.2
P3.3
D2
