C8051F500DK
Rev. 0.1
17
P3.2
24
P3.2
GPIO
J4[3]
P3.3
23
P3.3
GPIO
J4[4]
P3.4
22
P3.4
GPIO
J45]
P3.5
21
P3.5
GPIO
J4[6]
P3.6
20
P3.6
GPIO
J4[7]
P3.7
19
P3.7
GPIO
J4[8]
P4.0
18
P4.0
GPIO
J5[1]
P4.1
17
P4.1
GPIO
J5[2]
P4.2
16
P4.2
GPIO
J5[3]
P4.3
15
P4.3
GPIO
J5[4]
P4.4
14
P4.4
GPIO
J5[5]
P4.5
13
P4.5
GPIO
J5[6]
P4.6
10
P4.6
GPIO
J5[7]
P4.7
9
P4.7
GPIO
J5[8]
/RST/C2CK
12
/RST
C2CK
/RST/C2CK
P2[7], P2[5]*
C2D
11
C2D
C2D
P2[4]
VIO
2
VIO
VIO
J24[4], J18[1], TB3[1]
J1-J5[9]
VREGIN
3
VREGIN
VREGIN
J24[2], P2[5]*, TB3[2]
VDD
4
VDD
VDD
TB3[3]
VDDA
5
VDDA
VDDA
TB3[4]
GND
6
GND
GND
J1-J5[10], TB3[6]
GNDA
7
GNDA
VDD
TB3[5]
*Note:
Headers denoted by this symbol are not directly connected to the MCU pin; the connection might be via one or more
headers and/or pin-sharing resistor(s). See board schematic for details.
Table 11. C8051F500 Target Board Pin Assignments and Headers (Continued)
Summary of Contents for C8051F500
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