C8051F530A-DK
Rev. 0.3
11
7.4. Expansion I/O Connectors (J1, J2)
The two Expansion I/O connectors J1 (26 pins) and J2 (28 pins) provide access to all signal pins of the
C8051F530A devices. Pins for V
DD
, GND, 5 V, Reset, Vbat, LIN, 3.3 V and VREFIN are also available. A small
through-hole prototyping area is also provided.
All I/O signals routed to connectors J1 and J2 are also routed to through-hole connection points between J1 and J2
and the prototyping area (see Figure 3 on page 9). Each connection point is labeled indicating the signal available
at the connection point. See Table 2 for a list of pin descriptions for J1 and J2.
7.5. Target Board DEBUG Interface (HDR1, HDR2)
The DEBUG connectors (HDR1 and HDR2) provide access to the DEBUG (C2) pins of the C8051F530A parts.
They are used to connect the USB Debug Adapter to the target board for in-circuit debugging and Flash
programming. Table 3 shows the DEBUG pin definitions.
Table 2. Pin Descriptions for J1 and J2
J1
J2
Pin #
Description
Pin #
Description
Pin #
Description
Pin #
Description
1
P0.0_B
14
P1.5_B
1
P0.0_A
15
P1.6_A
2
P0.1_B
15
P1.6_B
2
P0.1_A
16
P1.7_A
3
P0.2_B
16
P1.7_B
3
P0.2_A
17
+5V
4
P0.3_B
17
+5V
4
P0.3_A
18
RST/C2CLK_A
5
P0.4_B
18
RST/C2CLK_B
5
P0.4_A
19
VBAT
6
P0.5_B
19
VBAT
6
P0.5_A
20
LIN
7
P0.6_B
20
LIN
7
P0.6_A
21
VREFIN
8
P0.7_B
21
NC
8
P0.7_A
22
VREGOUT_A
9
P1.0_B
22
VREGOUT_B
9
P1.0_A
23
+3.3V
10
P1.1_B
23
NC
10
P1.1_A
24
NC
11
P1.2_B
24
NC
11
P1.2_A
25
NC
12
P1.3_B
25
GND
12
P1.3_A
26
NC
13
P1.4_B
26
GND
13
P1.4_A
27
GND
14
P1.5_A
28
GND
Table 3. DEBUG Connector Pin Descriptions
Pin #
Description
1
+3 VD (+3.3 VDC)
2, 3, 9
GND (Ground)
4
C2D
5
RST (Reset)
6
P0.6
7
C2CK
8
Not Connected
10
USB Power
Summary of Contents for C8051F530A
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Page 14: ...C8051F530A DK 14 Rev 0 3 Figure 5 C8051F530A Target Board Schematic 2 of 3 ...
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