Silicon Laboratories C8051F530A, User Manual

C8051F530A-DK

Rev. 0.3

9

7.1.  Target Board Shorting Blocks: Factory Defaults

The C8051F530A target board comes from the factory with pre-installed shorting blocks on many headers.
Figure 3 shows the positions of the factory default shorting blocks.

Figure 3. C8051F530A Target Board

7.2.  System Clock Sources

The C8051F530A device installed on the target board features a calibrated programmable internal oscillator which
is enabled as the system clock source on reset. After reset, the internal oscillator operates at a frequency of
191.4 kHz (±0.5%) by default but may be configured by software to operate at other frequencies. Therefore, in
many applications an external oscillator is not required. However, if you wish to operate the C8051F530A device at
a frequency not available with the internal oscillator, an external crystal may be used. Refer to the C8051F52x/
52xA/53x/53xA data sheet for more information on configuring the system clock source.
The target board is designed to facilitate the installation of external crystals. Install the crystals at the pads marked
Y1 or Y2. Install a 10 M

Ω

 resistor at R17 or R22 and install capacitors at C29 and C30 or C34 and C35 using

values appropriate for the crystals you select. Headers J9, J10, J11, and J12 connect the external crystal pins to
the general purpose I/O headers (J1 and J2).  If the external crystal is in use, these headers should not be
populated. Refer to the C8051F52x/52xA/53x/53xA data sheet for more information on the use of external
oscillators.

P5

P1

P1.4_A

P1.4_B

U3

U1

U2

SILICON LABORATORIES

C8051F530A TB

T1

T2

J4

P1

.7

_A

J3

P1

.6

_A

J5

P0

.0

_A

+1

2V

L

IN

G

N

D

GND CH2 CH1 VRefin

DEBUG_B

HDR1

Re

set

_B

DEBUG_A

H

DR2

Rese

t_A

HDR3

“B” Side

“A” Side

J13

J14

J8

J6

HDR4

J12
J11

J10

J9

PWR

USB ACTIVE

P1.3_A

P1.3_B

J1

J2

D2

R32

D1

D3

D4

U5

TB1

TB

2

Pin 1

Pin 1

Pin 1

Pin 1

Pin 1

Pin 1