C 8 0 5 1 F 8 0 0 - D K
12
Rev. 0.2
7.8. Analog I/O, Voltage and Ground Reference Options (TB1, J5, J10)
Several of the C8051F800 target device’s port pins are connected to the TB1 terminal block. Refer to Table 4 for
the TB1 terminal block connections. The J5 header connects the MCU VREF pin (P0.0) to the VREF bypass
capacitors C18 and C19, and also to TB1 pin 6 for an optional external VREF input. The J10 header connects P0.1
to GND, and is useful if the P0.1/AGND option is enabled via the REF0CN register in the C8051F800. Refer to the
C8051F80x-83x data sheet for more information on configuring the voltage and ground reference options.
7.9. C2 Pin Sharing
On the C8051F800, the debug pins C2CK and C2D are shared with the pins RST and P2.0 respectively. The target
board includes the resistors necessary to enable pin sharing which allow the RST and P2.0 pins to be used
normally while simultaneously debugging the device. See Application Note “AN124: Pin Sharing Techniques for the
C2 Interface” at
for more information regarding pin sharing.
Table 4. TB1 Terminal Block Pin Descriptions
Pin #
Description
1
P0.6/CNVSTR
2
P1.0
3
P1.1
4
P0.1/AGND
5
GND (Ground)
6
P0.0/VREF (Voltage Reference)
