Silicon Laboratories C8051F90 Series, User Manual

C80 51 F 91 x/9 0x

Rev. 0.2

15

5.5.  Switches and LEDs (J1, J5, J8, J15, J16)

Three push-button switches are provided on the target board. Switch SW1 (RESET) is connected to the reset pin
of the C8051F912. Pressing SW1 puts the device into its hardware-reset state. Switches SW2 (P0.2) and SW3
(P0.3) are connected to the C8051F912’s general purpose I/O (GPIO) pins through headers. Pressing SW2 or
SW3 generates a logic low signal on the port pin. Remove the shorting block from the header (J8) to disconnect the
switches from the port pins. The port pin signal is also routed to pins on the J2 and P1 I/O connectors. See Table 1 
for the port pins and headers corresponding to each switch.

Two touch sensitive (contactless) switches are provided on the target board. The operation of these switches
require appropriate firmware running on the C8051F912 MCU that can sense the state of the switch.

Five power LEDs are provided on the target board to serve as indicators. Each of the two regulators has a red LED
used to indicate the presence of power at the output of the regulator. A red USB Power LED turns on when a USB
cable is plugged into the USB connector P3. One power LED is also added to each of the two primary supply nets
powering the MCU (VDD/DC+ and VBAT). The LEDs connected to the supply nets may be disabled by removing
the shorting blocks from J1 and J5.

Two LEDs are connected to GPIO pins P1.5 and P1.6 for use by application software. See Table 1 for the port pins
and headers corresponding to each LED.

A potentiometer (R15) is also provided on the target board for generating analog signals. Place a shorting block on
J16 to connect the wiper to P0.6/CNVSTR. The header J15 allows the negative terminal of the potentiometer to be
tied to GND or to P1.4. When tied to GND, the potentiometer is always enabled and will draw a measurable
amount of supply current. When tied to P1.4, it only draws current when P1.4 is driving a logic 0 and draws no
current when P1.4 is driving a logic 1. 

Table 1. Target Board I/O Descriptions

Description

I/O

Header(s)

SW1

Reset

none

SW2

P0.2

J8[5–6]

SW3

P0.3

J8[7–8]

P1.0 (Touch Sense Switch)

P1.0

none

P1.1 (Touch Sense Switch)

P1.1

none

Red LED (P1.5)

P1.5

J8[1–2]

Yellow LED (P1.6)

P1.6

J8[3–4]

Red LED (VDD/DC+)

VDD/DC+ Supply Net

J5

Red LED (VBAT)

VBAT Supply Net

J1

Red LED (USB Power)

USB VBUS

none

Red LED (+1 VD Power)

+1 VD Regulator Output

none

Red LED (+3 VD Power)

+3 VD Regulator Output

none

Potentiometer (R15) 

P0.6/P1.4 

J15, J16