Silicon Laboratories C8051F92 Series, User Manual

C 8 0 5 1 F 9 3 x / 9 2 x

18

Rev 0.7

5.7.  Target Board DEBUG Interface (J9)

The DEBUG connector J9 provides access to the DEBUG (C2) pins of the C8051F930. It is used to connect the
Serial Adapter or the USB Debug Adapter to the target board for in-circuit debugging and Flash programming.
Table 3 shows the DEBUG pin definitions.

5.8.  Serial Interface (J12)

A USB-to-UART bridge circuit (U3) and USB connector (P3) are provided on the target board to facilitate serial
connections to UART0 of the C8051F930. The Silicon Labs CP2103 (U3) USB-to-UART bridge provides data
connectivity between the C8051F930 and the PC via a USB port. The VIO power supply and TX, RX, RTS and
CTS signals of UART0 may be connected to the CP2103 by installing shorting blocks on header J12. The shorting
block positions for connecting each of these signals to the CP2103 are listed in Table 4. To use this interface, the
USB-to-UART device drivers should be installed as described in Section 4.4. "CP210x USB to UART VCP Driver
Installation‚" on page 7.

5.9.  Analog I/O (H1)

Several of the C8051F930 target device’s port pins are connected to the H1 terminal block. Refer to Table 5 for the
H1 terminal block connections.

Table 3. DEBUG Connector Pin Descriptions

Pin #

Description

1

+3 VD  (+3.3 VDC)

2, 3, 9

GND (Ground)

4

P2.7/C2D

5

RST (Reset)

6

P2.7

7

RST/C2CK

8

Not Connected

10

USB Power (+5 VDC from J9)

Table 4. Serial Interface Header (J12) Description

Header Pins UART0 Pin Description

J12[9–10]

CP2103_VIO (VDD/DC+)

J12[7–8]

TX_MCU (P0.5)

J12[5–6]

RX_MCU (P0.4)

J12[3–4]

RTS (P0.6)

J12[1–2]

CTS (P0.7)

Table 5. H1 Terminal Block Pin Descriptions

Pin #

Description

1

P0.6/CNVSTR

2

P0.7/IREF0

3

GND (Ground)

4

P0.0/V

REF

 (Voltage Reference)