Silicon Laboratories C8051F92 Series, User Manual

C 8 0 5 1 F 9 3 x / 9 2 x

22

Rev 0.7

11.  

When the missing clock detector is enabled, why does the MCU reset if I switch from the default 

system clock (Low Power Oscillator divided by 8) to smaRTClock divided by 1?

Background:

—The missing clock detector will trigger a reset if the system clock period exceeds 100 µs.
—Switchover between clock sources occurs in 1 clock cycle of the slowest clock.
—Changing the clock divide value requires up to 128 cycles of the undivided clock source.

Since the 

clock source

 change occurs in a single cycle and the 

clock divide

 change can take up to 128 

cycles, the system clock will be set to the 

new clock source divided by the old divide value

 for a brief 

period of time. In this example, the actual system clock will be 4.096 kHz for up to 128 cycles of the 
undivided clock source. This causes the missing clock detector to time out and reset the MCU.

The proper way of changing the system clock when both the 

clock source 

and the 

clock divide 

value are 

being changed is as follows:

If switching from a fast “undivided” clock to a slower “undivided” clock:

a. Change the 

clock divide

 value.

b. Poll for CLKRDY > 1.

c. Change the 

clock source

.

If switching from a fast “undivided” clock to a slower “undivided” clock:

d. Change the 

clock source

.

e. Change the 

clock divide

 value.

f. Poll for CLKRDY > 1.

12.  Why is the MCU prematurely released from reset when using a wall supply with a slow rise time?

The maximum VDD Ramp Time is specified at 3 ms. If the power supply ramp takes longer than 3 ms to 
reach 0.9 V, then the device may be released from reset before the supply has reached the minimum 
operating voltage. The slow ramp time (>3 ms) can occur when using a bench power supply that does not 
have an output enable switch.