Silicon Laboratories C8051F930, User Manual

Page 1: ...DB Figure 2 MSC DBLB2 Not Included Testing Platform for controlled Lab Tests Loadboard Both boards come with the Silicon Labs standard 40 pin socket for connecting standard EZRadio and EZRadioPRO evaluation testcards such as the Si4432 DKDB1 The onboard C8051F930 comes preloaded with sample firmware to demonstrate a packet based wireless link between two systems The MSC DBSB8 C8051F9xx software de...

Page 2: ...SDBC DK3 UG 2 Rev 0 3 ...

Page 3: ...ntenna Diversity and Where to Use It 16 7 1 5 Packet Length 17 7 1 6 Max Packets 18 7 1 7 Screen 5 The Ready Screen 18 7 1 8 Running the Demonstration 20 7 2 Lab Mode 22 7 2 1 Transmitter Evaluation Setup 25 7 2 2 Receiver Evaluation Setup 25 7 2 3 Transmitter Measurements 25 7 2 4 Results CW Tests 28 7 2 5 PN9 Measurement 29 7 2 6 Results PN9 Tests 31 7 2 7 Receiver Measurements 32 7 2 8 Results ...

Page 4: ...54 10 1 1 RF Packet Received 54 10 1 2 RFTransmit 54 10 2 Si4432 Header File 55 10 3 Si4432 Source File 59 11 C8051 67 11 1 C8051 Header File 67 11 2 C8051 Source File 70 12 Troubleshooting 73 Document Change List 74 Contact Information 76 ...

Page 5: ... should be powered by a standard 9 V ac or 9 12 V dc adapter 2 2 External PSU In this mode the board can be powered via the direct dc supply connector by an external PSU Any supply voltage can be used in the 3 3 4 V range Polarity is marked on the PCB 2 3 Powered by USB Port In this mode the board can be powered via the USB connector Note When using the white LED Flash option it is recommend to us...

Page 6: ...0 3 3 System Introduction IA MSC DBSB8 ICD Connector Figure 3 Debug Connector Emulator and Programmer Interface Table 1 Debug Connector Pin Description 1 VDD 3 3 V 2 GND 3 GND 4 P2 7 5 RESET 6 P2 7 7 RST C2CK 8 9 GND 10 ...

Page 7: ... 5 J6 3 RF_NSEL 25 J8 1 6 J7 3 26 EBID port SPI_MOSI 7 J6 4 27 GND 8 J7 4 28 EBID port SPI_MISO 9 J6 5 29 J8 2 10 J7 5 30 EBID port SPI_SCK 11 J6 6 31 GND 12 J7 6 RF_NIRQ 32 EBID port EE_NSEL 13 J6 7 PWRDN 33 J8 3 14 J7 7 RF_NIRQ 34 J15 3 15 J6 8 GPIO 35 GND 16 J7 8 SPI_MISO 36 J15 4 17 VDD 3 3 V 37 J8 4 18 VDD 3 3 V 38 J15 5 19 VDD 3 3 V 39 GND 20 VDD 3 3 V 40 J15 6 ...

Page 8: ...SDBC DK3 UG 8 Rev 0 3 4 System Introduction Schematic MSC DBSB8 Figure 4 MSC DBSB8 Schematic 1 of 2 ...

Page 9: ...SDBC DK3 UG Rev 0 3 9 Figure 5 MSC DBSB8 Schematic 2 of 2 ...

Page 10: ...SDBC DK3 UG 10 Rev 0 3 5 Typical Testboard Schematic Si443x Testcard Figure 6 Si443x Testcard Schematic ...

Page 11: ...s that are typically plugged into the MSC DBLB2 Loadboard when engineers are performing RF tests on the radio ICs can also be plugged into the 40pin socket on the Software Development Board SDB as demonstrated below Figure 7 Software Development Board MSC DBSB8 with a Standard Silicon Labs Testcard Installed ...

Page 12: ...e use of acknowledgements and retries In the demonstration software such techniques are NOT implemented such that system designers can understand range limitations in various environments allowing them to design robust protocols into their designs In order to use this demonstration users should start the demo then move the two boards apart until packet errors can be seen to start appearing and the...

Page 13: ...he mode of operation Figure 10 Operating Modes Figure 11 Screen 1 Demonstration Mode Since the SDB s firmware recognized the Si4432 test card inserted into the 40 pin socket the appropriate modes of operation are presented on the menu system in this case TRx Transceiver It is possible however to operate a transceiver in a RX Receive or TX Transmit mode also so menu features allow users to override...

Page 14: ...oards Press the GO button 7 1 3 Screen 3 Setting up Further RF Parameters On this screen their may be a difference with respect to the screen shot available depending on which card is plugged into the SDB On startup the firmware in the SDB interrogates the testcard to ensure relevant options are made available to the user and irrelevant options are disabled Three different testcards are supplied w...

Page 15: ... 15 Figure 15 Antenna Diversity Testcard Figure 16 Split TX and RX Testcard Rx Left SMA Tx Right SMA for Use with Coaxial Cable and RF Test Equipment for Scientific RF Evaluation Figure 17 Single Ended TX and RX Testcard ...

Page 16: ... the signal which can cause problems for the receiver Antenna diversity assists the receiver by allowing it to see the signal from two slightly different positions through the use of multiple antennas Studies have shown that antenna diversity in both indoor and urban environments can recover 8 10 dB of the link budget that is usually lost to the environment when receivers use only single antenna i...

Page 17: ...e second and vice versa This will allow the two SDB boards to communicate with each other The ID is considered the address 7 1 5 Packet Length The node parameters screen also allows users to adjust the packet length so that they may 1 Perform head to head comparisons with competitive radios 2 Learn the effects of packet length with respect to data rate and robustness Many things affect the robustn...

Page 18: ...environments is recommended the Max Packets menu option allows designers to select the number of packets used to generate a Packet Error Rate PER result A large number of packets 1000 9999 allows for a good averaged result but can take time particularly at low data rates A small number of packets 100 allows for a quick environmental assessment to be made prior to an exhaustive test 7 1 6 1 Example...

Page 19: ...0 MHz Using the ready screen we can see that there is an error on the split TX RX board in that it is configured with a selfID of 054 this does not match the DestinationID on the antenna diversity board From the ready screen we can update the antenna diversity board accordingly To do this we can press PB3 or PB4 which are highlighted as SETTINGS where we can re run the setting accordingly Once the...

Page 20: ...verage can be generated To run the demonstration place the antenna diversity SDB in a fixed location This unit will act as the base unit On the mobile unit the unit with the split TX and RX press TX ON and walk away from the base unit until the PER settles around 5 7 When the PER has settled and all 1000 packets are sent press the CLEAR button and run the test again but avoid being to close to the...

Page 21: ...SDBC DK3 UG Rev 0 3 21 Figure 24 Active Antenna and RSSI Indications ...

Page 22: ...tions such as Transmitter Evaluation Output power Spectrum Analysis Receiver Evaluation BER Sensitivity PER Sensitivity Receiver parameters Automatic Frequency Control Blocking Selectivity Using lab mode users can independently evaluate transmit and receive performance It is intended that the split Tx Rx testcard 4432 DKDB1 as supplied is used in lab mode Figure 25 4432 DKDB1 Split TX RX Antenna C...

Page 23: ...SDBC DK3 UG Rev 0 3 23 Figure 26 Lab Equipment Connection Diagram ...

Page 24: ...SDBC DK3 UG 24 Rev 0 3 Figure 27 Test Card Connection Diagram Figure 28 SDB Connection Diagram ...

Page 25: ...ern option The 4432 DKDB1 testcard also provides access to the radio s GPIO which can be used as test points for the radios internal signals see test card connection diagram Two modes are typically used during evaluations 1 Direct Mode In this mode data is continuously sent via a source such as a PN9 generator 2 Packet Mode In this mode the data source is customized in a defined packet structure T...

Page 26: ...1 Ensure Lab Mode is selected as the operating function 2 Select CW 3 Press GO to move on from this screen Figure 30 Setup Screen 2 of 4 1 Select the appropriate frequency When evaluating with CW data rate and modulation have no effect 2 Press GO to move on from this screen ...

Page 27: ...screen shots than those shown Users must turn off the diversity function by selecting antenna 1 and connecting to the appropriate antenna connector using 50 coaxial cable Figure 32 Setup Screen 4 of 4 1 Parameters on setup screen 4 are not relevant to CW evaluations Silicon Labs recommends leaving them at their default values 2 Press GO to move on from this screen In Figure 33 the runtime screen w...

Page 28: ...equency Offset at Transmitter Output 1 Set the center frequency of spectrum analyzer to the frequency under test 2 Set span to 100 kHz 3 Measure the frequency offset between the expected frequency as selected in the menu and the actual TX output frequency Figure 35 Typical Spectrum Plot Using a Silicon Labs Branded Testcard In Figure 35 it can be seen that the frequency error is less than 1 kHz Si...

Page 29: ... to the desired span typically from 100 Hz to 10 MHz span Figure 36 Typical Phase Noise Plot at 917 Mhz 7 2 5 PN9 Measurement Using the PN9 Lab Mode users may evaluate the following 1 Tx output spectrum 2 Transmitter spectral mask 7 2 5 1 Test Method Figure 37 Setup Screen 1 of 4 1 Ensure Lab Mode is selected as the operating function 2 Select PN9 3 Press GO to move on from this screen ...

Page 30: ...O to move on from this screen Figure 39 Setup Screen 3 of 4 1 Select the desired output power 2 Press GO to move on from this screen Figure 40 Setup Screen 4 of 4 1 Parameters in Figure 40 are not relevant to PN9 evaluations Silicon Labs recommends leaving them at their default values 2 Press GO to move on from this screen ...

Page 31: ... 1 TX Output Spectrum 1 Set the center frequency of spectrum analyzer to the frequency under test 2 Set span to 500 kHz and observe the TX spectrum 7 2 6 2 Evaluation of TX Spectral Mask Using the PN9 mode users can observe the TX spectrum to evaluate FCC ETSI compliance Figure 42 Spectrum Plot Demonstrating 40K Data Rate 40K Deviation GFSK Modulation ...

Page 32: ...est Method 1 Set frequency modulation type data rate and deviation parameters on the RF signal generator 2 Select the desired data source for the RF generator eg PN9 3 Connect the receiver s input to the signal generator s output Figure 43 Setup Screen 1 of 4 1 Ensure Function is set to Lab 2 Set Lab Mode to BER 3 Press GO to move on from this screen Figure 44 Setup Screen 2 of 4 1 Selections here...

Page 33: ... their default values 2 Press GO to move on from this screen Figure 46 Setup Screen 4 of 4 1 Parameters on setup screen 4 are not relevant to BER evaluations Silicon Labs recommends leaving them at their default values 2 Press GO to move on from this screen Figure 47 Runtime Screen In the Figure 47 the runtime screen will summarize the current valid settings ...

Page 34: ... a transmitter and the bottom trace is the data received on the GPIO pin Please note that there is an expected shift caused by a delay between the data at the transmitter and the data received by the receiver Figure 48 TX Data Sent and Received 7 2 8 2 Other Receiver Measurements Using the test setup described above users may also perform Automatic Frequency Control AFC Blocking and Selectivity te...

Page 35: ... Program a predefined packet into the generator using the format preamble sync_word 2DD4H data CRC 3 Set the signal generator to external single trigger mode 4 The software development board SDB generates a trigger on test point P1 4 this should be connected to the RF signal generator s external trigger input The P1 4 pin will enable the signal generator to send one packet for each trigger Figure ...

Page 36: ...ed by the receiver using the Max Packets field The appropriate number of triggers will be sent by the SDB according to this setting 3 Press GO to move on from this screen Figure 53 Setup Screen 5 of 5 1 Press Start to commence packet error rate evaluation This will start generating pulses on P1 4 that are used to trigger the RF signal generator The RF generator will send one packet for every exter...

Page 37: ...ovided on P1 4 of the SDB the middle trace shows the received data and the bottom trace shows the transmitted data from the RF signal generator In the plot we can see the receiver is turned on before the packet arrived Once the valid packet is received the radio will return to tune mode The radio will switch to receive mode prior to sending the next trigger This is repeated for the value set in Ma...

Page 38: ...river needs to be installed on the PC When the MSC DBSB8 is connected you may be prompted to install the Virtual COM port driver This driver can be found on the WDS CDROM The Virtual COM port settings of the software development board are as follows Data rate is 19 2 kbps 1 stop bit No parity bit No handshake If USB to virtual serial port driver is installed correctly when the software development...

Page 39: ... 2 Packet Structure The packet structure used by this demonstration is very simple but is not much different than a typical packet found in many RF applications today Figure 57 Packet Format Defined in the Packet Error Rate Test ...

Page 40: ...in software development the following chapter maybe used to illustrate basic code segment to create RF links using the EZRadioPRO platform The code set forth in the following chapter demonstrates a simple push button application and is based upon the EZRadioPRO Si443x transceiver using the C8051F930 microcontroller 8 1 Program Structure Figure 58 Basic Program Structure Block Diagram 1 of 4 Progra...

Page 41: ...Register 0x09 Chip version V2 TX RX offset Set center frequency of operation Register 0x75 0x76 0x77 Configuring GPIOs Register 0x0B 0x0C 0x0D Specific Data Rate and Modem Settings Set up Sync Words 2 3 Register 0x37 0x36 Customize Sync Words Using GIPOs Please use EZRadioPRO Register Calculator to configures the RF chip s modem for different predefined data rate deviation and modulation index req...

Page 42: ...shed PB1_PIN 0 No Build packet 1 strcpy packet 0 PAYLOAD Yes RFPacketReceived packet 0 length Return RF_NO_PACKET nIRQ interrupt occurred Read out Interrupt Status Registers Read Registers 0x03 0x04 packet received interrupt CRC ERROR interrupt occurred ItStatus1 0x01 0x01 Packet Received interrupt occurred ItStatus1 0x02 0x02 RFTransmit packet 0 length Read Packet Length Information Return RF_CRC...

Page 43: ...es No RF chip in Transmit Mode Set Register 0x07 0x8701 Set Packet Length Information DO a Burst Write to FIFO 64 bytes Enable packet sent interrupt Read out Interrupt Status Registers Set Register 0x3E Write Register 0x7F Write Register 0x7F Read Set Register 0x05 0x8504 Wait for packet sent interrupt While RF_NIRQ_PIN 1 No Packet Sent Sucessful Yes Read Registers 0x03 0x04 ...

Page 44: ...Master SPI enabled SPI1CKR SYSCLK 2 SPI_CLOCK 1 SPI1EN 1 Enable SPI1 module set nSEL pins to high RF_NSEL_PIN 1 RF chip hardware and I O init RF Parameters definition Si4432 h i e define the default radio frequency define FREQ_BAND_SELECT 0x75 frequency band select define NOMINAL_CAR_FREQ1 0xBB default carrier frequency 915 MHz define NOMINAL_CAR_FREQ2 0x80 RF hardware setup and parameters setting...

Page 45: ...SDBC DK3 UG Rev 0 3 45 8 2 Basic Hardware Connections Figure 62 Basic Hardware Connections C 8051F930 Si4432 HW SPI SCK SDI SDO nSEL nIRQ LED 1 LED 2 30MHz ...

Page 46: ...packet s In addition it also polls for a push button event by user If a button is pressed then it ll sends a payload out using the internal FIFO and packet handler features of the EZRadioPRO device before returning to a continuous receive mode 9 1 Flow Chart Main Figure 63 Flow Chart Main Continuous loop in receive mode Main 1 MCU and RF Hardware Init 2 Set RF chip in Idle mode and start continuou...

Page 47: ...oid void delay_ms uint8 delay The real program starts here After power on the first two tasks are the init of the MCU and the software development board The main loop starts after that While 1 means that it is a never ending loop MAIN PROGRAM void main void idata uint8 packet MAX_PAYLOAD_LENGTH idata uint8 length Hw_Init initialize the MCU and the SW Development board RfInitHw DR4800BPS_DEV45KHZ i...

Page 48: ...e system will return to receive mode if PB1_PIN 0 On PB1 a packet send is initiated while PB1_PIN 0 wait for release of the button LED1_PIN 1 blink the LED length 7 send a packet 64 bytes payload strcpy packet 0 PAYLOAD set packet content RFIdle disable receiving RFTransmit packet 0 length start packet transmission LED1_PIN 0 release the LED RFIdle disable transmission RFReceive start continuous r...

Page 49: ... Digital P0 2 Skipped Open Drain Analog P0 3 Skipped Open Drain Analog P0 4 TX0 UART0 Push Pull Digital P0 5 RX0 UART0 Open Drain Digital P0 6 Skipped Open Drain Digital P0 7 Skipped Open Drain Digital P1 0 SCK SPI1 Push Pull Digital P1 1 MISO SPI1 Open Drain Digital P1 2 MOSI SPI1 Push Pull Digital P1 3 Skipped Push Pull Digital P1 4 Skipped Push Pull Digital P1 5 Skipped Push Pull Digital P1 6 S...

Page 50: ...t inputs P0 0xE3 Set P0 inputs P1 0x02 Set P1 inputs P2 0x03 Set P2 inputs default I O port LED1_PIN 0 LED2_PIN 0 LED3_PIN 0 LED4_PIN 0 BLED_PIN 0 LCD_NSEL_PIN 1 LCD_A0_PIN 0 LCD_RESET_PIN 0 Oscillator init external XTAL 16MHz SYSCLK XTAL 2 OSCXCN 0x77 1ms delay for XTAL stabilization for i 0 i 500 i while OSCXCN 0x80 0 CLKSEL 0x01 Initialize SPI SetHwMasterSpi LED1_PIN 1 delay_ms 5 LED2_PIN 1 del...

Page 51: ...N NAME void delay_ms void DESCRIPTION This function generates milliseconds delay INPUT Number of milliseconds RETURN None NOTES None void delay_ms uint8 delay xdata uint8 i xdata uint16 j for i 0 i delay i for j 0 j 8000 j delay 1ms ...

Page 52: ...us to release the pending interrupts 2 SW reset wait for POR interrupt 3 Disable all ITs except Chip Ready ichiprdy 4 Set the non default Si4432 registers Set VCO Set the AGC Set ADC reference voltage to 0 9V Set capacitance bank to adjust for adjust crystal PPM accuracy and TX RX offsets Reset digital testbus disable scan test Select nothing to the Analog Testbus Set center frequency Disable RX T...

Page 53: ...Modulation Mode Control 1 0x70 FDEV Frequency Deviation 0x72 AFC AFC Loop Gear Shift Override 0x1D ChargepumpCT Charge Pump Current Trimming Override 0x58 This table contains the modem parameters for different data rates See the comments for more details code uint8 RfSettings NMBR_OF_SAMPLE_SETTING NMBR_OF_PARAMETER revV2 IFBW COSR CRO2 CRO1 CRO0 CTG1 CTG0 TDR1 TDR0 MMC1 FDEV AFC ChargepumpCT 0x01...

Page 54: ...IFO burst read from register 0x7F 3 Disable receiver Yes If nIRQ goes low 1 Read out Interrupt Status 1 Registers for valid packet bit No RFTransmit 1 Set packet length with register 0x3E 2 Do a Burst Write up to a maximum of 64 bits of data into the TX FIFO using register 0x7F 3 Enable packet sent interrupt with register 0x05 Interrupt Enable 1 Read Interrupt Status Registers 1 2 0x03 and 0x04 Wa...

Page 55: ...fine the default radio frequency define FREQ_BAND_SELECT 0x75 frequency band select define NOMINAL_CAR_FREQ1 0xBB default carrier frequency 915 MHz define NOMINAL_CAR_FREQ2 0x80 packet settings define PREAMBLE_LENGTH 4 4 byte preamble define PD_LENGTH 2 preamble detection threshold in nibbles The max length of the received data packet is defined here in data bytes define MAX_PAYLOAD_LENGTH 64 D E ...

Page 56: ... BBBW 112 8kHz DR100000BPS_DEV50KHZ 7 DR 100kbps Fdev 50kHz BBBW 208kHz DR128000BPS_DEV64KHZ 8 DR 128kbps Fdev 64kHz BBBW 269 3kHz RF_SAMPLE_SETTINGS typedef enum _RF_REG_MAP These settings are for silicon Rev V2 DeviceType 0x00 DeviceVersion 0x01 DeviceStatus 0x02 InterruptStatus1 0x03 InterruptStatus2 0x04 InterruptEnable1 0x05 InterruptEnable2 0x06 OperatingFunctionControl1 0x07 OperatingFuncti...

Page 57: ...1 0x3C TransmitHeader0 0x3D TransmitPacketLength 0x3E CheckHeader3 0x3F CheckHeader2 0x40 CheckHeader1 0x41 CheckHeader0 0x42 HeaderEnable3 0x43 HeaderEnable2 0x44 HeaderEnable1 0x45 HeaderEnable0 0x46 ReceivedHeader3 0x47 ReceivedHeader2 0x48 ReceivedHeader1 0x49 ReceivedHeader0 0x4A ReceivedPacketLength 0x4B AnalogTestBus 0x50 DigitalTestBus 0x51 TXRampControl 0x52 PLLTuneTime 0x53 CalibrationCo...

Page 58: ...3 FrequencyChannelControl 0x74 FrequencyBandSelect 0x75 NominalCarrierFrequency1 0x76 NominalCarrierFrequency0 0x77 FrequencyHoppingChannelSelect 0x79 FrequencyHoppingStepSize 0x7A TXFIFOControl1 0x7C TXFIFOControl2 0x7D RXFIFOControl 0x7E FIFOAccess 0x7F RF_REG_MAP F U N C T I O N P R O T O T Y P E S RF_ENUM RfInitHw U8 data_rate RF_ENUM RFSetRfParameters RF_SAMPLE_SETTINGS setting RF_ENUM RFIdle...

Page 59: ...xa5 0x20 0x48 0x40 0x80 DR 9 6kbps DEV 45kHz BBBW 112 8kHz 0x12 0xc8 0x00 0xa3 0xd7 0x01 0x13 0x51 0xec 0x20 0x13 0x40 0x80 DR 10kbps DEV 12kHz BBBW 41 7kHz 0x13 0x64 0x01 0x47 0xAE 0x04 0x46 0xa3 0xd7 0x20 0x13 0x40 0x80 DR 20kbps DEV 12kHz BBBW 45 2kHz 0x02 0x64 0x01 0x47 0xae 0x05 0x21 0x0A 0x3D 0x00 0x20 0x40 0x80 DR 40kbps DEV 20kHz BBBW 83 2kHz 0x05 0x50 0x01 0x99 0x9A 0x06 0x68 0x0C 0xCD 0x...

Page 60: ...should be able to oscillate the crystal Based on the crystal and PCB capacitance these cap banks can be used to tune the TX RX offset set cap bank SpiRfWriteAddressData REG_WRITE CrystalOscillatorLoadCapacitance 0xD7 reset digital testbus disable scan test SpiRfWriteAddressData REG_WRITE DigitalTestBus 41 0x00 select nothing to the Analog Testbus SpiRfWriteAddressData REG_WRITE AnalogTestBus 0x0B ...

Page 61: ...SDBC DK3 UG Rev 0 3 61 Figure 66 SpiRfWriteAddressData REG_WRITE SyncWord3 0x2D SpiRfWriteAddressData REG_WRITE SyncWord2 0xD4 ...

Page 62: ...O2 to RX State SpiRfWriteAddressData REG_WRITE GPIO1Configuration 0x12 SpiRfWriteAddressData REG_WRITE GPIO2Configuration 0x15 Next define your RF parameters based on application specific data rate deviation receive baseband bandwidth etc set modem and RF parameters according to the selected DATA rate RFSetRfParameters data_rate return RF_OK ...

Page 63: ...set0 RfSettings setting 4 SpiRfWriteAddressData REG_WRITE ClockRecoveryTimingLoopGain1 RfSettings setting 5 SpiRfWriteAddressData REG_WRITE ClockRecoveryTimingLoopGain0 RfSettings setting 6 SpiRfWriteAddressData REG_WRITE TXDataRate1 RfSettings setting 7 SpiRfWriteAddressData REG_WRITE TXDataRate0 RfSettings setting 8 SpiRfWriteAddressData REG_WRITE ModulationModeControl1 RfSettings setting 9 SpiR...

Page 64: ...tatus1 SpiRfReadRegister InterruptStatus1 ItStatus2 SpiRfReadRegister InterruptStatus2 return RF_OK FUNCTION NAME RF_ENUM RFTransmit uint8 packet uint8 length DESCRIPTION Starts packet transmission INPUT MESSAGE structure RETURN RF_OK The packet sent correctly NOTES RF_ENUM RFTransmit uint8 packet uint8 length uint8 temp8 set packet length SpiRfWriteAddressData REG_WRITE TransmitPacketLength lengt...

Page 65: ...n INPUT None RETURN RF_OK The operation was successful NOTES RF_ENUM RFReceive void enable receiver chain SpiRfWriteAddressData REG_WRITE OperatingFunctionControl1 0x05 enable the wanted ITs SpiRfWriteAddressData REG_WRITE InterruptEnable1 0x13 SpiRfWriteAddressData REG_WRITE InterruptEnable2 0x00 read interrupt status registers ItStatus1 SpiRfReadRegister InterruptStatus1 ItStatus2 SpiRfReadRegis...

Page 66: ...f RF_NIRQ_PIN 0 check what caused the interrupt read out IT status register ItStatus1 SpiRfReadRegister InterruptStatus1 ItStatus2 SpiRfReadRegister InterruptStatus2 packet received interrupt occurred if ItStatus1 0x02 0x02 read buffer length SpiRfReadRegister ReceivedPacketLength for i 0 i length i packet SpiRfReadRegister FIFOAccess disable receiver SpiRfWriteAddressData REG_WRITE OperatingFunct...

Page 67: ...SPI port 8 bits length nSEL pin is controlled separately by RF_NSEL_PIN The SpiRfWriteAddressData function sends data through the SPI port 16 length 8 bits address 8 bits data This function controls the nSEL pin The SpiRfWriteAddressData function reads the current value of the register This function controls the nSEL pin 11 1 C8051 Header File FILE C8051 h DESCRIPTION Contains the 8051 specific de...

Page 68: ...6 signed short define uint32 unsigned long define sint32 signed long typedef struct unsigned int bit0 1 unsigned int bit1 1 unsigned int bit2 1 unsigned int bit3 1 unsigned int bit4 1 unsigned int bit5 1 unsigned int bit6 1 unsigned int bit7 1 reg typedef union reg testreg uint8 adat reg_union typedef union reg_union bytes 2 uint16 adat reg16_union D E F I N I T I O N S undef TRUE undef FALSE unde...

Page 69: ... Test card EEPROM SBIT EE_NSEL_PIN SFR_P2 6 LCD SBIT LCD_NSEL_PIN SFR_P2 5 SBIT LCD_A0_PIN SFR_P2 3 SBIT LCD_RESET_PIN SFR_P2 4 SBIT LCD_BL_PIN SFR_P2 7 define SYSCLK 16000000L 2 SYSCLK frequency in Hz define SPI_CLOCK SYSCLK 4 define EnableGlobalIt EA 1 define DisableGlobalIt EA 0 F U N C T I O N P R O T O T Y P E S void SetHwMasterSpi void void SpiWrite uint8 spi_in uint8 SpiReadWrite uint8 spi_...

Page 70: ...n Laboratories Inc http www silabs com include C8051 h FUNCTION NAME void SetHwMasterSpi void DESCRIPTION Initialize the HW SPI port INPUT Data RETURN None NOTES It doesn t control the nSEL pin void SetHwMasterSpi void SPI1CFG 0x40 Master SPI CKPHA 0 CKPOL 0 SPI1CN 0x00 3 wire Single Master SPI enabled SPI1CKR SYSCLK 2 SPI_CLOCK 1 SPI1EN 1 Enable SPI1 module set nSEL pins to high RF_NSEL_PIN 1 ...

Page 71: ... data through the SPI port INPUT Data RETURN Received byte NOTES It doesn t control the nSEL pin uint8 SpiReadWrite uint8 spi_in SPI1DAT spi_in write data into the SPI register while SPIF1 0 wait for sending the data SPIF1 0 clear interrupt flag return SPI1DAT read received bytes FUNCTION NAME void SpiRfWriteAddressData uint8 address uint8 data1 DESCRIPTION Sends 16 length data through the SPI por...

Page 72: ...CRIPTION Read a register of the radio INPUT Address register address RETURN Value of the register NOTES It controls the nSEL pin of the radio uint8 SpiRfReadRegister uint8 address uint8 temp8 RF_NSEL_PIN 0 SpiReadWrite address temp8 SpiReadWrite 0x00 RF_NSEL_PIN 1 return temp8 ...

Page 73: ...sing testcard 2 A missing EEPROM 3 An invalid EEPROM authentication code In addition the firmware revision is highlighted in order for technical support to assist you Q2 After the Silicon Labs splash screen which contains the firmware revision there is an additional screen shown before the setup menu s What is this for A2 Authentication codes in the EBID enable the Silicon Labs to qualify a factor...

Page 74: ...SDBC DK3 UG 74 Rev 0 3 DOCUMENT CHANGE LIST Revision 0 2 to Revision 0 3 Added Lab Mode instructions Added software programmers guide ...

Page 75: ...SDBC DK3 UG Rev 0 3 75 NOTES ...

Page 76: ...y for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and speci...