S D B C - D K 3 U G
Rev. 0.3
63
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
FUNCTION NAME:
RF_ENUM RFSetRfParameters (RF_SAMPLE_SETTINGS setting)
+
DESCRIPTION:
This function configures the RF part of the chip (both TX and RX)
+
for different (predefined) data rate, deviation and modulation index
+
requirements.
+
RETURN:
RF_OK: The operation was successful
+
RF_ERROR_PARAMETER: Invalid parameter, operation is ignored.
+
NOTES:
+
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
RF_ENUM RFSetRfParameters(RF_SAMPLE_SETTINGS setting)
{
// setup the internal digital modem according the selected RF settings (data rate)
SpiRfWriteAddressData((REG_WRITE | IFFilterBandwidth), RfSettings[setting][0] );
SpiRfWriteAddressData((REG_WRITE | ClockRecoveryOversamplingRatio), RfSettings[setting][1]);
SpiRfWriteAddressData((REG_WRITE | ClockRecoveryOffset2), RfSettings[setting][2]);
SpiRfWriteAddressData((REG_WRITE | ClockRecoveryOffset1), RfSettings[setting][3]);
SpiRfWriteAddressData((REG_WRITE | ClockRecoveryOffset0), RfSettings[setting][4]);
SpiRfWriteAddressData((REG_WRITE | ClockRecoveryTimingLoopGain1), RfSettings[setting][5]);
SpiRfWriteAddressData((REG_WRITE | ClockRecoveryTimingLoopGain0), RfSettings[setting][6]);
SpiRfWriteAddressData((REG_WRITE | TXDataRate1), RfSettings[setting][7]);
SpiRfWriteAddressData((REG_WRITE | TXDataRate0), RfSettings[setting][8]);
SpiRfWriteAddressData((REG_WRITE | ModulationModeControl1), RfSettings[setting][9]);
SpiRfWriteAddressData((REG_WRITE | FrequencyDeviation), RfSettings[setting][10]);
SpiRfWriteAddressData((REG_WRITE | AFCLoopGearshiftOverride), RfSettings[setting][11]);
SpiRfWriteAddressData((REG_WRITE | ChargepumpCurrentTrimming_Override), RfSettings[setting][12]);
// enable packet handler & CRC16
SpiRfWriteAddressData((REG_WRITE | DataAccessControl), 0x8D);
SpiRfWriteAddressData((REG_WRITE | ModulationModeControl2), 0x63);
// set preamble length & detection threshold
SpiRfWriteAddressData((REG_WRITE | PreambleLength), (PREAMBLE_LENGTH << 1));
SpiRfWriteAddressData((REG_WRITE | PreambleDetectionControl), ( PD_LENGTH << 4));
SpiRfWriteAddressData((REG_WRITE | ClockRecoveryGearshiftOverride), 0x03);
return
RF_OK;
}
Summary of Contents for C8051F930
Page 2: ...SDBC DK3 UG 2 Rev 0 3 ...
Page 9: ...SDBC DK3 UG Rev 0 3 9 Figure 5 MSC DBSB8 Schematic 2 of 2 ...
Page 21: ...SDBC DK3 UG Rev 0 3 21 Figure 24 Active Antenna and RSSI Indications ...
Page 23: ...SDBC DK3 UG Rev 0 3 23 Figure 26 Lab Equipment Connection Diagram ...
Page 75: ...SDBC DK3 UG Rev 0 3 75 NOTES ...
