C 8 0 5 1 F 9 7 0 D K - U G
16
Rev. 0.1
8. Schematics
5
5
4
4
3
3
2
2
1
1
HEADERS
PIN ASSIGNMENT
DEBUG
EXTERNAL CLOCK
REVISION HISTORY
003 1/31/2014
- Cleaned up BoM
002 9/3/2013
- Modified part names for cleaner
silkscreen
- Cleaned up part names
001 7/12/2013
- Original Release
MCU
VDD
VDD
VDD
VDD
5V_DBA
VDD
VDD_MCU
VDD
VDD
VDD
VDD
VDD
P4.7
P4.6
P4.5
P5.1
P5.0
P0.0
P5.2/C2D
RST/C2CK
P3.0
P2.4
P2.5
P2.6
P2.7
P2.3
P2.2
P2.1
P2.0
P1.7
P3.3
P3.2
P3.1
P3.5
P3.4
P4.0
P3.7
P3.6
P4.2
P4.1
P4.3
P4.4
P1.4
P1.5
P1.6
P1.2
P1.3
P0.7
P1.0
P1.1
P6.1
P0.6
P6.0
P2.5
P2.7
P2.3
P2.1
P1.4
P1.6
P1.2
P3.2
P3.4
P3.6
P0.0
P0.2
P0.4
P1.4
P1.5
P0.5
P0.3
P0.2
P0.4
P0.1
P0.0
P0.3
P0.2
P0.1
P1.6
P1.2
P1.3
P0.6
P0.7
VCP_RX
VCP_TX
P1.0
P1.1
P6.0
RST/C2CK
P1.0_P
XTAL2
XTAL1
XTAL2
P1.1_P
P1.0_P
P0.4
XTAL1
SI504_C1D
BTN0
BTN1
LED2
LED4
LED0
SI504_C1D
LED3
LED1
TBTN_CS1
TBTN_CS2
P2.2
P2.3
TBTN_CS4
TBTN_CS3
P2.4
P2.5
P2.6
TBTN_CS11
P3.7
P4.1
P4.0
TSLIDER_CS0
TSLIDER_CS1
TSLIDER_CS2
TSLIDER_CS3
TBTN_CS5
TBTN_CS6
TBTN_CS7
TBTN_CS8
TBTN_CS9
TBTN_CS10
TBTN_CS12
TBTN_CS13
TBTN_CS14
P3.4
P2.7
P3.1
P3.0
P3.2
P3.3
P3.5
P3.6
ADC0
TBTN_CS19
P4.6
P6.1
P6.0
P5.0
TBTN_CS15
P4.3
P4.5
P4.4
TBTN_CS16
TBTN_CS17
TBTN_CS18
P4.2
P2.1
P2.0
P1.7
TBTN_CS20
P4.7
I2C_SDA
I2C_SCL
I2C_SDA
I2C_SCL
P0.5
LED5
P3.0
P2.2
P2.4
P2.6
P2.0
P4.2
P4.4
P4.6
P4.0
P5.2/C2D
P5.0
P0.5
P6.1
P0.3
P0.1
P1.5
P1.7
P1.3
P1.1_P
P3.5
P3.7
P3.3
P3.1
P4.5
P4.7
P4.3
P4.1
RST/C2CK
P5.1
P5.2/C2D
VDD_VREF
Title
Size
Document Number
R
Date:
Sheet
of
400 W Cesar Chavez
Austin, TX 78701
C8051F970-TB
C8051F970 Target Board
B
13
Friday, January 31, 2014
Title
Size
Document Number
R
Date:
Sheet
of
400 W Cesar Chavez
Austin, TX 78701
C8051F970-TB
C8051F970 Target Board
B
13
Friday, January 31, 2014
Title
Size
Document Number
R
Date:
Sheet
of
400 W Cesar Chavez
Austin, TX 78701
C8051F970-TB
C8051F970 Target Board
B
13
Friday, January 31, 2014
JP1
R3
10M
SH24
0
SH17
0
C1
4.7uF
SH4
0
SH8
0
SH32
0
SH11
0
JP2
R17
4.7K
SH40
0
SH19
0
H5
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
SH28
0
SH26
0
H4
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
SH34
0
SH5
0
Y1
32.768KHz
C4
20pF
SH25
0
SH21
0
SH12
0
SH15
0
SH35
0
SH37
0
R1
1K
SH6
0
SH30
0
H2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
C2
0.1uF
U1
C8051F970
TX26/AM04/P0.4
1
RX00/AM51/P5.1
8
TX27/AM03/P0.3
2
TX28/AM02/P0.2
3
TX29/AM01/P0.1
4
TX30/VREF/AM00/P0.0
5
C2D/TX32/AM52/P5.2
6
RST/C2CK
7
RX01/AM50/P5.0
9
RX02/AM47/P4.7
10
PX03/AM46/P4.6
11
PX04/AM45/P4.5
12
RX05/AM44/P4.4
13
RX06/AM43/P4.3
14
RX07/AM42/P4.2
15
PX08/AM41/P4.1
16
RX12/TX01/AM35/P3.5
20
RX13/TX02/AM34/P3.4
21
RX14/TX03/AM33/P3.3
22
RX15/TX04/AM32/P3.2
23
RX11/TX00/AM36/P3.6
19
RX09/AM40/P4.0
17
TX05/AM31/P3.1
24
TX11/AM23/P2.3
30
TX07/AM27/P2.7
26
TX09/AM25/P2.5
28
TX06/AM30/P3.0
25
TX08/AM26/P2.6
27
TX10/AM24/P2.4
29
TX18/AM14/P1.4
39
GND
32
TX19/AM13/P1.3
40
TX12/AM22/P2.2
31
TX17/AM15/P1.5
38
TX16/AM16/P1.6
37
TX13/AM21/P2.1
34
RX10/AM37/P3.7
18
TX15/AM17/P1.7
36
VDD
33
TX14/AM20/P2.0
35
EPAD
49
TX20/AM12/P1.2
41
TX21/XTAL2/AM11/P1.1
42
TX22/XTAL1/AM10/P1.0
43
TX23/XTAL4/AM07/P0.7
44
TX
24/XTAL3/AM06/CNVST
R/P0.6
45
SDA/P6.1
46
SCL/P6.0
47
TX25/MULTI/AM05/P0.5
48
H7
1
2
3
SH23
0
SH13
0
R2
0
SH1
0
H6
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
U2
32kHz
C1D
1
GND
2
CLK
3
VDD
4
SH36
0
H8
DEBUG
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
SH18
0
S3
RESET
SH14
0
SH2
0
SH20
0
SH7
0
SH16
0
SH29
0
H3
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
Y2
25MHz
H1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
SH3
0
SH22
0
SH9
0
SH39
0
SH38
0
C3
1uF
C5
20pF
R16
4.7K
Figure
9.
C
80
51F97
0 T
a
rg
et Board Schem
atic (Revis
ion 2.0)
(1 of 3)
Not
Recommended
for
New
Designs
