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Silicon Laboratories C8051T320, Manual

The Silicon Laboratories C8051T320 is a high-performance microcontroller designed for various applications. This versatile product offers a comprehensive user manual, which can be easily downloaded for free from 88.208.23.73:8080. Enhance your experience with this cutting-edge technology by accessing the detailed manual at your convenience.

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C8051T620/1/6/7 & C8051T320/1/2/3

102

Rev. 1.2

17.1.  MCU Interrupt Sources and Vectors

The C8051T620/1/6/7 & C8051T320/1/2/3 MCUs support 18 interrupt sources. Software can simulate an 
interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt 
request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending 
flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in 
Table 17.1. Refer to the datasheet section associated with a particular on-chip peripheral for information 
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).

17.1.1. Interrupt Priorities

Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be 
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to 
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the 
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed prior-
ity order is used to arbitrate, given in Table 17.1.

17.1.2. Interrupt Latency

Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are 
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6 
system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the 
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL 
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no 
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is 
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is 
20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock 
cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is 
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the 
current ISR completes, including the RETI and following instruction.

Note that the CPU is stalled during EPROM write operations and USB FIFO MOVX accesses (see Section 
“15.2.3. Accessing USB FIFO Space” on page 91). Interrupt service latency will be increased for interrupts 
occurring while the CPU is stalled. The latency for these situations will be determined by the standard 
interrupt service procedure (as described above) and the amount of time the CPU is stalled. 

17.2.  Interrupt Register Descriptions

The SFRs used to enable the interrupt sources and set their priority level are described in this section. 
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding 
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).

Summary of Contents for C8051T320

Page 1: ...51 µC Core Pipelined instruction architecture executes 70 of instructions in 1 or 2 system clocks Up to 48 MIPS throughput with 48 MHz clock Expanded interrupt handler Memory Up to 3328 bytes internal data RAM 256 up to 3072 Up to 64 kB byte programmable EPROM code memory EPROM can be programmed from firmware running on the device Digital Peripherals 25 Port I O with high sink current capability H...

Page 2: ...C8051T620 1 6 7 C8051T320 1 2 3 2 Rev 1 2 ...

Page 3: ...w Detector 52 8 4 1 Window Detector Example 54 8 5 ADC0 Analog Multiplexer C8051T620 6 7 and C8051T320 1 Only 55 9 Temperature Sensor C8051T620 6 7 and C8051T320 1 Only 57 9 1 Calibration 58 10 Voltage Reference Options 59 11 Voltage Regulators REG0 and REG1 61 11 1 Voltage Regulator REG0 61 11 1 1 Regulator Mode Selection 61 11 1 2 VBUS Detection 61 11 2 Voltage Regulator REG1 64 12 CIP 51 Microc...

Page 4: ...ntenance 115 18 3 3 System Clock 115 18 4 Program Memory CRC 115 18 4 1 Performing 32 bit CRCs on Full EPROM Content 115 18 4 2 Performing 16 bit CRCs on 256 Byte EPROM Blocks 115 19 Power Management Modes 118 19 1 Idle Mode 118 19 2 Stop Mode 119 19 3 Suspend Mode 119 20 Reset Sources 121 20 1 Power On Reset 122 20 2 Power Fail Reset VDD Monitor 122 20 3 External Reset 124 20 4 Missing Clock Dete...

Page 5: ...ssing and Configuring Port I O 152 23 Universal Serial Bus Controller USB0 160 23 1 Endpoint Addressing 161 23 2 USB Transceiver 161 23 3 USB Register Access 163 23 4 USB Clock Configuration 168 23 5 FIFO Management 169 23 5 1 FIFO Split Mode 170 23 5 2 FIFO Double Buffering 170 23 5 1 FIFO Access 171 23 6 Function Addressing 172 23 7 Function Configuration and Control 173 23 8 Interrupts 176 23 9...

Page 6: ...e Slave 210 24 6 SMBus Status Decoding 210 25 UART0 215 25 1 Enhanced Baud Rate Generation 216 25 2 Operational Modes 217 25 2 1 8 Bit UART 217 25 2 2 9 Bit UART 218 25 3 Multiprocessor Communications 219 26 UART1 223 26 1 Baud Rate Generator 223 26 2 Data Format 225 26 3 Configuration and Operation 226 26 3 1 Data Transmission 226 26 3 2 Data Reception 226 26 3 3 Multiprocessor Communications 227...

Page 7: ... Capture Mode 264 29 Programmable Counter Array 268 29 1 PCA Counter Timer 269 29 2 PCA0 Interrupt Sources 270 29 3 Capture Compare Modules 271 29 3 1 Edge triggered Capture Mode 272 29 3 2 Software Timer Compare Mode 273 29 3 3 High Speed Output Mode 274 29 3 4 Frequency Output Mode 275 29 3 5 8 bit 9 bit 10 bit and 11 bit Pulse Width Modulator Modes 276 29 3 5 1 8 bit Pulse Width Modulator Mode ...

Page 8: ...e Right Justified Data 54 Figure 8 5 ADC Window Compare Example Left Justified Data 54 Figure 8 6 ADC0 Multiplexer Block Diagram 55 Figure 9 1 Temperature Sensor Transfer Function 57 Figure 9 2 TOFFH and TOFFL Calibration Value Orientation 58 Figure 9 3 Temperature Sensor Error with 1 Point Calibration at 0 Celsius 58 Figure 10 1 Voltage Reference Functional Block Diagram 59 Figure 11 1 REG0 Confi...

Page 9: ...Sequence 209 Figure 24 8 Typical Slave Read Sequence 210 Figure 25 1 UART0 Block Diagram 215 Figure 25 2 UART0 Baud Rate Logic 216 Figure 25 3 UART Interconnect Diagram 217 Figure 25 4 8 Bit UART Timing Diagram 217 Figure 25 5 9 Bit UART Timing Diagram 218 Figure 25 6 UART Multi Processor Mode Interconnect Diagram 219 Figure 26 1 UART1 Block Diagram 223 Figure 26 2 UART1 Timing Without Parity or E...

Page 10: ...er 3 8 Bit Mode Block Diagram 263 Figure 28 9 Timer 3 Low Frequency Oscillation Capture Mode Block Diagram 264 Figure 29 1 PCA Block Diagram 268 Figure 29 2 PCA Counter Timer Block Diagram 270 Figure 29 3 PCA Interrupt Block Diagram 271 Figure 29 4 PCA Capture Mode Diagram 273 Figure 29 5 PCA Software Timer Mode Diagram 274 Figure 29 6 PCA High Speed Output Mode Diagram 275 Figure 29 7 PCA Frequen...

Page 11: ...cillator Electrical Characteristics 39 Table 7 10 ADC0 Electrical Characteristics 40 Table 7 11 Temperature Sensor Electrical Characteristics 41 Table 7 12 Voltage Reference Electrical Characteristics 41 Table 7 13 Comparator Electrical Characteristics 42 Table 7 14 USB Transceiver Electrical Characteristics 43 Table 12 1 CIP 51 Instruction Set Summary 68 Table 16 1 Special Function Register SFR M...

Page 12: ...n 81 SFR Definition 14 3 CPT1CN Comparator1 Control 82 SFR Definition 14 4 CPT1MD Comparator1 Mode Selection 83 SFR Definition 14 5 CPT0MX Comparator0 MUX Selection 85 SFR Definition 14 6 CPT1MX Comparator1 MUX Selection 86 SFR Definition 15 1 EMI0CN External Memory Interface Control 91 SFR Definition 15 2 EMI0CF External Memory Configuration 94 SFR Definition 17 1 IE Interrupt Enable 104 SFR Defi...

Page 13: ...2 Output Mode 157 SFR Definition 22 19 P2SKIP Port 2 Skip 158 SFR Definition 22 20 P3 Port 3 158 SFR Definition 22 21 P3MDOUT Port 3 Output Mode 159 SFR Definition 23 1 USB0XCN USB0 Transceiver Control 162 SFR Definition 23 2 USB0ADR USB0 Indirect Address 164 SFR Definition 23 3 USB0DAT USB0 Data 165 SFR Definition 24 1 SMB0CF SMBus Clock Configuration 200 SFR Definition 24 2 SMB0CN SMBus Control ...

Page 14: ...ion 28 12 TMR2H Timer 2 High Byte 261 SFR Definition 28 13 TMR3CN Timer 3 Control 265 SFR Definition 28 14 TMR3RLL Timer 3 Reload Register Low Byte 266 SFR Definition 28 15 TMR3RLH Timer 3 Reload Register High Byte 266 SFR Definition 28 16 TMR3L Timer 3 Low Byte 266 SFR Definition 28 17 TMR3H Timer 3 High Byte 267 SFR Definition 29 1 PCA0CN PCA Control 282 SFR Definition 29 2 PCA0MD PCA Mode 283 S...

Page 15: ... on a Chip solutions User software has complete control of all peripherals and may individually shut down any or all peripherals for power savings Code written for the C8051T620 1 6 7 C8051T320 1 2 3 family of processors will run on the C8051F34A Mixed signal ISP Flash microcontroller providing a quick cost effective way to develop code without requiring special emulator circuitry The C8051T620 1 ...

Page 16: ...P2 2 P2 3 P2 4 P2 5 P2 6 USB Peripheral Controller 1k Byte RAM Full Low Speed Transceiver CIP 51 8051 Controller Core 16k Byte OTP Program Memory 256 Byte SRAM 1024 Byte XRAM D D VBUS UART1 VIO Port 0 Drivers Port 1 Drivers Port 3 Drivers Port 2 Drivers Voltage Regulator Regulator Core Power Peripheral Power GND REGIN VDD In system Programming Hardware VPP System Clock Setup External Oscillator In...

Page 17: ... 1 P2 2 P2 3 P2 4 P2 5 P2 6 USB Peripheral Controller 1k Byte RAM Full Low Speed Transceiver CIP 51 8051 Controller Core 64 32k Byte OTP Program Memory 256 Byte SRAM 3072 Byte XRAM D D VBUS UART1 VIO Port 0 Drivers Port 1 Drivers Port 3 Drivers Port 2 Drivers Voltage Regulator Regulator Core Power Peripheral Power GND REGIN VDD In system Programming Hardware VPP System Clock Setup External Oscilla...

Page 18: ...2 2 P2 3 P2 4 P2 5 P2 6 USB Peripheral Controller 1k Byte RAM Full Low Speed Transceiver CIP 51 8051 Controller Core 16k Byte OTP Program Memory 256 Byte SRAM 1024 Byte XRAM D D VBUS UART1 Port 0 Drivers Port 1 Drivers Port 3 Drivers Port 2 Drivers Voltage Regulator Regulator Core Power Peripheral Power GND REGIN VDD In system Programming Hardware VPP System Clock Setup External Oscillator Interna...

Page 19: ...2 0 P2 1 P2 2 P2 3 USB Peripheral Controller 1k Byte RAM Full Low Speed Transceiver CIP 51 8051 Controller Core 16k Byte OTP Program Memory 256 Byte SRAM 1024 Byte XRAM D D VBUS UART1 Port 0 Drivers Port 1 Drivers Port 3 Drivers Port 2 Drivers Voltage Regulator Regulator Core Power Peripheral Power GND REGIN VDD In system Programming Hardware VPP System Clock Setup External Oscillator Internal Osc...

Page 20: ...y pin 0 1µF 4 7µF 1µF Add ESD protection diodes designed for use with USB such as Littlefuse SP0503BAHT or equivalent 1 8V to VDD VIO VIO can be connected directly to VDD VIO Port I O GPIO DEBUG SIGNALS Connections needed for optional debug interface Keep the USB shield ground isolated from the device ground C2CK C2D GND Unused port pins should be left floating configured to push pull output and d...

Page 21: ...QFN32 C8051T621 GM 48 16k1 1280 Y Y Y Y Y Y 2 4 Y 24 2 Y QFN32 C8051T626 B GM5 48 64k1 3328 Y Y Y Y Y Y 2 4 Y 24 Y Y Y 2 Y QFN32 C8051T627 B GM5 48 32k 3328 Y Y Y Y Y Y 2 4 Y 24 Y Y Y 2 Y QFN32 C8051T320 GQ2 48 16k1 1280 Y Y Y Y Y Y 2 4 Y 25 Y Y Y 2 Y LQFP32 C8051T321 GM3 48 16k1 1280 Y Y Y Y Y Y 2 4 Y 21 Y Y Y 2 Y QFN28 C8051T322 GQ2 48 16k1 1280 Y Y Y Y Y Y 2 4 Y 25 2 Y LQFP32 C8051T323 GM3 48 1...

Page 22: ...0 Bi directional data signal for the C2 Debug Interface REGIN 8 7 7 5 V Regulator Input This pin is the input to the on chip voltage regulator VBUS 9 8 8 D In VBUS Sense Input This pin should be connected to the VBUS signal of a USB network A 5 V signal on this pin indicates a USB network connection D 4 4 4 D I O USB D D 5 5 5 D I O USB D VIO 6 V I O Supply Voltage Input The voltage at this pin mu...

Page 23: ...ator Section for complete details P0 4 30 30 26 D I O or A In Port 0 4 P0 5 29 29 25 D I O or A In Port 0 5 P0 6 CNVSTR 28 28 24 D I O or A In D In Port 0 6 ADC0 External Convert Start or IDA0 Update Source Input P0 7 VREF 27 27 23 D I O or A In A I O Port 0 7 ADC Voltage Reference P1 0 26 26 22 D I O or A In Port 1 0 P1 1 25 25 21 D I O or A In Port 1 1 P1 2 24 24 20 D I O or A In Port 1 2 P1 3 2...

Page 24: ...8 18 14 D I O or A In Port 2 0 P2 1 17 17 13 D I O or A In Port 2 1 P2 2 16 16 12 D I O or A In Port 2 2 P2 3 15 15 11 D I O or A In Port 2 3 P2 4 14 14 D I O or A In Port 2 4 P2 5 13 13 D I O or A In Port 2 5 P2 6 12 12 D I O or A In Port 2 6 P2 7 11 D I O or A In Port 2 7 Table 3 1 Pin Definitions for the C8051T620 1 6 7 C8051T320 1 2 3 Continued Name Pin Number Type Description T62x T320 2 T321...

Page 25: ... 25 P1 1 16 8 32 31 30 29 28 27 26 1 2 3 4 5 6 7 9 10 11 12 13 14 15 24 23 22 21 20 19 18 GND optional C8051T620 1 6 7 GM Top View P1 0 P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 GND VDD D VIO P2 6 P2 5 P2 4 P2 3 P2 2 P2 0 P2 1 P1 7 P1 6 P1 5 VPP P1 4 P1 3 P1 2 REGIN P3 0 C2D D RST C2CK VBUS ...

Page 26: ... View C8051T320 2 GQ Top View 1 P1 2 P1 7 P1 4 P1 3 P1 5 VPP P2 0 P2 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 P1 6 P3 0 C2D P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P1 1 P1 0 P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 GND REGIN D VDD VBUS D RST C2CK ...

Page 27: ...agram Top View 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 GND optional C8051T321 3 GM Top View P1 0 P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 GND P2 3 P2 2 P2 1 P2 0 P1 7 P1 6 P1 5 VPP P1 4 P1 3 P1 2 P1 1 VDD D REGIN D P3 0 C2D RST C2CK VBUS ...

Page 28: ... A2 1 35 1 40 1 45 L 0 45 0 60 0 75 b 0 30 0 37 0 45 aaa 0 20 c 0 09 0 20 bbb 0 20 D 9 00 BSC ccc 0 10 D1 7 00 BSC ddd 0 20 e 0 80 BSC 0 3 5 7 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to JEDEC outline MS 026 variation BBA 4 Recommended card reflow profile is per the JEDEC IPC J STD 020C spe...

Page 29: ...All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 m minimum all the way around the pad Stencil Design 4 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125 mm 5 mils 6 The ratio of stencil aperture to land pad siz...

Page 30: ...0 15 D 5 00 BSC aaa 0 15 D2 3 20 3 30 3 40 bbb 0 10 e 0 50 BSC ddd 0 05 E 5 00 BSC eee 0 08 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 variation VHHD except for custom features D2 E2 and L which are toleranced per supplier designation 4 Recommended card...

Page 31: ...MD Clearance between the solder mask and the metal pad is to be 60 m minimum all the way around the pad Stencil Design 4 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 5 The stencil thickness should be 0 125 mm 5 mils 6 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pins 7 A 3x3 arra...

Page 32: ...0 D 5 00 BSC ddd 0 05 D2 2 90 3 15 3 35 eee 0 08 e 0 50 BSC Z 0 44 E 5 00 BSC Y 0 18 E2 2 90 3 15 3 35 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This drawing conforms to the JEDEC Solid State Outline MO 220 variation VHHD except for custom features D2 E2 Z Y and L which are toleranced per supplier designation 4 R...

Page 33: ...older mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 m minimum all the way around the pad Stencil Design 5 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 6 The stencil thickness should be 0 125 mm 5 mils 7 The ratio of stencil aperture to land pad size should be 1 1 for all perime...

Page 34: ... cumulative VPP 3 6 V and In Applica tion Programming enabled or a non zero value written to EPCTL 10 s Voltage on VDD with respect to GND Regulator1 in Normal Mode Regulator1 in Bypass Mode 0 3 0 3 4 2 1 98 V V Maximum Total current through VDD VIO REGIN or GND 500 mA Maximum output current sunk by RST or any Port pin 100 mA Note Stresses above those listed under Absolute Maximum Ratings may caus...

Page 35: ...MHz VDD 3 3 V Clock 1 MHz VDD 3 6 V Clock 48 MHz VDD 3 6 V Clock 1 MHz 4 6 0 4 5 1 0 45 5 1 0 5 5 5 5 9 6 0 mA mA mA mA mA mA Digital Supply Current shutdown Oscillator not running stop mode Inter nal Regulator Off 1 µA Oscillator not running stop or suspend mode Internal Regulator On 375 µA Digital Supply Current for USB Module USB Active Mode VDD 3 6 V USB Clock 48 MHz VDD 3 3 V USB Clock 48 MHz...

Page 36: ...On VIN 0 V 1 25 1 50 µA µA Table 7 4 Reset Electrical Characteristics 40 to 85 C unless otherwise specified Parameters Test Condition Min Typ Max Unit RST Output Low Voltage IOL 8 5 mA VDD 1 8 V to 3 6 V 0 6 V RST Input High Voltage 0 75 x VIO V RST Input Low Voltage 0 6 V RST Input Pullup Current RST 0 0 V 25 50 µA VDD POR Threshold VRST 1 7 1 75 1 8 V Missing Clock Detector Time out Time from la...

Page 37: ...Normal Mode REG0MD 0 Low Power Mode REG0MD 1 83 38 98 52 µA Dropout Voltage VDO 3 IDD 1 mA IDD 100 mA 1 100 mV mA mV mA Voltage Regulator REG1 Input Voltage Range 1 8 3 6 V Bias Current Normal Mode REG1MD 0 Low Power Mode REG1MD 1 C8051T626 7 T320 1 2 3 C8051T626 7 320 425 175 200 µA µA µA Notes 1 Input range specified for regulation When an external regulator is used should be tied to VDD 2 Outpu...

Page 38: ...051T626 2 For devices with a Date Code prior to 1040 the programming time over the C2 interface is twice as long See Section 18 1 1 for more information 3 Duration of write time is largely dependent on VIO voltage supply voltage and residual charge on the VPP capacitor The majority of the write time consists of charging the voltage on VPP to 6 0 V These measurements include the VPP ramp time and V...

Page 39: ... Oscillator Supply Current from VDD 25 C VDD 3 0 V OSCLCN 7 1 C8051T626 7 T320 1 2 3 C8051T626 7 3 4 6 7 µA µA Power Supply Sensitivity Constant Temperature 0 09 V Temperature Sensitivity Constant Supply 30 ppm C Note Represents mean 1 standard deviation Table 7 9 External Oscillator Electrical Characteristics VDD 2 7 to 3 6 V TA 40 to 85 C unless otherwise specified Parameters Test Condition Min ...

Page 40: ...0 dB Total Harmonic Distortion Up to the 5th harmonic 70 dB Spurious Free Dynamic Range 93 dB Conversion Rate SAR Conversion Clock 8 00 MHz Conversion Time in SAR Clocks 10 bit Mode 8 bit Mode 13 11 clocks clocks Track Hold Acquisition Time VDD 2 0 V VDD 2 0 V 300 2 0 ns µs Throughput Rate 500 ksps Analog Inputs ADC Input Voltage Range Single Ended AIN GND 0 VREF V Absolute Pin Voltage with respec...

Page 41: ...ax Unit Internal Reference REFBE 1 Output Voltage 1 2 V Setting 25 C ambient 2 4 V Setting 25 C ambient 1 1 2 3 1 2 2 4 1 3 2 5 V VREF Short Circuit Current 4 5 6 mA VREF Temperature Coefficient 15 ppm C Load Regulation Load 0 to 200 µA to GND 1 2 V Setting Load 0 to 200 µA to GND 2 4 V Setting 3 3 5 7 µV µA µV µA VREF Turn on Time 1 2 V setting 4 7 µF tantalum 0 1 µF ceramic bypass 1 2 ms 0 1 µF ...

Page 42: ...ection Ratio 1 0 4 mV V Positive Hysteresis 1 CP0HYP1 0 00 0 1 mV Positive Hysteresis 2 CP0HYP1 0 01 2 5 8 mV Positive Hysteresis 3 CP0HYP1 0 10 6 10 14 mV Positive Hysteresis 4 CP0HYP1 0 11 12 20 28 mV Negative Hysteresis 1 CP0HYN1 0 00 0 1 mV Negative Hysteresis 2 CP0HYN1 0 01 2 5 8 mV Negative Hysteresis 3 CP0HYN1 0 10 6 10 14 mV Negative Hysteresis 4 CP0HYN1 0 11 12 20 28 mV Inverting or Non I...

Page 43: ...CRS 1 3 2 0 V Output Impedance ZDRV Driving High Driving Low 36 36 Pull up Resistance RPU Full Speed D Pull up Low Speed D Pull up 1 425 1 5 1 575 k Output Rise Time TR Low Speed Full Speed 75 4 300 20 ns Output Fall Time TF Low Speed Full Speed 75 4 300 20 ns Receiver Differential Input Sensitivity VDI D D 0 2 V Differential Input Common Mode Range VCM 0 8 2 5 V Input Leakage Current IL Pullups D...

Page 44: ...gital Supply Current vs Frequency MPCE 1 Figure 7 2 Idle Mode Digital Supply Current vs Frequency MPCE 1 0 0 2 0 4 0 6 0 8 0 10 0 12 0 0 5 10 15 20 25 30 35 40 45 50 IDD mA SYSCLK MHz VDD 1 8 V VDD 3 3 V 0 0 1 0 2 0 3 0 4 0 5 0 6 0 0 5 10 15 20 25 30 35 40 45 50 IDD mA SYSCLK MHz VDD 3 3 V VDD 1 8 V ...

Page 45: ...051T320 1 Only on page 55 The voltage reference for the ADC is selected as described in Section 10 Voltage Reference Options on page 59 The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register ADC0CN is set to logic 1 The ADC0 subsystem is in low power shutdown when this bit is logic 0 Figure 8 1 ADC0 Functional Block Diagram ADC0CF AMP0GN0 AD08BE AD0LJST AD0SC0 AD0SC1 AD...

Page 46: ...n Mode bits AD0CM2 0 in register ADC0CN Conversions may be initiated by one of the fol lowing 1 Writing a 1 to the AD0BUSY bit of register ADC0CN 2 A Timer 0 overflow i e timed continuous conversions 3 A Timer 2 overflow 4 A Timer 1 overflow 5 A rising edge on the CNVSTR input signal 6 A Timer 3 overflow Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed on ...

Page 47: ...are frequently changed due to the settling time requirements described in Section 8 3 3 Settling Time Requirements on page 48 Figure 8 2 10 Bit ADC Track and Conversion Example Timing Write 1 to AD0BUSY Timer 0 Timer 2 Timer 1 Overflow AD0CM 2 0 000 001 010 011 AD0TM 1 Track Convert Track AD0TM 0 Track Convert Track SAR Clocks SAR Clocks B ADC Timing for Internal Trigger Source CNVSTR AD0CM 2 0 1x...

Page 48: ...8 3 shows the equivalent ADC0 input circuit The required ADC0 settling time for a given settling accuracy SA may be approximated by Equation 8 1 See Table 7 10 for ADC0 minimum settling time requirements as well as the mux impedance and sampling capacitor values Equation 8 1 ADC0 Settling Time Requirements Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle w...

Page 49: ...0 SAR Conversion clock requirements are given in the ADC specification table Note If the Memory Power Controller is enabled MPCE 1 AD0SC must be set to at least 00001 for proper ADC operation 2 AD0LJST ADC0 Left Justify Select 0 Data in ADC0H ADC0L registers are right justified 1 Data in ADC0H ADC0L registers are left justified Note The AD0LJST bit is only valid for 10 bit mode AD08BE 0 1 AD08BE 8...

Page 50: ...0LJST 1 Bits 7 0 are the most significant bits of the 10 bit ADC0 Data Word Note In 8 bit mode AD0LJST is ignored and ADC0H holds the 8 bit data word SFR Definition 8 3 ADC0L ADC0 Data Word LSB Bit 7 6 5 4 3 2 1 0 Name ADC0L 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 ADC0L 7 0 ADC0 Data Word Low Order Bits For AD0LJST 0 Bits 7 0 are the lower 8 bits of the 10 bit Data Word For AD0LJS...

Page 51: ...ng and then begins the conversion 5 AD0INT ADC0 Conversion Complete Interrupt Flag 0 ADC0 has not completed a data conversion since AD0INT was last cleared 1 ADC0 has completed a data conversion 4 AD0BUSY ADC0 Busy Bit Read 0 ADC0 conversion is not in progress 1 ADC0 conversion is in prog ress Write 0 No Effect 1 Initiates ADC0 Conversion if AD0CM 2 0 000b 3 AD0WINT ADC0 Window Compare Interrupt F...

Page 52: ...GTL and Less Than ADC0LTH ADC0LTL registers hold the comparison values The window detector flag can be programmed to indicate when mea sured data is inside or outside of the user programmed limits depending on the contents of the ADC0 Less Than and ADC0 Greater Than registers SFR Address 0xC4 SFR Address 0xC3 SFR Definition 8 5 ADC0GTH ADC0 Greater Than Data High Byte Bit 7 6 5 4 3 2 1 0 Name ADC0...

Page 53: ...t 7 6 5 4 3 2 1 0 Name ADC0LTH 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 ADC0LTH 7 0 ADC0 Less Than Data Word High Order Bits SFR Definition 8 8 ADC0LTL ADC0 Less Than Data Low Byte Bit 7 6 5 4 3 2 1 0 Name ADC0LTL 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 ADC0LTL 7 0 ADC0 Less Than Data Word Low Order Bits ...

Page 54: ...mparison values Figure 8 4 ADC Window Compare Example Right Justified Data Figure 8 5 ADC Window Compare Example Left Justified Data 0x03FF 0x0081 0x0080 0x007F 0x0041 0x0040 0x003F 0x0000 0 Input Voltage AIN GND VREF x 1023 1024 VREF x 128 1024 VREF x 64 1024 AD0WINT 1 AD0WINT not affected AD0WINT not affected ADC0LTH ADC0LTL ADC0GTH ADC0GTL 0x03FF 0x0081 0x0080 0x007F 0x0041 0x0040 0x003F 0x0000...

Page 55: ... the AMX0P register described in SFR Definition 8 9 Figure 8 6 ADC0 Multiplexer Block Diagram Important Note About ADC0 Input Configuration Port pins selected as ADC0 inputs should be config ured as analog inputs and should be skipped by the Digital Crossbar To configure a Port pin for analog input set to 0 the corresponding bit in register PnMDIN To force the Crossbar to skip a Port pin set to 1 ...

Page 56: ... 0 AMX0P 4 0 AMUX0 Positive Input Selection 00000 P1 0 00001 P1 1 00010 P1 2 00011 P1 3 00100 P1 4 00101 P1 5 00110 P1 6 00111 P1 7 01000 P2 0 01001 P2 1 01010 P2 2 01011 P2 3 01100 P2 4 C8051T320 2 and C8051T620 6 7 Only 01101 P2 5 C8051T320 2 and C8051T620 6 7 Only 01110 P2 6 C8051T320 2 and C8051T620 6 7 Only 01111 P2 7 C8051T320 2 Only 10000 P3 0 10001 P0 0 10010 P0 1 10011 P0 4 10100 P0 5 101...

Page 57: ...function is shown in Figure 9 1 The output voltage VTEMP is the positive ADC input when the ADC multiplexer is set correctly The TEMPE bit in register REF0CN enables disables the temperature sensor as described in SFR Definition 10 1 While disabled the temperature sensor defaults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data Refer to Tab...

Page 58: ...so TOFFH contains the 8 most significant bits of the calibration value and TOFFL 7 6 contain the 2 least significant bits of the cali bration value as shown in Figure 9 2 One LSB of this measurement is equivalent to one LSB of the ADC output under the measurement conditions Figure 9 2 TOFFH and TOFFL Calibration Value Orientation Figure 9 3 shows the typical temperature sensor error assuming a 1 p...

Page 59: ...oltage reference generator and a selectable gain output buffer amplifier The buffer is configured for 1x or 2x gain using the REFBGS bit in register REF0CN On the 1x gain setting the output voltage is nominally 1 2 V and on the 2x gain setting the output voltage is nominally 2 4 V The on chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REF0CN to a 1 The max...

Page 60: ...llows the internal regulator to be used as a ref erence source 0 The voltage reference source is selected by the REFSL bit 1 The internal regulator is used as the voltage reference 3 REFSL Voltage Reference Select This bit selects the ADCs voltage reference 0 VREF pin used as voltage reference 1 VDD used as voltage reference 2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor off 1...

Page 61: ...G0 11 1 1 Regulator Mode Selection REG0 offers a low power mode intended for use when the device is in suspend mode In this low power mode the REG0 output remains as specified however the REG0 dynamic performance response time is degraded See Table 7 5 for normal and low power mode supply current specifications The REG0 mode selection is controlled via the REG0MD bit in register REG01CN 11 1 2 VBU...

Page 62: ...e 11 3 REG0 Configuration USB Self Powered Regulator Disabled Voltage Regulator REG0 5 V In 3 V Out VBUS Sense REGIN VBUS To 3 V Power Net Device Power Net VDD From 5 V Power Net From VBUS Voltage Regulator REG0 5 V In 3 V Out VBUS Sense REGIN VBUS From 3 V Power Net Device Power Net VDD From VBUS ...

Page 63: ... 1 2 63 C8051T620 1 6 7 C8051T320 1 2 3 Figure 11 4 REG0 Configuration No USB Connection Voltage Regulator REG0 5 V In 3 V Out VBUS Sense REGIN VBUS To 3 V Power Net Device Power Net VDD From 5 V Power Net ...

Page 64: ...mode When STOPCF is set to 1 the RST pin and a full power cycle of the device are the only methods of generating a reset REG1 offers an additional low power mode intended for use when the device is in suspend mode This low power mode should not be used during normal operation or if the REG0 Voltage Regulator is disabled See Table 7 5 for normal and low power mode supply current specifications The ...

Page 65: ... mode 0 REG1 Regulator is still active in STOP mode Any enabled reset source will reset the device 1 REG1 Regulator is shut down in STOP mode Only the RST pin or power cycle can reset the device 2 Reserved Must Write 0b 1 REG1MD Voltage Regulator REG1 Mode This bit selects the Voltage Regulator mode for REG1 When REG1MD is set to 1 the REG1 voltage regulator operates in lower power mode 0 REG1 Vol...

Page 66: ...struction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute and usually have a maximum system clock of 12 MHz By contrast the CIP 51 core executes 70 of its instructions in one or two system clock cycles with no instructions taking more than eight system clock cycles Figure 12 1 CIP 51 Block Diagr...

Page 67: ...erface to provide fast and efficient in sys tem device programming and debugging Third party macro assemblers and C compilers are also avail able 12 1 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the standard MCS 51 instruc tion set Standard 8051 development tools can be used to develop software for the CIP 51 All CIP 51 instructions are the binary a...

Page 68: ... A with borrow 2 2 SUBB A Ri Subtract indirect RAM from A with borrow 1 2 SUBB A data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC Ri Increment indirect RAM 1 2 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Ri Decrement indirect RAM 1 2 INC DPTR Increment Data Po...

Page 69: ... A right 1 1 RRC A Rotate A right through Carry 1 1 SWAP A Swap nibbles of A 1 1 Data Transfer MOV A Rn Move Register to A 1 1 MOV A direct Move direct byte to A 2 2 MOV A Ri Move indirect RAM to A 1 2 MOV A data Move immediate to A 2 2 MOV Rn A Move A to Register 1 1 MOV Rn direct Move direct byte to Register 2 2 MOV Rn data Move immediate to Register 2 2 MOV direct A Move A to direct byte 2 2 MO...

Page 70: ...AM with A 1 2 Boolean Manipulation CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set Carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 ANL C bit AND complement of direct bit to Carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to Carry 2 2 MOV C bit Move direct bit ...

Page 71: ... 4 CJNE A direct rel Compare direct byte to A and jump if not equal 3 3 5 CJNE A data rel Compare immediate to A and jump if not equal 3 3 5 CJNE Rn data rel Compare immediate to Register and jump if not equal 3 3 5 CJNE Ri data rel Compare immediate to indirect and jump if not equal 3 4 6 DJNZ Rn rel Decrement Register and jump if not zero 2 2 4 DJNZ direct rel Decrement direct byte and jump if n...

Page 72: ...dress This could be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2 kB page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP T...

Page 73: ... s default state Detailed descriptions of the remaining SFRs are included in the sec tions of the datasheet associated with their corresponding system function SFR Address 0x82 SFR Address 0x83 SFR Definition 12 1 DPL Data Pointer Low Byte Bit 7 6 5 4 3 2 1 0 Name DPL 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 DPL 7 0 Data Pointer Low The DPL register is the low byte of the 16 bit DP...

Page 74: ...stack The stack pointer is incre mented before every PUSH operation The SP register defaults to 0x07 after reset SFR Definition 12 4 ACC Accumulator Bit 7 6 5 4 3 2 1 0 Name ACC 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 ACC 7 0 Accumulator This register is the accumulator for arithmetic operations SFR Definition 12 5 B B Register Bit 7 6 5 4 3 2 1 0 Name B 7 0 Type R W Reset 0 0 0 0...

Page 75: ...is a bit addressable general purpose flag for use under software control 4 3 RS 1 0 Register Bank Select These bits select which register bank is used during register accesses 00 Bank 0 Addresses 0x00 0x07 01 Bank 1 Addresses 0x08 0x0F 10 Bank 2 Addresses 0x10 0x17 11 Bank 3 Addresses 0x18 0x1F 2 OV Overflow Flag This bit is set to 1 under the following circumstances An ADD ADDC or SUBB instructio...

Page 76: ...ut any jumps or branches the prefetch engine allows instructions to be exe cuted at full speed When a code branch occurs the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from EPROM memory Note The prefetch engine should be disabled when the device is in suspend mode to save power SFR Address 0xAF SFR Definition 13 1 PFE0CN Prefetch Engine Contro...

Page 77: ...A or CP1A The asynchronous signals are available even when the sys tem clock is not active This allows the Comparators to operate and generate an output with the device in STOP mode When assigned to a Port pin the Comparator outputs may be configured as open drain or push pull see Section 22 4 Port I O Initialization on page 146 Comparator0 may also be used as a reset source see Section 20 5 Compa...

Page 78: ...2 3 Priority Crossbar Decoder on page 142 for details on configuring Comparator outputs via the digital Crossbar Comparator inputs can be externally driven from 0 25 V to VDD 0 25 V without damage or upset The complete Comparator elec trical specifications are given in Section 7 Electrical Characteristics on page 34 The Comparator response time may be configured in software via the CPTnMD register...

Page 79: ... to logic 1 upon a Comparator falling edge occurrence and the CPnRIF flag is set to logic 1 upon the Comparator rising edge occurrence Once set these bits remain set until cleared by soft ware The Comparator rising edge interrupt mask is enabled by setting CPnRIE to a logic 1 The Compar ator falling edge interrupt mask is enabled by setting CPnFIE to a logic 1 The output state of the Comparator ca...

Page 80: ... software 0 No Comparator0 Rising Edge has occurred since this flag was last cleared 1 Comparator0 Rising Edge has occurred 4 CP0FIF Comparator0 Falling Edge Flag Must be cleared by software 0 No Comparator0 Falling Edge has occurred since this flag was last cleared 1 Comparator0 Falling Edge has occurred 3 2 CP0HYP 1 0 Comparator0 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 0...

Page 81: ... 0 Comparator0 Rising edge interrupt disabled 1 Comparator0 Rising edge interrupt enabled 4 CP0FIE Comparator0 Falling Edge Interrupt Enable 0 Comparator0 Falling edge interrupt disabled 1 Comparator0 Falling edge interrupt enabled 3 2 Unused Read 00b Write don t care 1 0 CP0MD 1 0 Comparator0 Mode Select These bits affect the response time and power consumption for Comparator0 00 Mode 0 Fastest R...

Page 82: ... software 0 No Comparator1 Rising Edge has occurred since this flag was last cleared 1 Comparator1 Rising Edge has occurred 4 CP1FIF Comparator1 Falling Edge Flag Must be cleared by software 0 No Comparator1 Falling Edge has occurred since this flag was last cleared 1 Comparator1 Falling Edge has occurred 3 2 CP1HYP 1 0 Comparator1 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 0...

Page 83: ... 0 Comparator1 Rising edge interrupt disabled 1 Comparator1 Rising edge interrupt enabled 4 CP1FIE Comparator1 Falling Edge Interrupt Enable 0 Comparator1 Falling edge interrupt disabled 1 Comparator1 Falling edge interrupt enabled 3 2 Unused Read 00b Write don t care 1 0 CP1MD 1 0 Comparator1 Mode Select These bits affect the response time and power consumption for Comparator1 00 Mode 0 Fastest R...

Page 84: ...t Important Note About Comparator Inputs The Port pins selected as comparator inputs should be con figured as analog inputs in their associated Port configuration register and configured to be skipped by the Crossbar for details on Port configuration see Section 22 6 Special Function Registers for Accessing and Configuring Port I O on page 152 Figure 14 4 Comparator Input Multiplexer Block Diagram...

Page 85: ...pe R R W R R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 Unused Read 0b Write don t care 6 4 CMX0N 2 0 Comparator0 Negative Input MUX Selection 000 P1 1 001 P1 5 010 P2 1 011 P2 5 100 P0 1 101 111 RESERVED 3 Unused Read 0b Write don t care 2 0 CMX0P 2 0 Comparator0 Positive Input MUX Selection 0000 P1 0 0001 P1 4 0010 P2 0 0011 P2 4 0100 P0 0 101 111 RESERVED ...

Page 86: ...e R R W R R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 Unused Read 0b Write don t care 6 4 CMX1N 2 0 Comparator1 Negative Input MUX Selection 000 P1 3 001 P1 7 010 P2 3 011 RESERVED 100 P0 5 101 111 RESERVED 3 Unused Read 0b Write don t care 2 0 CMX1P 2 0 Comparator1 Positive Input MUX Selection 000 P1 2 001 P1 6 010 P2 2 011 RESERVED 100 P0 4 101 111 RESERVED ...

Page 87: ...15 1 C8051T620 1 and C8051T320 1 2 3 Memory Map PROGRAM DATA MEMORY EPROM Direct and Indirect Addressing 0x00 0x7F Upper 128 RAM Indirect Addressing Only 0x80 0xFF Special Function Register s Direct Addressing Only DATA MEMORY RAM General Purpose Registers 0x1F 0x20 0x2F Bit Addressable Lower 128 RAM Direct and Indirect Addressing 0x30 INTERNAL DATA ADDRESS SPACE EXTERNAL DATA ADDRESS SPACE XRAM 1...

Page 88: ... Upper 128 RAM Indirect Addressing Only 0x80 0xFF Special Function Register s Direct Addressing Only DATA MEMORY RAM General Purpose Registers 0x1F 0x20 0x2F Bit Addressable Lower 128 RAM Direct and Indirect Addressing 0x30 INTERNAL DATA ADDRESS SPACE EXTERNAL DATA ADDRESS SPACE XRAM 3072 Bytes accessable using MOVX instruction 0x0000 0x0BFF Same 4096 bytes as from 0x0000 to 0x0FFF wrapped on 4096...

Page 89: ... temperature sensor calibration values can be found in Section 9 1 Calibration on page 58 15 1 3 Serialization All C8051T620 1 6 7 C8051T320 1 2 3 devices have a factory serialization located in EPROM memory This value is unique to each device The serial number is located at the address indicated in Figure 15 3 and can be accessed like any constant array in program memory Device Derivative ID C805...

Page 90: ...ks of gen eral purpose registers Each bank consists of eight byte wide registers designated R0 through R7 Only one of these banks may be enabled at a time Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in SFR Definition 12 6 This allows fast context switching when entering subroutines and interrupt service routines Indirect ad...

Page 91: ... 4 shows an expanded view of the FIFO space and user XRAM FIFO space is normally accessed via USB FIFO registers see Section 23 5 FIFO Management on page 169 for more informa tion on accessing these FIFOs The MOVX instruction should not be used to load or modify USB data in the FIFO space Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary The FIFO block operates on...

Page 92: ...when the USBFAE bit is set to 1 Important Note The USB clock must be active when accessing FIFO space Figure 15 4 C8051T620 1 and C8051T320 1 2 3 USB FIFO Space and XRAM Memory Map with USBFAE Set to 1 On Chip XRAM 0x0000 Endpoint0 64 bytes Free 64 bytes 0x0400 0x043F 0x0440 0x063F 0x0640 0x073F 0x0740 0x07BF 0x07C0 0x07FF Endpoint1 128 bytes Endpoint2 256 bytes Endpoint3 512 bytes USB FIFO Space ...

Page 93: ... empty space 0x0000 Endpoint0 64 bytes Free 64 bytes 0x1000 0x103F 0x1040 0x123F 0x1240 0x133F 0x1340 0x13BF 0x13C0 0x13FF Endpoint1 128 bytes Endpoint2 256 bytes Endpoint3 512 bytes USB FIFO Space USB Clock Domain 0x0FFF Same 8192 bytes as 0x0000 to 0x1FFF wrapped at 8192 byte boundaries 0x1400 0x1FFF USB FIFO space repeated 3 times 0x2000 0xFFFF ...

Page 94: ...sed Read 0b Write Don t Care 6 USBFAE USB FIFO Access Enable 0 USB FIFO RAM not available through MOVX instructions 1 USB FIFO RAM available using MOVX instructions The 1k of USB RAM will be mapped in XRAM space at addresses 0x0400 to 0x07FF The USB clock must be active and greater than or equal to twice the SYSCLK USBCLK 2 x SYSCLK to access this area with MOVX instructions 5 0 Unused Read 000011...

Page 95: ...ing these areas will have an indeterminate effect and should be avoided Refer to the corresponding pages of the data sheet as indicated in Table 16 2 for a detailed description of each register Table 16 1 Special Function Register SFR Memory Map F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN F0 B P0MDIN P1MDIN P2MDIN PCA0PWM IAPCN EIP1 EIP2 E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PC...

Page 96: ...0P 0xBB AMUX0 Positive Channel Select 56 B 0xF0 B Register 74 CKCON 0x8E Clock Control 247 CLKMUL 0xB9 Clock Multiplier Control 132 CLKSEL 0xA9 Clock Select 129 CPT0CN 0x9B Comparator0 Control 80 CPT0MD 0x9D Comparator0 Mode Selection 81 CPT0MX 0x9F Comparator0 MUX Selection 85 CPT1CN 0x9B Comparator1 Control 82 CPT1MD 0x9D Comparator1 Mode Selection 83 CPT1MX 0x9F Comparator1 MUX Selection 86 DPH...

Page 97: ...ut Mode Configuration 153 P0MDOUT 0xA4 Port 0 Output Mode Configuration 153 P0SKIP 0xD4 Port 0 Skip 154 P1 0x90 Port 1 Latch 154 P1MASK 0xBA Port 1Mask Configuration 151 P1MAT 0xB6 Port 1 Match Configuration 151 P1MDIN 0xF2 Port 1 Input Mode Configuration 155 P1MDOUT 0xA5 Port 1 Output Mode Configuration 155 P1SKIP 0xD5 Port 1 Skip 156 P2 0xA0 Port 2 Latch 156 P2MDIN 0xF3 Port 2 Input Mode Configu...

Page 98: ...CPM3 0xDD PCA Module 3 Mode Register 285 PCA0CPM4 0xDE PCA Module 4 Mode Register 285 PCA0H 0xFA PCA Counter High 286 PCA0L 0xF9 PCA Counter Low 286 PCA0MD 0xD9 PCA Mode 283 PCA0PWM 0xF4 PCA PWM Configuration 284 PCON 0x87 Power Control 120 PFE0CN 0xAF Prefetch Engine Control 76 PSCTL 0x8F Program Store R W Control 116 PSW 0xD0 Program Status Word 75 REF0CN 0xD1 Voltage Reference Control 60 REG01C...

Page 99: ...xA2 SPI Clock Rate Control 242 SPI0CN 0xF8 SPI Control 241 SPI0DAT 0xA3 SPI Data 242 TCON 0x88 Timer Counter Control 252 TH0 0x8C Timer Counter 0 High 255 TH1 0x8D Timer Counter 1 High 255 TL0 0x8A Timer Counter 0 Low 254 TL1 0x8B Timer Counter 1 Low 254 TMOD 0x89 Timer Counter Mode 253 TMR2CN 0xC8 Timer Counter 2 Control 259 TMR2H 0xCD Timer Counter 2 High 261 TMR2L 0xCC Timer Counter 2 Low 260 T...

Page 100: ...USB0 Indirect Address 164 USB0DAT 0x97 USB0 Data 165 USB0XCN 0xD7 USB0 Transceiver Control 162 VDM0CN 0xFF VDD Monitor Control 124 XBR0 0xE1 Port I O Crossbar Control 0 147 XBR1 0xE2 Port I O Crossbar Control 1 148 XBR2 0xE3 Port I O Crossbar Control 2 149 Table 16 2 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address...

Page 101: ...rupt enable bit in an SFR IE EIE1 or EIE2 However interrupts must first be globally enabled by setting the EA bit IE 7 to logic 1 before the individual interrupt enables are recognized Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt enable settings Note Any instruction that clears a bit to disable an interrupt should be immediately followed by an...

Page 102: ...k cycle Therefore the fastest possible response time is 6 system clock cycles 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the ISR If an interrupt is pending when a RETI is executed a single instruction is executed before an LCALL is made to service the pending interrupt Therefore the maximum response time for an interrupt when no other interrupt is currently b...

Page 103: ...SPI0CN 4 Y N ESPI0 IE 6 PSPI0 IP 6 SMB0 0x003B 7 SI SMB0CN 0 Y N ESMB0 EIE1 0 PSMB0 EIP1 0 USB0 0x0043 8 Special N N EUSB0 EIE1 0 PUSB0 EIP1 1 ADC0 Window Com pare 0x004B 9 AD0WINT ADC0CN 3 Y N EWADC0 EIE1 2 PWADC0 EIP1 2 ADC0 Conversion Complete 0x0053 10 AD0INT ADC0CN 5 Y N EADC0 EIE1 3 PADC0 EIP1 3 Programmable Coun ter Array 0x005B 11 CF PCA0CN 7 CCFn PCA0CN n COVF PCA0PWM 6 Y N EPCA0 EIE1 4 P...

Page 104: ...imer 2 interrupt 0 Disable Timer 2 interrupt 1 Enable interrupt requests generated by the TF2L or TF2H flags 4 ES0 Enable UART0 Interrupt This bit sets the masking of the UART0 interrupt 0 Disable UART0 interrupt 1 Enable UART0 interrupt 3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable all Timer 1 interrupt 1 Enable interrupt requests generated by the TF1...

Page 105: ...it sets the priority of the UART0 interrupt 0 UART0 interrupt set to low priority level 1 UART0 interrupt set to high priority level 3 PT1 Timer 1 Interrupt Priority Control This bit sets the priority of the Timer 1 interrupt 0 Timer 1 interrupt set to low priority level 1 Timer 1 interrupt set to high priority level 2 PX1 External Interrupt 1 Priority Control This bit sets the priority of the Ext...

Page 106: ...e CP0RIF or CP0FIF flags 4 EPCA0 Enable Programmable Counter Array PCA0 Interrupt This bit sets the masking of the PCA0 interrupts 0 Disable all PCA0 interrupts 1 Enable interrupt requests generated by PCA0 3 EADC0 Enable ADC0 Conversion Complete Interrupt This bit sets the masking of the ADC0 Conversion Complete interrupt 0 Disable ADC0 Conversion Complete interrupt 1 Enable interrupt requests ge...

Page 107: ...rogrammable Counter Array PCA0 Interrupt Priority Control This bit sets the priority of the PCA0 interrupt 0 PCA0 interrupt set to low priority level 1 PCA0 interrupt set to high priority level 3 PADC0 ADC0 Conversion Complete Interrupt Priority Control This bit sets the priority of the ADC0 Conversion Complete interrupt 0 ADC0 Conversion Complete interrupt set to low priority level 1 ADC0 Convers...

Page 108: ...b 3 EMAT Enable Port Match Interrupts This bit sets the masking of the Port Match Event interrupt 0 Disable all Port Match interrupts 1 Enable interrupt requests generated by a Port Match 2 Reserved Must write 0b 1 ES1 Enable UART1 Interrupt This bit sets the masking of the UART1 interrupt 0 Disable UART1 interrupt 1 Enable UART1 interrupt 0 EVBUS Enable VBUS Level Interrupt This bit sets the mask...

Page 109: ...ntrol This bit sets the priority of the Port Match Event interrupt 0 Port Match interrupt set to low priority level 1 Port Match interrupt set to high priority level 2 Reserved Must Write 0b 1 PS1 UART1 Interrupt Priority Control This bit sets the priority of the UART1 interrupt 0 UART1 interrupt set to low priority level 1 UART1 interrupt set to high priority level 0 PVBUS VBUS Level Interrupt Pr...

Page 110: ...see Section 22 3 Priority Crossbar Decoder on page 142 for complete details on configuring the Crossbar IE0 TCON 1 and IE1 TCON 3 serve as the interrupt pending flags for the INT0 and INT1 external inter rupts respectively If an INT0 or INT1 external interrupt is configured as edge sensitive the corresponding interrupt pending flag is automatically cleared by the hardware when the CPU vectors to t...

Page 111: ...ill not assign the Port pin to a peripheral if it is configured to skip the selected pin 000 Select P0 0 001 Select P0 1 010 Select P0 2 011 Select P0 3 100 Select P0 4 101 Select P0 5 110 Select P0 6 111 Select P0 7 3 IN0PL INT0 Polarity 0 INT0 input is active low 1 INT0 input is active high 2 0 IN0SL 2 0 INT0 Port Pin Selection Bits These bits select which Port pin is assigned to INT0 Note that ...

Page 112: ... 3 1 Reset the device using the RST pin 2 Wait at least 20 ms before sending the first C2 command 3 Place the device in core reset Write 0x04 to the DEVCTL register 4 Set the device to program mode 1st step Write 0x40 to the EPCTL register 5 Set the device to program mode 2nd step Write 0x4A to the EPCTL register Note Devices with a Date Code prior to 1040 should write 0x58 to the EPCTL register 6...

Page 113: ...gister 6 Set the VPP Pin to an open drain configuration with a 1 in the port latch 7 Set the PSWE bit register PSCTL 8 Write the first key code to MEMKEY 0xA5 9 Write the second key code to MEMKEY 0xF1 10 Enable in application programming Write 0x80 to the IAPCN register 11 Using a MOVX write instruction write a single data byte to the desired location 12 Disable in application EPROM programming W...

Page 114: ...ces to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded 2 Make certain that the minimum VDD rise time specification of 1 ms is met If the system cannot meet this rise time specification then add an external VDD brownout circuit to the RST pin of the device that holds the device in reset until VDD reaches VRST and re asserts RST if VD...

Page 115: ...ed on chip which provides a means of verifying EPROM contents once the device has been programmed The CRC engine is available for EPROM verification even if the device is fully read and write locked allowing for verification of code contents at any time The CRC engine is operated through the C2 debug and programming interface and performs 16 bit CRCs on individual 256 Byte blocks of program memory...

Page 116: ...0 0 0 0 0 0 0 Bit Name Function 7 0 MEMKEY 7 0 EPROM Lock and Key Register Write This register provides a lock and key function for EPROM writes EPROM writes are enabled by writing 0xA5 followed by 0xF1 to the MEMKEY register EPROM writes are automatically disabled after the next write is complete If any writes to MEMKEY are performed incorrectly or if a EPROM write operation is attempted while th...

Page 117: ...Application Programming is disabled 1 In Application Programming is enabled 6 IAPHWD In Application Programming Hardware Disable This bit disables the In Application Programming hardware so the VPP programming pin can be used as a normal GPIO pin Note This bit should not be set less than 1 µs after the last EPROM write 0 In Application Programming discharge hardware enabled 1 In Application Progra...

Page 118: ...imers or serial buses draw little power when they are not in use Turning off oscillators lowers power consumption considerably at the expense of reduced functionality 19 1 Idle Mode Setting the Idle Mode Select bit PCON 0 causes the hardware to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution All internal registers and memory maintain their original...

Page 119: ...efinition 11 1 If the regulator is shut down using the STOPCF bit only the RST pin or a full power cycle are capa ble of resetting the device 19 3 Suspend Mode Setting the SUSPEND bit OSCICN 5 causes the hardware to halt the high frequency internal oscillator and go into suspend mode as soon as the instruction that sets the bit completes execution All internal reg isters and memory maintain their ...

Page 120: ...purpose flags for use under software control 1 STOP Stop Mode Select Setting this bit will place the CIP 51 in stop mode This bit will always be read as 0 1 CPU goes into stop mode internal oscillator stopped 0 IDLE IDLE Idle Mode Select Setting this bit will place the CIP 51 in Idle mode This bit will always be read as 0 1 CPU goes into Idle mode Shuts off clock to CPU but clock to Timers Interru...

Page 121: ... not altered The Port I O latches are reset to 0xFF all logic ones in open drain mode Weak pullups are enabled dur ing and after the reset For VDD Monitor and power on resets the RST pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator The Watchdog Timer is enabled with the sy...

Page 122: ...the RSTSRC Register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The con tent of internal data memory should be assumed to be undefined after a power on reset The VDD monitor is enabled following a power on reset Figure 20 2 Powe...

Page 123: ...et source before it is enabled and stabi lized may cause a system reset In some applications this reset may be undesirable If this is not desirable in the application a delay should be introduced between enabling the monitor and selecting it as a reset source The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled state is shown below 1 Enable the VDD monito...

Page 124: ...n on chatter on the output from generating an unwanted reset The Comparator0 reset is active low if the non inverting input voltage on CP0 is less than the inverting input voltage on CP0 the device is put into the reset state After a Comparator0 reset the C0RSEF flag RSTSRC 5 will read 1 signifying Comparator0 as the reset source otherwise this bit reads 0 The state of the RST pin is unaffected by...

Page 125: ...t A Program read is attempted above user code space This occurs when user code attempts to branch to an address above the user code space address limit The MEMERR bit RSTSRC 6 is set following an EPROM error reset The state of the RST pin is unaf fected by this reset 20 8 Software Reset Software may force a reset by writing a 1 to the SWRSF bit RSTSRC 4 The SWRSF bit will read 1 fol lowing a softw...

Page 126: ...d Flag Writing a 1 forces a sys tem reset Set to 1 if last reset was caused by a write to SWRSF 3 WDTRSF Watchdog Timer Reset Flag N A Set to 1 if Watchdog Timer overflow caused the last reset 2 MCDRSF Missing Clock Detector Enable and Flag Writing a 1 enables the Missing Clock Detector The MCD triggers a reset if a missing clock condition is detected Set to 1 if Missing Clock Detector timeout cau...

Page 127: ...or circuit or either internal oscillator Both internal oscillators offer a selectable post scaling feature The USB clock USBCLK can be derived from the internal oscillators or external oscillator Figure 21 1 Oscillator Options OSC Programmable Internal Clock Generator Input Circuit EN SYSCLK OSCICL OSCICN IOSCEN IFRDY SUSPEND IFCN1 IFCN0 OSCXCN XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 CLKSEL USBC...

Page 128: ...gh Frequency oscillator or a divided version of the external oscillator Note that the USB clock must be 48 MHz when operating USB0 as a Full Speed Function the USB clock must be 6 MHz when operating USB0 as a Low Speed Function See SFR Definition 21 1 for USB clock selection options Some example USB clock configurations for Full and Low Speed mode are given below USB Full Speed 48 MHz Internal Osc...

Page 129: ...d from the Internal Low Frequency Oscillator 111 RESERVED 3 OUTCLK Crossbar Clock Out Select If the SYSCLK signal is enabled on the Crossbar this bit selects between outputting SYSCLK and SYSCLK synchronized with the Port I O pins 0 Enabling the Crossbar SYSCLK signal outputs SYSCLK 1 Enabling the Crossbar SYSCLK signal outputs SYSCLK synchronized with the Port I O 2 0 CLKSL 2 0 System Clock Sourc...

Page 130: ...Event Port 1 Match Event Timer3 Overflow Event USB0 Transceiver Resume Signalling When one of the oscillator awakening events occur the internal oscillator CIP 51 and affected peripherals resume normal operation regardless of whether the event also causes an interrupt The CPU resumes execution at the instruction following the write to the SUSPEND bit Note The prefetch engine can be turned off in s...

Page 131: ...d frequency 5 SUSPEND Internal Oscillator Suspend Enable Bit Setting this bit to logic 1 places the internal oscillator in SUSPEND mode The inter nal oscillator resumes operation when one of the SUSPEND mode awakening events occurs 4 2 Unused Read 000b Write Don t Care 1 0 IFCN 1 0 Internal H F Oscillator Frequency Divider Control Bits The Internal H F Oscillator is divided by the IFCN bit setting...

Page 132: ... 0 Bit Name Description Write Read 7 MULEN Clock Multiplier Enable Bit 0 Clock Multiplier disabled 1 Clock Multiplier enabled This bit always reads 1 6 MULINIT Clock Multiplier Initialize Bit This bit should be a 0 when the Clock Multiplier is enabled Once enabled writing a 1 to this bit will initialize the Clock Multiplier The MULRDY bit reads 1 when the Clock Multiplier is stabilized This bit al...

Page 133: ...d registers TMRnRLH TMRnRLL By recording the differ ence between two successive timer capture values the low frequency oscillator s period can be calcu lated The OSCLF bits can then be adjusted to produce the desired oscillator frequency SFR Address 0x86 SFR Definition 21 5 OSCLCN Internal L F Oscillator Control Bit 7 6 5 4 3 2 1 0 Name OSCLEN OSCLRDY OSCLF 3 0 OSCLD 1 0 Type R W R R W R W Reset 0...

Page 134: ...e data sheet chapters for each digital peripheral for details See Section 7 Electrical Characteristics on page 34 for complete oscillator specifications 21 6 1 External Crystal Mode If a crystal or ceramic resonator is used as the external oscillator the crystal resonator and a 10 M resis tor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 21 1 Crystal Mode Appropriate loading cap...

Page 135: ...nal oscillator has a duty cycle of 50 The External Oscillator Frequency Con trol value XFCN must also be specified based on the crystal frequency see SFR Definition 21 6 When the crystal oscillator is first enabled the external oscillator valid detector allows software to deter mine when the external system clock is valid and running Switching to the external oscillator before the crystal oscillat...

Page 136: ...Definition 21 6 the required XFCN setting is 010b 21 6 3 External Capacitor Example If a capacitor is used as an external oscillator for the MCU the circuit should be configured as shown in Figure 21 1 C Mode The capacitor should be no greater than 100 pF however for very small capaci tors the total capacitance may be dominated by parasitic capacitance in the PCB layout To determine the required E...

Page 137: ...rcuit off 010 External CMOS Clock Mode 011 External CMOS Clock Mode with divide by 2 stage 100 RC Oscillator Mode 101 Capacitor Oscillator Mode 110 Crystal Oscillator Mode 111 Crystal Oscillator Mode with divide by 2 stage 3 Unused Read 0 Write Don t Care 2 0 XFCN 2 0 External Oscillator Frequency Control Bits Set according to the desired frequency for RC mode Set according to the desired K Factor...

Page 138: ...I O pins based on the Priority Decoder Figure 22 4 The registers XBR0 XBR1 and XBR2 defined in SFR Definition 22 1 SFR Definition 22 2 and SFR Definition 22 2 are used to select internal digital functions All Port I Os are 5 V tolerant refer to Figure 22 2 for the Port cell circuit The Port I O cells are configured as either push pull or open drain in the Port Output Mode registers PnMDOUT where n...

Page 139: ...wo output modes push pull or open drain must be selected using the PnMDOUT registers Push pull outputs PnMDOUT n 1 drive the Port pad to the VIO or GND supply rails based on the output logic value of the Port pin Open drain outputs have the high side driver disabled therefore they only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs both high and low dri...

Page 140: ...ort I O assignments Port pins selected for these analog functions should have their corresponding bit in PnSKIP set to 1 This reserves the pin for use by the analog function and does not allow it to be claimed by the Crossbar Table 22 1 shows the potential mapping of Port I O to each analog function 22 2 2 Assigning Port I O Pins to Digital Functions Any Port pins not assigned to analog functions ...

Page 141: ...sbar PnSKIP 0 External digital event capture functions cannot be used on pins configured for analog I O Table 22 3 shows all available external digital event capture functions Table 22 2 Port I O Assignment for Digital Functions Digital Function Potentially Assignable Port Pins Suffers used for Assignment UART0 SPI0 SMBus CP0 CP0A CP1 CP1A SYSCLK PCA0 CEX0 4 and ECI T0 T1 or UART1 Any Port pin ava...

Page 142: ... as if they were already assigned and moves to the next unassigned pin Registers XBR0 XBR1 and XBR2 are used to assign the digital I O resources to the physical I O Port pins Note that when the SMBus is selected the Crossbar assigns both pins associated with the SMBus SDA and SCL when a UART is selected the Crossbar assigns both pins associated with the UART TX and RX UART0 pin assignments are fix...

Page 143: ...e crossbar peripherals are assigned in priority order from top to bottom according to this diagram These boxes represent Port pins which can potentially be assigned to a peripheral Special Function Signals are not assigned by the crossbar When these signals are enabled the Crossbar should be manually configured to skip the corresponding port pins Pins can be skipped by setting the corresponding bi...

Page 144: ...o P0 4 2nd RX0 is assigned to P0 5 3rd SCK MISO MOSI and NSS are assigned to P0 0 P0 1 P0 2 and P0 3 respectively 4th CEX0 CEX1 and CEX2 are assigned to P0 6 P0 7 and P1 0 respectively All unassigned pins can be used as GPIO or for other non crossbar functions Notes 1 P2 4 P2 7 are only available in certain packages 0 P0 Port Pin Number Special Function Signals 0 0 0 0 0 0 0 0 P0SKIP Pin Skip Sett...

Page 145: ...ed to P0 5 3rd SCK MISO MOSI and NSS are assigned to P0 1 P0 6 P0 7 and P1 0 respectively 4th CEX0 CEX1 and CEX2 are assigned to P1 1 P1 2 and P1 3 respectively All unassigned pins including those skipped by XBR0 can be used as GPIO or for other non crossbar functions Notes 1 P2 4 P2 7 are only available in certain packages 0 P0 Port Pin Number Special Function Signals 1 0 1 1 0 0 0 0 P0SKIP Pin S...

Page 146: ... SFR Definition 22 13 and SFR Definition 22 17 for the PnMDIN register details The output driver characteristics of the I O pins are defined using the Port Output Mode registers PnMD OUT Each Port Output driver can be configured as either open drain or push pull This selection is required even for the digital resources selected in the XBRn registers and is not automatic The only exception to this ...

Page 147: ...utput Enable 0 Asynchronous CP0 unavailable at Port pin 1 Asynchronous CP0 routed to Port pin 4 CP0E Comparator0 Output Enable 0 CP0 unavailable at Port pin 1 CP0 routed to Port pin 3 SYSCKE SYSCLK Output Enable The source of this signal is determined by the OUTCLK bit see SFR Definition 21 1 0 SYSCLK unavailable at Port pin 1 SYSCLK output routed to Port pin 2 SMB0E SMBus I O Enable 0 SMBus I O u...

Page 148: ... 6 XBARE Crossbar Enable 0 Crossbar disabled 1 Crossbar enabled 5 T1E T1 Enable 0 T1 unavailable at Port pin 1 T1 routed to Port pin 4 T0E T0 Enable 0 T0 unavailable at Port pin 1 T0 routed to Port pin 3 ECIE PCA0 External Counter Input Enable 0 ECI unavailable at Port pin 1 ECI routed to Port pin 2 0 PCA0ME 2 0 PCA Module I O Enable Bits 000 All PCA I O unavailable at Port pins 001 CEX0 routed to...

Page 149: ...used to individually select which P0 and P1 pins should be compared against the PnMATCH registers A Port mismatch event is generated if P0 P0MASK does not equal P0MATCH P0MASK or if P1 P1MASK does not equal P1MATCH P1MASK A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode such as IDLE or SUSPEND See the Interrupts and Power Options chapters for more...

Page 150: ...rresponding bits in P0MAT 0 P0 n pin logic value is ignored and cannot cause a Port Mismatch event 1 P0 n pin logic value is compared to P0MAT n SFR Definition 22 5 P0MAT Port 0 Match Register Bit 7 6 5 4 3 2 1 0 Name P0MAT 7 0 Type R W Reset 1 1 1 1 1 1 1 1 Bit Name Function 7 0 P0MAT 7 0 Port 0 Match Value Match comparison value used on Port 0 for bits in P0MASK which are set to 1 0 P0 n pin log...

Page 151: ...rresponding bits in P1MAT 0 P1 n pin logic value is ignored and cannot cause a Port Mismatch event 1 P1 n pin logic value is compared to P1MAT n SFR Definition 22 7 P1MAT Port 1 Match Register Bit 7 6 5 4 3 2 1 0 Name P1MAT 7 0 Type R W Reset 1 1 1 1 1 1 1 1 Bit Name Function 7 0 P1MAT 7 0 Port 1 Match Value Match comparison value used on Port 1 for bits in P1MASK which are set to 1 0 P1 n pin log...

Page 152: ... be assigned to dig ital functions or skipped by the Crossbar All Port pins used for analog functions or GPIO should have their PnSKIP bit set to 1 The Port input mode of the I O pins is defined using the Port Input Mode registers PnMDIN Each Port cell can be configured for analog or digital I O This selection is required even for the digital resources selected in the XBRn registers and is not aut...

Page 153: ... pullup digital driver and digital receiver disabled 0 Corresponding P0 n pin is configured for analog mode 1 Corresponding P0 n pin is not configured for analog mode SFR Definition 22 10 P0MDOUT Port 0 Output Mode Bit 7 6 5 4 3 2 1 0 Name P0MDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 P0MDOUT 7 0 Output Configuration Bits for P0 7 P0 0 respectively These bits are ignored if the ...

Page 154: ...analog special functions or GPIO should be skipped by the Crossbar 0 Corresponding P0 n pin is not skipped by the Crossbar 1 Corresponding P0 n pin is skipped by the Crossbar SFR Definition 22 12 P1 Port 1 Bit 7 6 5 4 3 2 1 0 Name P1 7 0 Type R W Reset 1 1 1 1 1 1 1 1 Bit Name Description Write Read 7 0 P1 7 0 Port 1 Data Sets the Port latch logic value or reads the Port pin logic state in Port ce...

Page 155: ... pullup digital driver and digital receiver disabled 0 Corresponding P1 n pin is configured for analog mode 1 Corresponding P1 n pin is not configured for analog mode SFR Definition 22 14 P1MDOUT Port 1 Output Mode Bit 7 6 5 4 3 2 1 0 Name P1MDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 P1MDOUT 7 0 Output Configuration Bits for P1 7 P1 0 respectively These bits are ignored if the ...

Page 156: ...analog special functions or GPIO should be skipped by the Crossbar 0 Corresponding P1 n pin is not skipped by the Crossbar 1 Corresponding P1 n pin is skipped by the Crossbar SFR Definition 22 16 P2 Port 2 Bit 7 6 5 4 3 2 1 0 Name P2 7 0 Type R W Reset 1 1 1 1 1 1 1 1 Bit Name Description Write Read 7 0 P2 7 0 Port 2 Data Sets the Port latch logic value or reads the Port pin logic state in Port ce...

Page 157: ... pullup digital driver and digital receiver disabled 0 Corresponding P2 n pin is configured for analog mode 1 Corresponding P2 n pin is not configured for analog mode SFR Definition 22 18 P2MDOUT Port 2 Output Mode Bit 7 6 5 4 3 2 1 0 Name P2MDOUT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 P2MDOUT 7 0 Output Configuration Bits for P2 7 P2 0 respectively These bits are ignored if the ...

Page 158: ...s or GPIO should be skipped by the Crossbar 0 Corresponding P2 n pin is not skipped by the Crossbar 1 Corresponding P2 n pin is skipped by the Crossbar SFR Definition 22 20 P3 Port 3 Bit 7 6 5 4 3 2 1 0 Name P3 0 Type R R R R R R R R W Reset 0 0 0 0 0 0 0 1 Bit Name Description Write Read 7 1 Unused Unused Don t Care 0000000b 0 P3 0 Port 3 Data Sets the Port latch logic value or reads the Port pin...

Page 159: ...n 22 21 P3MDOUT Port 3 Output Mode Bit 7 6 5 4 3 2 1 0 Name P3MDOUT 0 Type R R R R R R R R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 1 Unused Read 0000000b Write Don t Care 0 P3MDOUT 0 Output Configuration Bits for P3 0 0 P3 0 Output is open drain 1 P3 0 Output is push pull ...

Page 160: ...he USB Function Controller and Transceiver is Universal Serial Bus Specification 2 0 compliant Figure 23 1 USB0 Block Diagram Important Note This document assumes a comprehensive understanding of the USB Protocol Terms and abbreviations used in this document are defined in the USB Specification We encourage you to review the latest version of the USB Specification before proceeding Note The C8051T...

Page 161: ...n and the on chip pull up resistor if enabled appears on the D pin When bit SPEED 0 USB0 operates as a Low Speed USB function and the on chip pull up resistor if enabled appears on the D pin Bits4 0 of register USB0XCN can be used for Transceiver testing as described in SFR Definition 23 1 The pull up resistor is enabled only when VBUS is present see Section 11 1 2 VBUS Detection on page 61 for de...

Page 162: ... USB0 speed 0 USB0 operates as a Low Speed device If enabled the internal pull up resistor appears on the D line 1 USB0 operates as a Full Speed device If enabled the internal pull up resistor appears on the D line 4 3 PHYTST 1 0 Physical Layer Test Bits 00 Mode 0 Normal non test mode D X D X 01 Mode 1 Differential 1 Forced D 1 D 0 10 Mode 2 Differential 0 Forced D 0 D 1 11 Mode 3 Single Ended 0 F...

Page 163: ...nd point number Once the target endpoint number is written to the INDEX register the control status registers associated with the target endpoint may be accessed See the Indexed Registers section of Table 23 2 for a list of endpoint control status registers Important Note The USB clock must be active when accessing USB registers Figure 23 2 USB0 Register Access Scheme USB Controller FIFO Access In...

Page 164: ...a is valid 1 USB0 is busy access ing an indirect register USB0DAT register data is invalid 6 AUTORD USB0 Register Auto read Flag This bit is used for block FIFO reads 0 BUSY must be written manually for each USB0 indirect register read 1 The next indirect register read will automatically be initiated when software reads USB0DAT USBADDR bits will not be changed 5 0 USBADDR 5 0 USB0 Indirect Registe...

Page 165: ...ster address into the USBADDR bits in register USB0ADR 3 Write data to USB0DAT 4 Repeat Step 2 may be skipped when writing to the same USB0 register Read Procedure 1 Poll for BUSY USB0ADR 7 0 2 Load the target USB0 register address into the USBADDR bits in register USB0ADR 3 Write 1 to the BUSY bit in register USB0ADR steps 2 and 3 can be per formed in the same write 4 Poll for BUSY USB0ADR 7 0 5 ...

Page 166: ...ction Address 172 POWER 0x01 Power Management 174 FRAMEL 0x0C Frame Number Low Byte 175 FRAMEH 0x0D Frame Number High Byte 175 INDEX 0x0E Endpoint Index Selection 167 CLKREC 0x0F Clock Recovery Control 168 EENABLE 0x1E Endpoint Enable 186 FIFOn 0x20 0x23 Endpoints0 3 FIFOs 171 Indexed Registers E0CSR 0x11 Endpoint0 Control Status 184 EINCSRL Endpoint IN Control Status Low Byte 188 EINCSRH 0x12 End...

Page 167: ...7 6 5 4 3 2 1 0 Name EPSEL 3 0 Type R R R R R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 4 Unused Read 0000b Write don t care 3 0 EPSEL 3 0 Endpoint Select Bits These bits select which endpoint is targeted when indexed USB0 registers are accessed 0000 Endpoint 0 0001 Endpoint 1 0010 Endpoint 2 0011 Endpoint 3 0100 1111 Reserved ...

Page 168: ...ically not necessary in Low Speed mode Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are pres ent on the USB network This mode is not required or recommended in typical USB environments USB Register Address 0x0F Communication Speed USB Clock Full Speed Internal Oscillator Low Speed Internal Oscillator 8 USB Register Definition 23 5 CLKREC Clock Re...

Page 169: ...or Endpoints1 3 is configurable as IN OUT or both Split Mode half IN half OUT Figure 23 3 C8051T620 1 and C8051T320 1 2 3 USB FIFO Allocation Endpoint0 64 bytes Configurable as IN OUT or both Split Mode Free 64 bytes 0x0400 0x043F 0x0440 0x063F 0x0640 0x073F 0x0740 0x07BF 0x07C0 0x07FF User XRAM 1024 bytes 0x0000 0x03FF USB Clock Domain System Clock Domain Endpoint1 128 bytes Endpoint2 256 bytes E...

Page 170: ...the DIRSEL bit in the corresponding endpoint s EINCSRH register see SFR Definition 23 13 23 5 2 FIFO Double Buffering FIFO slots for Endpoints1 3 can be configured for double buffered mode In this mode the maximum packet size is halved and the FIFO may contain two packets at a time This mode is available for Endpoints1 3 When an endpoint is configured for split mode double buffering may be enabled...

Page 171: ...ations Endpoint Number Split Mode Enabled Maximum IN Packet Size Double Buffer Disabled Enabled Maximum OUT Packet Size Double Buffer Disabled Enabled 0 N A 64 1 N 128 64 Y 64 32 64 32 2 N 256 128 Y 128 64 128 64 3 N 512 256 Y 256 128 256 128 USB Register Definition 23 6 FIFOn USB0 Endpoint FIFO Access Bit 7 6 5 4 3 2 1 0 Name FIFODATA 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 FIFOD...

Page 172: ...er Hardware clears the UPDATE bit when the new address takes effect as described above USB Register Address 0x00 USB Register Definition 23 7 FADDR USB0 Function Address Bit 7 6 5 4 3 2 1 0 Name UPDATE FADDR 6 0 Type R R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 UPDATE Function Address Update Bit Set to 1 when software writes the FADDR register USB0 clears this bit to 0 when the new address take...

Page 173: ...r USB0 exits Suspend mode when any of the following occur 1 Resume signaling is detected or gener ated 2 Reset signaling is detected or 3 a device or USB reset occurs If suspended the internal oscil lator will exit Suspend mode upon any of the above listed events Resume Signaling USB0 will exit Suspend mode if Resume signaling is detected on the bus A Resume interrupt will be generated upon detect...

Page 174: ...annot set this bit to 1 0 USB0 enabled 1 USB0 inhibited All USB traffic is ignored 3 USBRST Reset Detect Read 0 Reset signaling is not present 1 Reset signaling detected on the bus Write Writing 1 to this bit forces an asynchronous USB0 reset 2 RESUME Force Resume Writing a 1 to this bit while in Suspend mode SUSMD 1 forces USB0 to generate Resume signaling on the bus a remote wakeup event Softwar...

Page 175: ...0 Bit Name Function 7 0 FRMEL 7 0 Frame Number Low Bits This register contains bits 7 0 of the last received frame number USB Register Definition 23 10 FRAMEH USB0 Frame Number High Bit 7 6 5 4 3 2 1 0 Name FRMEH 2 0 Type R R R R R R Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 3 Unused Read 00000b Write don t care 2 0 FRMEH 2 0 Frame Number High Bits This register contains bits 10 8 of the last rece...

Page 176: ...n 23 11 IN1INT USB0 IN Endpoint Interrupt Bit 7 6 5 4 3 2 1 0 Name IN3 IN2 IN1 EP0 Type R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 4 Unused Read 0000b Write don t care 3 IN3 IN Endpoint 3 Interrupt Pending Flag This bit is cleared when software reads the IN1INT register 0 IN Endpoint 3 interrupt inactive 1 IN Endpoint 3 interrupt active 2 IN2 IN Endpoint 2 Interrupt Pending Flag Thi...

Page 177: ...ag This bit is cleared when software reads the OUT1INT register 0 OUT Endpoint 3 interrupt inactive 1 OUT Endpoint 3 interrupt active 2 OUT2 OUT Endpoint 2 Interrupt pending Flag This bit is cleared when software reads the OUT1INT register 0 OUT Endpoint 2 interrupt inactive 1 OUT Endpoint 2 interrupt active 1 OUT1 OUT Endpoint 1 Interrupt pending Flag This bit is cleared when software reads the O...

Page 178: ...er 0 SOF interrupt inactive 1 SOF interrupt active 2 RSTINT Reset Interrupt pending Flag Set by hardware when Reset signaling is detected on the bus This bit is cleared when software reads the CMINT register 0 Reset interrupt inactive 1 Reset interrupt active 1 RSUINT Resume Interrupt pending Flag Set by hardware when Resume signaling is detected on the bus while USB0 is in sus pend mode This bit ...

Page 179: ... 4 Unused Read 0000b Write don t care 3 IN3E IN Endpoint 3 Interrupt Enable 0 IN Endpoint 3 interrupt disabled 1 IN Endpoint 3 interrupt enabled 2 IN2E IN Endpoint 2 Interrupt Enable 0 IN Endpoint 2 interrupt disabled 1 IN Endpoint 2 interrupt enabled 1 IN1E IN Endpoint 1 Interrupt Enable 0 IN Endpoint 1 interrupt disabled 1 IN Endpoint 1 interrupt enabled 0 EP0E Endpoint 0 Interrupt Enable 0 Endp...

Page 180: ...1 1 0 Bit Name Function 7 4 Unused Read 0000b Write don t care 3 OUT3E OUT Endpoint 3 Interrupt Enable 0 OUT Endpoint 3 interrupt disabled 1 OUT Endpoint 3 interrupt enabled 2 OUT2E OUT Endpoint 2 Interrupt Enable 0 OUT Endpoint 2 interrupt disabled 1 OUT Endpoint 2 interrupt enabled 1 OUT1E OUT Endpoint 1 Interrupt Enable 0 OUT Endpoint 1 interrupt disabled 1 OUT Endpoint 1 interrupt enabled 0 Un...

Page 181: ...interrupt is generated when 1 A data packet OUT or SETUP has been received and loaded into the Endpoint0 FIFO The OPRDY bit E0CSR 0 is set to 1 by hardware 2 An IN data packet has successfully been unloaded from the Endpoint0 FIFO and transmitted to the host INPRDY is reset to 0 by hardware 3 An IN transaction is completed this interrupt generated during the status stage of the transaction 4 Hardw...

Page 182: ...that it has serviced the OUT packet 23 10 2 Endpoint0 IN Transactions When a SETUP request is received that requires USB0 to transmit data to the host one or more IN requests will be sent by the host For the first IN transaction firmware should load an IN packet into the Endpoint0 FIFO and set the INPRDY bit E0CSR 1 An interrupt will be generated when an IN packet is transmitted successfully Note ...

Page 183: ...s reported to the host the host will send a zero length data packet signaling the end of the transfer Upon reception of the first OUT token for a particular control transfer Endpoint0 is said to be in Receive Mode In this mode only OUT tokens should be sent by the host to Endpoint0 The SUEND bit E0CSR 4 is set to 1 if a SETUP or IN token is received while Endpoint0 is in Receive Mode Endpoint0 wil...

Page 184: ...s read only bit to 1 when a control transaction ends before software has written 1 to the DATAEND bit Hardware clears this bit when software writes 1 to SSUEND 3 DATAEND Data End Bit Software should write 1 to this bit 1 When writing 1 to INPRDY for the last outgoing data packet 2 When writing 1 to INPRDY for a zero length data packet 3 When writ ing 1 to SOPRDY after servicing the last incoming d...

Page 185: ...bit in register EINCSRH When SPLIT 1 the corresponding endpoint FIFO is split and both IN and OUT pipes are available When SPLIT 0 the corresponding endpoint functions as either IN or OUT the endpoint direction is selected by the DIRSEL bit in register EINCSRH Endpoints1 3 can be disabled individually by the corresponding bits in the ENABLE register When an End point is disabled it will not respon...

Page 186: ...NCSRL 0 Upon reception of an IN token hardware will transmit the data clear the INPRDY bit and generate an interrupt Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero length packet to be transmitted upon reception of the next IN token A Bulk or Interrupt pipe can be shut down or Halted by writing 1 to the SDSTL bit EINCSRL 4 While SDSTL 1 hardware will respond to ...

Page 187: ...de the host will send one IN token data request per frame the location of data within each frame may vary Because of this it is recommended that double buffering be enabled for ISO IN endpoints Hardware will automatically reset INPRDY EINCSRL 0 to 0 when a packet slot is open in the endpoint FIFO Note that if double buffering is enabled for the target endpoint it is possible for firmware to load t...

Page 188: ...transmitted from the IN Endpoint FIFO The FIFO pointer is reset and the INPRDY bit is cleared If the FIFO contains mul tiple packets software must write 1 to FLUSH for each packet Hardware resets the FLUSH bit to 0 when the FIFO flush is complete 2 UNDRUN Data Underrun Bit The function of this bit depends on the IN Endpoint mode ISO Set when a zero length packet is sent after an IN token is receiv...

Page 189: ...fering disabled for the selected IN endpoint 1 Double buffering enabled for the selected IN endpoint 6 ISO Isochronous Transfer Enable This bit enables disables isochronous transfers on the current endpoint 0 Endpoint configured for bulk interrupt transfers 1 Endpoint configured for isochronous transfers 5 DIRSEL Endpoint Direction Select This bit is valid only when the selected FIFO is not split ...

Page 190: ...ble for two packets to be ready in the OUT FIFO at a time In this case hardware will set OPRDY to 1 immediately after firmware unloads the first packet and resets OPRDY to 0 A second interrupt will be generated in this case 23 13 2 Endpoints1 3 OUT Isochronous Mode When the ISO bit EOUTCSRH 6 is set to 1 the target endpoint operates in Isochronous ISO mode Once an endpoint has been configured for ...

Page 191: ...s the FLUSH bit to 0 when the flush is complete Note If data for the current packet has already been read from the FIFO the FLUSH bit should not be used to flush the packet Instead the FIFO should be read manually 3 DATERR Data Error Bit In ISO mode this bit is set by hardware if a received packet has a CRC or bit stuffing error It is cleared when software clears OPRDY This bit is only valid in IS...

Page 192: ...endpoint 6 ISO Isochronous Transfer Enable This bit enables disables isochronous transfers on the current endpoint 0 Endpoint configured for bulk interrupt transfers 1 Endpoint configured for isochronous transfers 5 0 Unused Read 000000b Write don t care USB Register Definition 23 24 EOUTCNTL USB0 OUT Endpoint Count Low Bit 7 6 5 4 3 2 1 0 Name EOCL 7 0 Type R Reset 0 0 0 0 0 0 0 0 Bit Name Functi...

Page 193: ...it 7 6 5 4 3 2 1 0 Name EOCH 1 0 Type R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 2 Unused Read 000000b Write don t care 1 0 EOCH 1 0 OUT Endpoint Count High Byte EOCH holds the upper 2 bits of the 10 bit number of data bytes in the last received packet in the current OUT endpoint FIFO This number is only valid while OPRDY 1 ...

Page 194: ...on arbitration logic and START STOP control and generation The SMBus peripheral can be fully driven by software i e software accepts rejects slave addresses and generates ACKs or hardware slave address recognition and automatic ACK generation can be enabled to minimize software overhead A block dia gram of the SMBus peripheral and the associated SFRs is shown in Figure 24 1 Figure 24 1 SMBus Block...

Page 195: ...from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave and multiple master devices on the same bus are supported If two or more masters attempt to initiate...

Page 196: ... the same time an arbitra tion scheme is employed to force one master to give up the bus The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW Since the bus is open drain the bus will be pulled LOW The master attempting the HIGH will detect a LOW SDA and lose the arbitration The winning master continues its transmission without interruption the losing m...

Page 197: ...at is transferred When hardware acknowledgement is disabled the point at which the interrupt is generated depends on whether the hard ware is acting as a data transmitter or receiver When a transmitter i e sending address data receiving an ACK this interrupt is generated after the ACK cycle so that software may read the received ACK value when receiving data i e receiving address data sending an A...

Page 198: ...r Equation 24 1 When the interface is operating as a master and SCL is not driven or extended by any other devices on the bus the typical SMBus bit rate is approximated by Equation 24 2 Equation 24 2 Typical SMBus Bit Rate Figure 24 4 shows the typical SCL generation described by Equation 24 2 Notice that THIGH is typically twice as large as TLOW The actual SCL output may vary due to other devices...

Page 199: ...timeouts see Section 24 3 4 SCL Low Timeout on page 196 The SMBus interface will force Timer 3 to reload while SCL is high and allow Timer 3 to count when SCL is low The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re enabling the SMBus SMBus Free Timeout detection can be enabled by setting the SMBFTE bit When this bit is set the bus will be consid...

Page 200: ...tup and hold times according to Table 24 2 0 SDA Extended Setup and Hold Times disabled 1 SDA Extended Setup and Hold Times enabled 3 SMBTOE SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is configured to Split Mode only the High Byte of the...

Page 201: ... set thus SCL is held low and the bus is stalled until software clears SI 24 4 2 1 Software ACK Generation When the EHACK bit in register SMB0ADM is cleared to 0 the firmware on the device must detect incom ing slave addresses and ACK or NACK the slave address and incoming data bytes As a receiver writing the ACK bit defines the outgoing ACK value as a transmitter reading the ACK bit indicates the...

Page 202: ...ted 0 No Start generated 1 When Configured as a Master initiates a START or repeated START 4 STO SMBus Stop Flag 0 No Stop condition detected 1 Stop condition detected if in Slave Mode or pend ing if in Master Mode 0 No STOP condition is transmitted 1 When configured as a Master causes a STOP condition to be transmit ted after the next ACK cycle Cleared by Hardware 3 ACKRQ SMBus Acknowledge Reques...

Page 203: ...ress mask means that bit will be treated as a don t care for comparison purposes Table 24 3 Sources for Hardware Changes to SMB0CN Bit Set by Hardware When Cleared by Hardware When MASTER A START is generated A STOP is generated Arbitration is lost TXMODE START is generated SMB0DAT is written before the start of an SMBus frame A START is detected Arbitration is lost SMB0DAT is not written before t...

Page 204: ...4 0x00 General Call 0x34 0x7E 0 0x34 0x35 0x34 0x7E 1 0x34 0x35 0x00 General Call 0x70 0x73 0 0x70 0x74 0x78 0x7C SFR Definition 24 3 SMB0ADR SMBus Slave Address Bit 7 6 5 4 3 2 1 0 Name SLV 6 0 GC Type R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 1 SLV 6 0 SMBus Hardware Slave Address Defines the SMBus Slave Address es for automatic hardware acknowledgement Only address bits which have a 1 i...

Page 205: ...are compared with an incoming address byte and which bits are ignored Any bit set to 1 in SLVM 6 0 enables compari sons with the corresponding bit in SLV 6 0 Bits set to 0 are ignored can be either 0 or 1 in the incoming address 0 EHACK Hardware Acknowledge Enable Enables hardware acknowledgement of slave address and received data bytes 0 Firmware must manually acknowledge all incoming address and...

Page 206: ...y being shifted in SMB0DAT always contains the last data byte present on the bus In the event of lost arbi tration the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT SFR Address 0xC2 SFR Definition 24 5 SMB0DAT SMBus Data Bit 7 6 5 4 3 2 1 0 Name SMB0DAT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 SMB0DAT 7 0 SMBus Data The SMB...

Page 207: ...ster in this transfer will be a transmitter during the address byte and a transmitter during all data bytes The SMBus interface gener ates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 0 WRITE The master then trans mits one or more bytes of serial data After each byte is t...

Page 208: ...priate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled Writing a 1 to the ACK bit generates an ACK writing a 0 generates a NACK Software should write a 0 to the ACK bit for the last data transfer to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated The interface will switc...

Page 209: ...ed the ACKRQ is set to 1 and an interrupt is generated after each received byte Software must write the ACK bit at that time to ACK or NACK the received byte With hardware ACK generation enabled the SMBus hardware will automatically generate the ACK NACK and then post the interrupt It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving th...

Page 210: ...ore SI is cleared an error condition may be generated if SMB0DAT is written following a received NACK while in slave transmitter mode The interface exits slave transmitter mode after receiving a STOP Note that the interface will switch to slave receiver mode if SMB0DAT is not written following a Slave Transmitter interrupt Figure 24 8 shows a typical slave read sequence Two transmitted data bytes ...

Page 211: ...ta byte into SMB0DAT 0 0 X 1100 End transfer with STOP 0 1 X End transfer with STOP and start another transfer 1 1 X Send repeated START 1 0 X 1110 Switch to Master Receiver Mode clear SI without writing new data to SMB0DAT 0 0 X 1000 Master Receiver 1000 1 0 X A master data byte was received ACK requested Acknowledge received byte Read SMB0DAT 0 0 1 1000 Send NACK to indicate last byte and send S...

Page 212: ...eceived address 0 0 1 0100 NACK received address 0 0 0 Reschedule failed transfer NACK received address 1 0 0 1110 0001 0 0 X A STOP was detected while addressed as a Slave Trans mitter or Slave Receiver Clear STO 0 0 X 1 1 X Lost arbitration while attempt ing a STOP No action required transfer complete aborted 0 0 0 0000 1 0 X A slave byte was received ACK requested Acknowledge received byte Read...

Page 213: ... X 1100 End transfer with STOP 0 1 X End transfer with STOP and start another transfer 1 1 X Send repeated START 1 0 X 1110 Switch to Master Receiver Mode clear SI without writing new data to SMB0DAT Set ACK for initial data byte 0 0 1 1000 Master Receiver 1000 0 0 1 A master data byte was received ACK sent Set ACK for next data byte Read SMB0DAT 0 0 1 1000 Set NACK to indicate next data byte as t...

Page 214: ...100 Reschedule failed transfer 1 0 X 1110 0001 0 0 X A STOP was detected while addressed as a Slave Trans mitter or Slave Receiver Clear STO 0 0 X 0 1 X Lost arbitration while attempt ing a STOP No action required transfer complete aborted 0 0 0 0000 0 0 X A slave byte was received Set ACK for next data byte Read SMB0DAT 0 0 1 0000 Set NACK for next data byte Read SMB0DAT 0 0 0 0000 Bus Error Cond...

Page 215: ...cess the buffered Receive register it is not possible to read data from the Transmit register With UART0 interrupts enabled an interrupt is generated each time a transmit is completed TI0 is set in SCON0 or a data byte has been received RI0 is set in SCON0 The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by so...

Page 216: ...ad on page 249 The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency Note that Timer 1 may be clocked by one of six sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 the external oscillator clock 8 or an external input T1 For any given Timer 1 clock source the UART0 baud rate is determined by Equation 25 1 A and Equation 25 1 B Equation 25 ...

Page 217: ...eginning of the stop bit time Data recep tion can begin any time after the REN0 Receive Enable bit SCON0 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if the following conditions are met RI0 must be logic 0 and if MCE0 is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latch...

Page 218: ... set at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the REN0 Receive Enable bit SCON0 4 is set to 1 After the stop bit is received the data byte will be loaded into the SBUF0 receive register if the following conditions are met 1 RI0 must be logic 0 and 2 if MCE0 is logic 1 the 9th bit must be logic 1 when MCE0 is logic 0 the state of the ...

Page 219: ...ned 8 bit address If the addresses match the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE0 bit to ignore all transmis s...

Page 220: ...h bit is logic 1 4 REN0 Receive Enable 0 UART0 reception disabled 1 UART0 reception enabled 3 TB80 Ninth Transmission Bit The logic level of this bit will be sent as the ninth transmission bit in 9 bit UART Mode Mode 1 Unused in 8 bit mode Mode 0 2 RB80 Ninth Receive Bit RB80 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 1 TI0 Transmit Inter...

Page 221: ...0 0 0 0 Bit Name Function 7 0 SBUF0 7 0 Serial Data Buffer Bits 7 0 MSB LSB This SFR accesses two registers a transmit shift register and a receive latch register When data is written to SBUF0 it goes to the transmit shift register and is held for serial transmission Writing a byte to SBUF0 initiates the transmission A read of SBUF0 returns the contents of the receive latch ...

Page 222: ... care Table 25 2 Timer Settings for Standard Baud Rates Using an External 22 1184 MHz Oscillator Frequency 22 1184 MHz Target Baud Rate bps Baud Rate Error Oscillator Divide Factor Timer Clock Source SCA1 SCA0 pre scale select 1 T1M1 Timer 1 Reload Value hex SYSCLK from External Osc 230400 0 00 96 SYSCLK XX2 1 0xD0 115200 0 00 192 SYSCLK XX 1 0xA0 57600 0 00 384 SYSCLK XX 1 0x40 28800 0 00 768 SYS...

Page 223: ...interrupt transmit complete or receive complete Note that if additional bytes are available in the Receive FIFO the RI1 bit cannot be cleared by software Figure 26 1 UART1 Block Diagram 26 1 Baud Rate Generator The UART1 baud rate is generated by a dedicated 16 bit timer which runs from the controller s core clock SYSCLK and has prescaler options of 1 4 12 or 48 The timer and prescaler options com...

Page 224: ...0xFF30 14400 14388 0 08 834 11 0xFE5F 9600 9600 0 0 1250 11 0xFD8F 2400 2400 0 0 5000 11 0xF63C 1200 1200 0 0 10000 11 0xEC78 SYSCLK 24 MHz 230400 230769 0 16 104 11 0xFFCC 115200 115385 0 16 208 11 0xFF98 57600 57692 0 16 416 11 0xFF30 28800 28777 0 08 834 11 0xFE5F 14400 14406 0 04 1666 11 0xFCBF 9600 9600 0 0 2500 11 0xFB1E 2400 2400 0 0 10000 11 0xEC78 1200 1200 0 0 20000 11 0xD8F0 SYSCLK 48 M...

Page 225: ...red using the SMOD1 register shown in SFR Definition Figure 26 2 shows the timing for a UART1 transaction without parity or an extra bit enabled Figure 26 3 shows the timing for a UART1 trans action with parity enabled PE1 1 Figure 26 4 is an example of a UART1 transaction when the extra bit is enabled XBE1 1 Note that the extra bit feature is not available when parity is enabled and the sec ond s...

Page 226: ...set to 1 If a transmission is in prog ress the data will remain in the Transmit Holding Register until the current transmission is complete The TI1 Transmit Interrupt Flag SCON1 1 will be set at the end of any transmission the beginning of the stop bit time If enabled an interrupt will occur when TI1 is set If the extra bit function is enabled XBE1 1 and the parity function is disabled PE1 0 the v...

Page 227: ...sor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its extra bit is logic 1 in a data byte the extra bit is always set to logic 0 Setting the MCE1 bit SMOD1 7 of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the extra bit is logic...

Page 228: ...RT receiver When disabled bytes can still be read from the receive FIFO 0 UART1 reception disabled 1 UART1 reception enabled 3 TBX1 Extra Transmission Bit The logic level of this bit will be assigned to the extra transmission bit when XBE1 1 This bit is not used when Parity is enabled 2 RBX1 Extra Receive Bit RBX1 is assigned the value of the extra bit when XBE1 1 If XBE1 is cleared to 0 RBX1 is a...

Page 229: ...ty is enabled 6 5 S1PT 1 0 Parity Type Bits 00 Odd 01 Even 10 Mark 11 Space 4 PE1 Parity Enable This bit activates hardware parity generation and checking The parity type is selected by bits S1PT1 0 when parity is enabled 0 Hardware parity is disabled 1 Hardware parity is enabled 3 2 S1DL 1 0 Data Length 00 5 bit data 01 6 bit data 10 7 bit data 11 8 bit data 1 XBE1 Extra Bit Enable When enabled t...

Page 230: ...initiates the transmission When data is written to SBUF1 it first goes to the Transmit Holding Register where it is held for serial transmission When the transmit shift register is available data is trans ferred into the shift regis ter and SBUF1 may be written again Reading SBUF1 retrieves data from the receive FIFO When read the old est byte in the receive FIFO is returned and removed from the F...

Page 231: ...te 0b 6 SB1RUN Baud Rate Generator Enable 0 Baud Rate Generator is disabled UART1 will not function 1 Baud Rate Generator is enabled 5 2 Reserved Read 0000b Must Write 0000b 1 0 SB1PS 1 0 Baud Rate Prescaler Select 00 Prescaler 12 01 Prescaler 4 10 Prescaler 48 11 Prescaler 1 SFR Definition 26 5 SBRLH1 UART1 Baud Rate Generator High Byte Bit 7 6 5 4 3 2 1 0 Name SBRLH1 7 0 Type R W Reset 0 0 0 0 0...

Page 232: ...s 0xB4 SFR Definition 26 6 SBRLL1 UART1 Baud Rate Generator Low Byte Bit 7 6 5 4 3 2 1 0 Name SBRLL1 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 SBRLL1 7 0 UART1 Baud Rate Reload Low Bits Low Byte of reload value for UART1 Baud Rate Generator ...

Page 233: ... than one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional gen eral purpose port I O pins can be used to select multiple slave devices in master mode Figure 27 1 SPI Block Diagram SFR Bus Data Path Control SFR Bus Write SPI0DAT Receive Data Buffer SPI0DAT 0 1 2 3 4 5 6 7 Shift Register SPI CONT...

Page 234: ... The SCK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 27 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register There are three possible modes that can be selected with these bits 1 NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode SPI0 operates in 3 wire mode and ...

Page 235: ...le the master SPI0 when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPI0CN 6 and SPIEN SPI0CN 0 are set to 0 to disable the SPI master device and a Mode Fault is generated MODF SPI0CN 5 1 Mode Fault will generate an interrupt if enabled SPI0 must be manually re enabled in software under these circumstances In multi master systems devices will typically default to ...

Page 236: ...configured as a slave SPI0 can be configured for 4 wire or 3 wire operation The default 4 wire slave mode is active when NSSMD1 SPI0CN 3 0 and NSSMD0 SPI0CN 2 1 In 4 wire mode the NSS signal is routed to a port pin and configured as a digital input SPI0 is enabled when NSS is logic 0 and disabled when NSS is logic 1 The bit counter is reset on a falling edge of NSS Note that the NSS sig nal must b...

Page 237: ...ck phases edge used to latch the data The CKPOL bit SPI0CFG 4 selects between an active high or active low clock Both master and slave devices must be configured to use the same clock phase and polarity SPI0 should be disabled by clearing the SPIEN bit SPI0CN 0 when changing the clock phase or polarity The clock and data line relationships for master mode are shown in Figure 27 5 For slave mode th...

Page 238: ... SCK CKPOL 0 CKPHA 0 SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 0 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MOSI NSS Must Remain High in Multi Master Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MOSI SCK CKPOL 0 CKPHA 0 SCK CKPOL 1 CKPHA 0 ...

Page 239: ... the system controller SPI0CN Control Register SPI0DAT Data Register SPI0CFG Configuration Register and SPI0CKR Clock Rate Register The four special function registers related to the operation of the SPI0 Bus are described in the following figures SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...

Page 240: ... the pin input 2 NSSIN NSS Instantaneous Pin Input This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched 1 SRMT Shift Register Empty valid in slave mode only This bit will be set to logic 1 when all data has been transferred in out of the shift register and there is no new information available to read from t...

Page 241: ...rrupt will be generated This bit is not automatically cleared by hardware and must be cleared by software 4 RXOVRN Receive Overrun Flag valid in slave mode only This bit is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register If SPI interrupts are enabled an interrupt wil...

Page 242: ...wing equation where SYSCLK is the system clock frequency and SPI0CKR is the 8 bit value held in the SPI0CKR register for 0 SPI0CKR 255 Example If SYSCLK 2 MHz and SPI0CKR 0x04 SFR Definition 27 4 SPI0DAT SPI0 Data Bit 7 6 5 4 3 2 1 0 Name SPI0DAT 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 SPI0DAT 7 0 SPI0 Transmit and Receive Data The SPI0DAT register is used to transmit and receive ...

Page 243: ...r Timing CKPHA 0 Figure 27 9 SPI Master Timing CKPHA 1 SCK T MCKH T MCKL MOSI T MIS MISO SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIH SCK T MCKH T MCKL MISO T MIH MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIS ...

Page 244: ... Slave Timing CKPHA 1 SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SEZ T SDZ SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SLH T SEZ T SDZ ...

Page 245: ... and Figure 27 11 TSE NSS Falling to First SCK Edge 2 x TSYSCLK ns TSD Last SCK Edge to NSS Rising 2 x TSYSCLK ns TSEZ NSS Falling to MISO Valid 4 x TSYSCLK ns TSDZ NSS Rising to MISO High Z 4 x TSYSCLK ns TCKH SCK High Time 5 x TSYSCLK ns TCKL SCK Low Time 5 x TSYSCLK ns TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK ns TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK ns TSOH SCK Shift Edge to MIS...

Page 246: ...0 The Clock Scale bits define a pre scaled clock from which Timer 0 and or Timer 1 may be clocked See SFR Definition 28 1 for pre scaled clock selection Timer 0 1 may then be configured to use this pre scaled clock signal or the system clock Timer 2 and Timer 3 may be clocked by the system clock the system clock divided by 12 or the external oscillator clock source divided by 8 Timer 0 and Timer 1...

Page 247: ...imer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 high byte uses the system clock 4 T2ML Timer 2 Low Byte Clock Select Selects the clock supplied to Timer 2 If Timer 2 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer 0 Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 low byte uses the syste...

Page 248: ... identically and Timer 1 is configured in the same manner as described for Timer 0 The TH0 register holds the eight MSBs of the 13 bit counter timer TL0 holds the five LSBs in bit positions TL0 4 TL0 0 The three upper bits of TL0 TL0 7 TL0 5 are indeterminate and should be masked out or ignored when reading As the 13 bit timer register increments and overflows from 0x1FFF all ones to 0x0000 the ti...

Page 249: ...olds the reload value When the counter in TL0 overflows from all ones to 0x00 the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded from TH0 If Timer 0 interrupts are enabled an interrupt will occur when the TF0 flag is set The reload value in TH0 is not changed TL0 must be initialized to the desired value before enabling the timer for the first count to be cor...

Page 250: ...1 interrupt Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mo...

Page 251: ...28 3 T0 Mode 3 Block Diagram TL0 8 bits TMOD 0 1 TCON TF0 TR0 TR1 TF1 IE1 IT1 IE0 IT0 Interrupt Interrupt 0 1 SYSCLK Pre scaled Clock TR1 TH0 8 bits T 1 M 1 T 1 M 0 C T 1 G A T E 1 G A T E 0 C T 0 T 0 M 1 T 0 M 0 TR0 GATE0 IN0PL XOR INT0 T0 Crossbar T0M ...

Page 252: ...is flag is set by hardware when an edge level of type defined by IT1 is detected It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge triggered mode 2 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit ...

Page 253: ... 4 T1M 1 0 Timer 1 Mode Select These bits select the Timer 1 operation mode 00 Mode 0 13 bit Counter Timer 01 Mode 1 16 bit Counter Timer 10 Mode 2 8 bit Counter Timer with Auto Reload 11 Mode 3 Timer 1 Inactive 3 GATE0 Timer 0 Gate Control 0 Timer 0 enabled when TR0 1 irrespective of INT0 logic level 1 Timer 0 enabled only when TR0 1 AND INT0 is active as defined by bit IN0PL in register IT01CF s...

Page 254: ...L0 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TL0 7 0 Timer 0 Low Byte The TL0 register is the low byte of the 16 bit Timer 0 SFR Definition 28 5 TL1 Timer 1 Low Byte Bit 7 6 5 4 3 2 1 0 Name TL1 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TL1 7 0 Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 ...

Page 255: ... 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TH0 7 0 Timer 0 High Byte The TH0 register is the high byte of the 16 bit Timer 0 SFR Definition 28 7 TH1 Timer 1 High Byte Bit 7 6 5 4 3 2 1 0 Name TH1 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TH1 7 0 Timer 1 High Byte The TH1 register is the high byte of the 16 bit Timer 1 ...

Page 256: ... as a 16 bit timer with auto reload Timer 2 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from 0xFFFF to 0x0000 the 16 bit value in the Timer 2 reload registers TMR2RLH and TMR2RLL is loaded into the Timer 2 register as shown in Figure 28 4 and the Timer 2 High Byte Overflow Flag TMR2CN 7 is ...

Page 257: ...0x00 the TF2L bit is set when TMR2L overflows from 0xFF to 0x00 When Timer 2 interrupts are enabled IE 5 an interrupt is generated each time TMR2H overflows If Timer 2 interrupts are enabled and TF2LEN TMR2CN 5 is set an interrupt is gener ated each time either TMR2L or TMR2H overflows When TF2LEN is enabled software must check the TF2H and TF2L flags to determine the source of the Timer 2 interru...

Page 258: ...Upon a falling edge of the low frequency oscillator the contents of Timer 2 TMR2H TMR2L are loaded into the Timer 2 reload registers TMR2RLH TMR2RLL and the TF2H flag is set By recording the difference between two successive timer capture values the LFO clock frequency can be determined with respect to the Timer 2 clock The Timer 2 clock should be much faster than the LFO to achieve an accurate re...

Page 259: ... overflows 4 TF2CEN Timer 2 Low Frequency Oscillator Capture Enable When set to 1 this bit enables Timer 2 Low Frequency Oscillator Capture Mode If TF2CEN is set and Timer 2 interrupts are enabled an interrupt will be generated on a falling edge of the low frequency oscillator output and the current 16 bit timer value in TMR2H TMR2L will be copied to TMR2RLH TMR2RLL 3 T2SPLIT Timer 2 Split Mode En...

Page 260: ...R Definition 28 10 TMR2RLH Timer 2 Reload Register High Byte Bit 7 6 5 4 3 2 1 0 Name TMR2RLH 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR2RLH 7 0 Timer 2 Reload Register High Byte TMR2RLH holds the high byte of the reload value for Timer 2 SFR Definition 28 11 TMR2L Timer 2 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR2L 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR2L 7 0 T...

Page 261: ...12 TMR2H Timer 2 High Byte Bit 7 6 5 4 3 2 1 0 Name TMR2H 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR2H 7 0 Timer 2 Low Byte In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the 8 bit high byte timer value ...

Page 262: ...wake up source other than the timer wakes the device from suspend mode it may take up to three timer clocks before the timer registers can be read or written During this time the STSYNC bit in register OSCICN will be set to 1 to indicate that it is not safe to read or write the timer reg isters Important Note In internal LFO 8 mode the divider for the internal LFO must be set to 1 for proper func ...

Page 263: ...t when TMR3L overflows from 0xFF to 0x00 When Timer 3 interrupts are enabled an interrupt is generated each time TMR3H over flows If Timer 3 interrupts are enabled and TF3LEN TMR3CN 5 is set an interrupt is generated each time either TMR3L or TMR3H overflows When TF3LEN is enabled software must check the TF3H and TF3L flags to determine the source of the Timer 3 interrupt The TF3H and TF3L interru...

Page 264: ...or the contents of Timer 3 TMR3H TMR3L are loaded into the Timer 3 reload registers TMR3RLH TMR3RLL and the TF3H flag is set By recording the difference between two successive timer capture values the LFO clock frequency can be determined with respect to the Timer 3 clock The Timer 3 clock should be much faster than the LFO to achieve an accurate reading This means that the LFO 8 should not be sel...

Page 265: ...Timer 3 Low Frequency Oscillator Capture Enable When set to 1 this bit enables Timer 3 Low Frequency Oscillator Capture Mode If TF3CEN is set and Timer 3 interrupts are enabled an interrupt will be generated on a falling edge of the low frequency oscillator output and the current 16 bit timer value in TMR3H TMR3L will be copied to TMR3RLH TMR3RLL 3 T3SPLIT Timer 3 Split Mode Enable When this bit i...

Page 266: ...FR Definition 28 15 TMR3RLH Timer 3 Reload Register High Byte Bit 7 6 5 4 3 2 1 0 Name TMR3RLH 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR3RLH 7 0 Timer 3 Reload Register High Byte TMR3RLH holds the high byte of the reload value for Timer 3 SFR Definition 28 16 TMR3L Timer 3 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR3L 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR3L 7 0 ...

Page 267: ...7 TMR3H Timer 3 High Byte Bit 7 6 5 4 3 2 1 0 Name TMR3H 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR3H 7 0 Timer 3 High Byte In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer 3 In 8 bit mode TMR3H contains the 8 bit high byte timer value ...

Page 268: ...e Software Timer High Speed Output Fre quency Output 8 to 11 Bit PWM or 16 Bit PWM each mode is described in Section 29 3 Capture Compare Modules on page 271 The external oscillator clock option is ideal for real time clock RTC functionality allowing the PCA to be clocked by a precision external oscillator while the inter nal oscillator drives the system clock The PCA is configured and controlled ...

Page 269: ...F to 0x0000 the Counter Overflow Flag CF in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Clearing the CIDL bit in the PC...

Page 270: ...operation mode of that module These event flags are always set when the trigger condition occurs Each of these flags can be individually selected to generate a PCA0 interrupt using the corresponding interrupt enable flag ECF for CF ECOV for COVF and ECCFn for each CCFn PCA0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor PCA0 interrupts a...

Page 271: ...sed to select the PCA capture compare module s operating mode Note that all modules set to use 8 9 10 or 11 bit PWM mode must use the same cycle length 8 11 bits Setting the ECCFn bit in a PCA0CPMn register enables the module s CCFn interrupt PCA0CN C F C R C C F 0 C C F 2 C C F 1 C C F 4 C C F 3 PCA0MD C I D L W D T E E C F C P S 1 C P S 0 W D L C K C P S 2 0 1 PCA Module 0 CCF0 PCA Module 1 CCF1...

Page 272: ...sitive edge on CEXn X X 1 0 0 0 0 A 0 X B XXX XX Capture triggered by negative edge on CEXn X X 0 1 0 0 0 A 0 X B XXX XX Capture triggered by any transition on CEXn X X 1 1 0 0 0 A 0 X B XXX XX Software Timer X C 0 0 1 0 0 A 0 X B XXX XX High Speed Output X C 0 0 1 1 0 A 0 X B XXX XX Frequency Output X C 0 0 0 1 1 A 0 X B XXX XX 8 Bit Pulse Width Modulator Note 7 0 C 0 0 E 0 1 A 0 X B XXX 00 9 Bit...

Page 273: ...led The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser vice routine and must be cleared by software Setting the ECOMn and MATn bits in the PCA0CPMn regis ter enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Cap ture Compare registers the low byte should always be written first Writing to ...

Page 274: ...utine and must be cleared by software Setting the TOGn MATn and ECOMn bits in the PCA0CPMn register enables the High Speed Output mode If ECOMn is cleared the associated pin will retain its state and not toggle on the next match event Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Cap ture Compare registers the low byte should always be written first Writing...

Page 275: ...ggled and the offset held in the high byte is added to the matched value in PCA0CPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCA0CPMn reg ister Note that the MATn bit should normally be set to 0 in this mode If the MATn bit is set to 1 the CCFn flag for the channel will be set when the 16 bit PCA0 counter and the 16 bit capture compare register for the chann...

Page 276: ...CEXn output will be reset see Figure 29 8 Also when the counter timer low byte PCA0L overflows from 0xFF to 0x00 PCA0CPLn is reloaded automatically with the value stored in the module s capture compare high byte PCA0CPHn without software intervention Setting the ECOMn and PWMn bits in the PCA0CPMn register and setting the CLSEL bits in register PCA0PWM to 00b enables 8 Bit Pulse Width Modulator mo...

Page 277: ...gister PCA0PWM The 9 10 or 11 bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis ter and setting the CLSEL bits in register PCA0PWM to the desired cycle length other than 8 bits If the MATn bit is set to 1 the CCFn flag for the module will be set each time a comparator match rising edge occurs The COVF flag in PCA0PWM can be used to detect the overflow falling edge w...

Page 278: ...le will be set each time a 16 bit comparator match rising edge occurs The CF flag in PCA0CN can be used to detect the overflow falling edge The duty cycle for 16 Bit PWM Mode is given by Equation 29 4 Important Note About Capture Compare Registers When writing a 16 bit value to the PCA0 Cap ture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit ...

Page 279: ...system 29 4 1 Watchdog Timer Operation While the WDT is enabled PCA counter is forced on Writes to PCA0L and PCA0H are not allowed PCA clock source bits CPS2 CPS0 are frozen PCA Idle control bit CIDL is frozen Module 4 is forced into software timer mode Writes to the Module 4 mode register PCA0CPM4 are disabled While the WDT is enabled writes to the CR bit will not change the PCA counter state the...

Page 280: ...le the WDT by writing a 0 to the WDTE bit Select the desired PCA clock source with the CPS2 CPS0 bits Load PCA0CPL4 with the desired WDT update offset value Configure the PCA Idle mode set CIDL if the WDT should be suspended while the CPU is in Idle mode Enable the WDT by setting the WDTE bit to 1 Reset the WDT timer by writing to PCA0CPH4 The PCA clock source and Idle mode select cannot be change...

Page 281: ...e operation of the PCA Table 29 3 Watchdog Timer Timeout Intervals1 System Clock Hz PCA0CPL4 Timeout Interval ms 12 000 000 255 65 5 12 000 000 128 33 0 12 000 000 32 8 4 24 000 000 255 32 8 24 000 000 128 16 5 24 000 000 32 4 2 1 500 0002 255 524 3 1 500 0002 128 264 2 1 500 0002 32 67 6 32 768 255 24 000 32 768 128 12 093 75 32 768 32 3 093 75 Notes 1 Assumes SYSCLK 12 as the PCA clock source an...

Page 282: ...nd must be cleared by software 3 CCF3 PCA Module 3Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF3 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service rou tine This bit is not automatically cleared by hardware and must be cleared by software 2 CCF2 PCA Module 2 Capture Compare Flag This bit is set by hardware when...

Page 283: ... the Watchdog Timer may not be disabled until the next system reset 0 Watchdog Timer Enable unlocked 1 Watchdog Timer Enable locked 4 Unused Read 0b Write Don t care 3 1 CPS 2 0 PCA Counter Timer Pulse Select These bits select the timebase source for the PCA counter 000 System clock divided by 12 001 System clock divided by 4 010 Timer 0 overflow 011 High to low transitions on ECI max rate system ...

Page 284: ...ng of the Cycle Overflow Flag COVF interrupt 0 COVF will not generate PCA interrupts 1 A PCA interrupt will be generated when COVF is set 5 COVF Cycle Overflow Flag This bit indicates an overflow of the 8th 9th 10th or 11th bit of the main PCA counter PCA0 The specific bit used for this flag depends on the setting of the Cycle Length Select bits The bit can be set by hardware or software but must ...

Page 285: ...re compare register cause the CCFn bit in PCA0MD register to be set to logic 1 2 TOGn Toggle Function Enable This bit enables the toggle function for PCA module n when set to 1 When enabled matches of the PCA counter with a module s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module oper ates in Frequency Output Mode 1 PWMn Pu...

Page 286: ...the PCA0L register the Watchdog Timer must first be disabled SFR Definition 29 6 PCA0H PCA Counter Timer High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0 15 8 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 PCA0 15 8 PCA Counter Timer High Byte The PCA0H register holds the high byte MSB of the 16 bit PCA Counter Timer Reads of this register will read the contents of a snaps...

Page 287: ...load value for 9 10 or 11 bit PWM mode The ARSEL bit in register PCA0PWM controls which register is accessed Note A write to this register will clear the module s ECOMn bit to a 0 SFR Definition 29 8 PCA0CPHn PCA Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPn 15 8 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 PCA0CPn 15 8 PCA Capture Module High Byte T...

Page 288: ...0 0 0 0 0 0 0 Bit Name Function 7 0 C2ADD 7 0 Write C2 Address Selects the target Data register for C2 Data Read and Data Write commands accord ing to the following list Address Name Description 0x00 DEVICEID Selects the Device ID Register read only 0x01 REVID Selects the Revision ID Register read only 0x02 DEVCTL Selects the C2 Device Control Register 0xDF EPCTL Selects the C2 EPROM Programming C...

Page 289: ...es Bit Name Function 7 0 DEVICEID 7 0 Device ID This read only register returns the 8 bit device ID 0x18 C8051T620 621 320 321 322 323 0x2C C8051T626 627 C2 Register Definition 30 3 REVID C2 Revision ID Bit 7 6 5 4 3 2 1 0 Name REVID 7 0 Type R W Reset Varies Varies Varies Varies Varies Varies Varies Varies Bit Name Function 7 0 REVID 7 0 Revision ID This read only register returns the 8 bit revis...

Page 290: ...r This register is used to halt the device for EPROM operations via the C2 interface Refer to the EPROM chapter for more information C2 Register Definition 30 5 EPCTL EPROM Programming Control Register Bit 7 6 5 4 3 2 1 0 Name EPCTL 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 EPCTL 7 0 EPROM Programming Control Register This register is used to enable EPROM programming via the C2 inte...

Page 291: ...OM operations C2 Register Definition 30 7 EPSTAT C2 EPROM Status Bit 7 6 5 4 3 2 1 0 Name WRLOCK RDLOCK ERROR Type R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 WRLOCK Write Lock Indicator Set to 1 if EPADDR currently points to a write locked address 6 RDLOCK Read Lock Indicator Set to 1 if EPADDR currently points to a read locked address 5 1 Unused Read 00000b Write don t care 0 ERROR...

Page 292: ...Name Function 7 0 EPADDR 15 8 C2 EPROM Address High Byte This register is used to set the EPROM address location during C2 EPROM oper ations C2 Register Definition 30 9 EPADDRL C2 EPROM Address Low Byte Bit 7 6 5 4 3 2 1 0 Name EPADDR 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 EPADDR 15 8 C2 EPROM Address Low Byte This register is used to set the EPROM address location during C2 EPRO...

Page 293: ...e CRC will begin The lower byte of the beginning address is always 0x00 When complete the 16 bit result will be available in CRC1 MSB and CRC0 LSB See Section 18 4 Program Memory CRC on page 115 C2 Register Definition 30 11 CRC1 CRC Byte 1 Bit 7 6 5 4 3 2 1 0 Name CRC 15 8 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 CRC 15 8 CRC Byte 1 A write to this register initiates a 32 bit CRC on th...

Page 294: ...0 Name CRC 23 16 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 CRC 23 16 CRC Byte 2 See Section 18 4 Program Memory CRC on page 115 C2 Register Definition 30 13 CRC3 CRC Byte 3 Bit 7 6 5 4 3 2 1 0 Name CRC 31 24 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 CRC 31 24 CRC Byte 3 See Section 18 4 Program Memory CRC on page 115 ...

Page 295: ...rmally RST and C2D pins In most applications external resistors are required to isolate C2 interface traffic from the user application when performing debug functions These external resistors are not necessary for production boards A typ ical isolation configuration is shown in Figure 30 1 Figure 30 1 Typical C2 Pin Sharing The configuration in Figure 30 1 assumes the following 1 The user input b ...

Page 296: ...ectrical Characteristics on page 38 Internal Oscillator Supply Current Table 7 8 Internal Low Frequency Oscillator Electrical Characteristics on page 39 Internal Oscillator Supply Current Table 7 10 ADC0 Electrical Characteristics on page 40 Power Supply Current Table 7 11 Temperature Sensor Electrical Characteristics on page 41 Slope and Offset Updated Section 15 Memory Organization on page 87 an...

Page 297: ...Rev 1 2 297 C8051T620 1 6 7 C8051T320 1 2 3 NOTES ...

Page 298: ...information included herein Additionally Silicon Laboratories assumes no responsibility for the function ing of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume a...

Page 299: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Silicon Laboratories C8051T626 B GM C8051T627 B GM ...

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