C8051T620/1/6/7 & C8051T320/1/2/3
198
Rev. 1.2
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 24.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “28. Timers” on page 246.
Equation 24.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 24.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 24.2.
Equation 24.2. Typical SMBus Bit Rate
Figure 24.4 shows the typical SCL generation described by Equation 24.2. Notice that T
HIGH
is typically
twice as large as T
LOW
. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 24.1.
Figure 24.4. Typical SMBus SCL Generation
Table 24.1. SMBus Clock Source Selection
SMBCS1
SMBCS0
SMBus Clock Source
0
0
Timer 0 Overflow
0
1
Timer 1 Overflow
1
0
Timer 2 High Byte Overflow
1
1
Timer 2 Low Byte Overflow
T
HighMin
T
LowMin
1
f
ClockSourceOverflow
----------------------------------------------
=
=
BitRate
f
ClockSourceOverflow
3
----------------------------------------------
=
SCL
Timer Source
Overflows
SCL High Timeout
T
Low
T
High
