manualshive.com logo in svg

Silicon Laboratories EFM32TG, Reference Manual

The Silicon Laboratories EFM32TG Reference Manual is a comprehensive user manual that provides detailed information about the product's features and functionality. Download this manual for free from 88.208.23.73:8080, and unleash the full potential of your EFM32TG device with our in-depth instructions and explanations.

Share
Download
background image

...the world's most energy friendly microcontrollers

2014-07-02 - Tiny Gecko Family - d0034_Rev1.20

230

www.silabs.com

16.3.4.3 Jitter in Transmitted Data

Internally  the  LEUART  module  uses  only  the  positive  edges  of  the  32.768  kHz  clock  (LFBCLK)  for
transmission and reception. Transmitted data will thus have jitter equal to the difference between the
optimal data set-up location and the closest positive edge on the 32.768 kHz clock. The jitter in on the
location data is set up by the transmitter will thus be no more than half a clock period according to the
optimal set-up location. The jitter in the period of a single baud output by the transmitter will never be
more than one clock period.

16.3.5 Data Reception

Data reception is enabled by setting RXEN in LEUARTn_CMD. When the receiver is enabled, it actively
samples the input looking for a transition from high to low indicating the start baud of a new frame. When
a start baud is found, reception of the new frame begins if the receive shift register is empty and ready
for new data. When the frame has been received, it is pushed into the receive buffer, making the shift
register ready for another frame of data, and the receiver starts looking for another start baud. If the
receive  buffer  is  full,  the  received  frame  remains  in  the  shift  register  until  more  space  in  the  receive
buffer is available.

If an incoming frame is detected while both the receive buffer and the receive shift register are full, the
data in the receive shift register is overwritten, and the RXOF interrupt flag in LEUARTn_IF is set to
indicate the buffer overflow.

The receiver can be disabled by setting the command bit RXDIS in LEUARTn_CMD. Any frame currently
being received when the receiver is disabled is discarded. Whether or not the receiver is enabled at a
given time can be read out from RXENS in LEUARTn_STATUS.

16.3.5.1 Receive Buffer Operation

When data becomes available in the receive buffer, the RXDATAV flag in LEUARTn_STATUS and the
RXDATAV  interrupt  flag  in  LEUARTn_IF  are  set.  Both  the  RXDATAV  status  flag  and  the  RXDATAV
interrupt flag are cleared by hardware when data is no longer available, i.e. when data has been read
out of the buffer.

Data  can  be  read  from  receive  buffer  using  either  LEUARTn_RXDATA  or  LEUARTn_RXDATAX.
LEUARTn_RXDATA  gives  access  to  the  8  least  significant  bits  of  the  received  frame,  while
LEUARTn_RXDATAX must be used to get access to the 9th, most significant bit. The latter register also
contains status information regarding the frame.

When a frame is read from the receive buffer using LEUARTn_RXDATA or LEUARTn_RXDATAX, the
frame  is  removed  from  the  buffer,  making  room  for  a  new  one.  If  an  attempt  is  done  to  read  more
frames from the buffer than what is available, the RXUF interrupt flag in LEUARTn_IF is set to signal
the underflow, and the data read from the buffer is undefined.

Frames  can  also  be  read  from  the  receive  buffer  without  removing  the  data  by  using
LEUARTn_RXDATAXP, which gives access to the frame in the buffer including control bits. Data read
from this register when the receive buffer is empty is undefined. No underflow interrupt is generated
by a read using LEUARTn_RXDATAXP, i.e. the RXUF interrupt flag is never set as a result of reading
from LEUARTn_RXDATAXP.

An overview of the operation of the receiver is shown in Figure 16.4 (p. 231) .

Summary of Contents for EFM32TG

Page 1: ...the 8 to 32 bit market with a combination of unmatched performance and ultra low power consumption in both active and sleep modes EFM32TG devices consume as little as 150 µA MHz in run mode and as little as 1 0 µA with a Real Time Counter running Brown out and full RAM and register retention EFM32TG s low energy consumption outperforms any other available 8 16 and 32 bit solution The EFM32TG inclu...

Page 2: ...ers get more out of the available energy in a variety of applications Ultra low energy EFM32TG microcontrollers are perfect for Gas metering Energy metering Water metering Smart metering Alarm and security systems Health and fitness applications Industrial and home automation 0 1 2 3 4 1 2 EFM32TG Development Because EFM32TG use the Cortex M3 CPU embedded designers benefit from the largest develop...

Page 3: ...egister where x denotes the port instance A B Bit Fields Registers contain one or more bit fields which can be 1 to 32 bits wide Multi bit fields are denoted with x y where x is the start bit and y is the end bit Address The address for each register can be found by adding the base address of the module found in the Memory Map and the offset address for the register found in module Register Map Ac...

Page 4: ...egisters denoted with X have an unknown reset value and need to be initialized before use Note that before these registers are initialized read modify write operations might result in undefined register values Pin Connections Pin connections are given as a module prefix followed by a short pin name USn_TX USARTn TX pin The pin locations referenced in this document are given in the device specific ...

Page 5: ...e 150 µA MHz 3 V Run Mode with code executed from flash 32 16 8 4 KB Flash 4 2 KB RAM Up to 56 General Purpose I O pins Configurable push pull open drain pull up down input filter drive strength Configurable peripheral I O locations 16 asynchronous external interrupts Output state retention and wake up from Shutoff Mode 8 Channel DMA Controller Alternate primary descriptors with scatter gather pin...

Page 6: ...to 3 Operational Amplifiers Supports rail to rail inputs and outputs Programmable gain 2 Analog Comparator Programmable speed current Capacitive sensing with up to 8 inputs Supply Voltage Comparator Ultra low power sensor interface Autonomous sensor monitoring in Deep Sleep Mode Wide range of sensors supported including LC sensors and capacitive buttons Ultra efficient Power on Reset and Brown Out...

Page 7: ...w Energy UART Watchdog Oscillator ADC DAC DMA Controller Debug Interface External Interrupts Pin Reset USART I2 C AES Tiny Gecko Operational Amplifier Analog Comparator Figure 3 2 Energy Mode Indicator 0 1 2 3 4 Note In the energy mode indicator the numbers indicates Energy Mode i e EM0 EM4 3 4 Energy Modes There are five different Energy Modes EM0 EM4 in the EFM32TG see Table 3 1 p 8 The EFM32TG ...

Page 8: ...y Mode 3 Stop Mode In EM3 the low frequency oscillator is disabled but there is still full CPU and RAM retention as well as Power on Reset Pin reset EM4 wake up and Brown out Detection with a consumption of only 0 6 µA The low power ACMP asynchronous external interrupt PCNT and I 2 C can wake up the device Even in this mode the wake up time is a few microseconds 0 1 2 3 4 EM4 Energy Mode 4 Shutoff...

Page 9: ... 4 2 1 2 12 Y Y 3 QFP48 225F8 8 2 37 2 1 1 2 6 1 1 1 1 1 4 2 1 2 12 Y Y 3 BGA48 225F16 16 4 37 2 1 1 2 6 1 1 1 1 1 4 2 1 2 12 Y Y 3 BGA48 225F32 32 4 37 2 1 1 2 6 1 1 1 1 1 4 2 1 2 12 Y Y 3 BGA48 230F8 8 2 56 2 1 1 2 6 1 1 1 1 1 8 2 2 2 16 Y Y 3 QFN64 230F16 16 4 56 2 1 1 2 6 1 1 1 1 1 8 2 2 2 16 Y Y 3 QFN64 230F32 32 4 56 2 1 1 2 6 1 1 1 1 1 8 2 2 2 16 Y Y 3 QFN64 232F8 8 2 53 2 1 1 2 6 1 1 1 1 1...

Page 10: ...ly number is read from PID0 and PID1 registers The minor revision number is extracted from the PID2 and PID3 registers as illustrated in Figure 3 3 p 10 The Fam 5 2 and Fam 1 0 must be combined to complete the chip family number while the Minor Rev 7 4 and Minor Rev 3 0 must be combined to form the complete revision number Figure 3 3 Revision Number Extraction PID1 0xE00FFFE4 31 4 3 0 PID0 0xE00FF...

Page 11: ...le meeting low cost requirements and low power consumption The ARM Cortex M3 implemented is revision r2p1 4 2 Features Harvard Architecture Separate data and program memory buses No memory bottleneck as for a single bus system 3 stage pipeline Thumb 2 instruction set Enhanced levels of performance energy efficiency and code density Single cycle multiply and efficient divide instructions 32 bit mul...

Page 12: ...ices have up to 23 interrupt request lines IRQ which are connected to the Cortex M3 Each of these lines shown in Table 4 1 p 12 are connected to one or more interrupt flags in one or more modules The interrupt flags are set by hardware on an interrupt condition It is also possible to set clear the interrupt flags through the IFS IFC registers Each interrupt flag is then qualified with its own inte...

Page 13: ...rgy friendly microcontrollers 2014 07 02 Tiny Gecko Family d0034_Rev1 20 13 www silabs com IRQ Source 10 TIMER1 11 USART1_RX 12 USART1_TX 13 LESENSE 14 LEUART0 15 LETIMER0 16 PCNT0 17 RTC 18 CMU 19 VCMP 20 LCD 21 MSC 22 AES ...

Page 14: ...e data restore time penalty and the DMA ensures fast autonomous transfers with predictable response time 5 1 Introduction The EFM32TG contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space A multilayer AHB bus matrix using a Round robin arbitration scheme connects the master bus interfaces to the AHB slaves Figure 5 1 p 15 The bus matrix allows several AHB s...

Page 15: ... com Figure 5 1 EFM32TG Bus System Cortex AHB Multilayer Bus Matrix DCode System DMA Flash RAM AES AHB APB Bridge ICode Peripheral 0 Peripheral n 5 2 Functional Description The memory segments are mapped together with the internal segments of the Cortex M3 into the system memory map shown by Figure 5 2 p 16 ...

Page 16: ...MA 5 2 1 Bit banding The SRAM bit band alias and peripheral bit band alias regions are located at 0x22000000 and 0x42000000 respectively Read and write operations to these regions are converted into masked single bit reads and atomic single bit writes to the embedded SRAM and peripherals of the EFM32TG The standard approach to modify a single register or SRAM bit in the aliased regions requires so...

Page 17: ...he AHB peripheral AES does not support bit banding 5 2 2 Peripherals The peripherals are mapped into the peripheral memory segment each with a fixed size address range according to Table 5 1 p 17 Table 5 2 p 18 and Table 5 3 p 19 Table 5 1 Memory System Core Peripherals Core peripherals Address range Peripheral 0x400E0400 0x41FFFFFF Reserved 0x400E0000 0x400E03FF AES 0x400CC400 0x400FFFFF Reserved...

Page 18: ...e Peripheral 0x4008A400 0x400BFFFF Reserved 0x4008C000 0x4008C3FF LESENSE 0x4008A000 0x4008A3FF LCD 0x40088400 0x40089FFF Reserved 0x40088000 0x400883FF WDOG 0x40086C00 0x40087FFF Reserved 0x40086000 0x400863FF PCNT0 0x40084800 0x40085FFF Reserved 0x40084000 0x400843FF LEUART0 0x40082400 0x40083FFF Reserved 0x40082000 0x400823FF LETIMER0 0x40080400 0x40081FFF Reserved 0x40080000 0x400803FF RTC ...

Page 19: ...ADC0 0x40001800 0x40001FFF Reserved 0x40001400 0x400017FF ACMP1 0x40001000 0x400013FF ACMP0 0x40000400 0x40000FFF Reserved 0x40000000 0x400003FF VCMP 5 2 3 Bus Matrix The Bus Matrix connects the memory segments to the bus masters Code CPU instruction or data fetches from the code space System CPU read and write to the SRAM and peripherals DMA Access to SRAM Flash and peripherals 5 2 3 1 Arbitratio...

Page 20: ... 2 Nslave cycles x fHFCORECLK fHFPERCLK 5 4 where Nslave cycles is the number of wait cycles introduced by the slave For general register access Nslave cycles 1 More details on clocks and prescaling can be found in Chapter 11 p 99 5 3 Access to Low Energy Peripherals Asynchronous Registers 5 3 1 Introduction The Low Energy Peripherals are capable of running when the high frequency oscillator and c...

Page 21: ...t is not required to wait until the relevant flag in the SYNCBUSY register is cleared after writing a register E g EM2 can be entered immediately after writing a register See Figure 5 3 p 21 for a more detailed overview of the write operation Figure 5 3 Write operation to Low Energy Peripherals Register 0 Register 1 Register n Synchronizer 0 Synchronizer 1 Synchronizer n Register 0 Sync Register 1...

Page 22: ...t the write operation is complete This is not necessarily the case Please refer to the SYNCBUSY register for correct status of the write operation to the Low Energy Peripheral Figure 5 4 Read operation from Low Energy Peripherals Register 0 Register 1 Register n Synchronizer 0 Synchronizer 1 Synchronizer n Register 0 Sync Register 1 Sync Register n Sync Freeze Core Clock Low Frequency Clock Low Fr...

Page 23: ...dually powered down when not in use Data retention of the entire memory in EM0 to EM3 5 6 Device Information DI Page The DI page contains calibration values a unique identification number and other useful data See the table below for a complete overview Table 5 4 Device Information Page Contents DI Address Register Description 0x0FE08020 CMU_LFRCOCTRL Register reset value 0x0FE08028 CMU_HFRCOCTRL ...

Page 24: ...0 Tuning for the 6 6 MHZ AUXHFRCO band 0x0FE081D6 AUXHFRCO_CALIB_BAND_11 7 0 Tuning for the 11 MHZ AUXHFRCO band 0x0FE081D7 AUXHFRCO_CALIB_BAND_14 7 0 Tuning for the 14 MHZ AUXHFRCO band 0x0FE081D8 AUXHFRCO_CALIB_BAND_21 7 0 Tuning for the 21 MHZ AUXHFRCO band 0x0FE081D9 AUXHFRCO_CALIB_BAND_28 7 0 Tuning for the 28 MHZ AUXHFRCO band 0x0FE081DC HFRCO_CALIB_BAND_1 7 0 Tuning for the 1 2 MHZ HFRCO ba...

Page 25: ... a 2 pin serial wire debug SWD interface In addition there is also a Serial Wire Viewer pin which can be used to output profiling information data trace and software generated messages For more technical information about the debug interface the reader is referred to ARM Cortex M3 Technical Reference Manual ARM CoreSight Components Technical Reference Manual ARM Debug Interface v5 Architecture Spe...

Page 26: ...ugger before doing current consumption measurements 6 4 Debug Lock and Device Erase The debug access to the Cortex M3 is locked by clearing the Debug Lock Word DLW and resetting the device see Section 7 3 2 p 32 When debug access is locked the debug interface remains accessible but the connection to the Cortex M3 core and the whole bus system is blocked as shown in Figure 6 2 p 27 This mechanism i...

Page 27: ...re reset and debug access through the AHB AP is enabled The operation takes 40 ms to complete Note that the SRAM contents will also be deleted during a device erase while the UD page is not erased Even if the device is not locked the can device can be erased through the AAP using the above procedure during the AAP window This can be useful if the device has been programmed with code that e g disab...

Page 28: ... to 0 More information in Section 2 1 p 3 1 SYSRESETREQ 0 W1 System Reset Request A system reset request is generated when set to 1 This register is write enabled from the AAP_CMDKEY register 0 DEVICEERASE 0 W1 Erase the Flash Main Block SRAM and Lock Bits When set all data and program code in the main block is erased the SRAM is cleared and then the Lock Bit LB page is erased This also includes t...

Page 29: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name ERASEBUSY Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 ERASEBUSY 0 R Device Erase Command Status This bit is set when a device erase is executing 6 6 4 AAP_IDR AAP Identification Register Offset Bit Position 0x0FC 31 30 29 28 27 26 25...

Page 30: ... capabilities to the requirements at hand How The MSC integrates a low energy Flash IP with a charge pump enabling minimum energy consumption while eliminating the need for external programming voltage to erase the memory An easy to use write and erase interface is supported by an internal fixed frequency oscillator and autonomous flash timing and control reduces software complexity while not usin...

Page 31: ...r and internal timers for precise and autonomous Flash timing General purpose timers are not occupied during Flash erase and write operations Configurable interrupt erase abort Improved interrupt predictability Memory and bus fault control Security features Lockable debug access Page lock bits User data lock bits End of write and end of erase interrupts 7 3 Functional Description The size of the m...

Page 32: ...n This is the user data page in the information block The page can be erased and written by software The page is erased by the ERASEPAGE command of the MSC_WRITECMD register Note that the page is not erased by a device erase operation The device erase operation is described in Section 6 4 p 26 7 3 2 Lock Bits LB Page Description This page contains the following information Debug Lock Word DLW User...

Page 33: ... When changing to a lower frequency the MODE field of the MSC_READCTRL register can be set to WS0 or WS0SCBTP but only after the frequency transition is completed If the HFRCO is used wait until the oscillator is stable on the new frequency Otherwise the behavior is unpredictable 7 3 4 2 Zero Wait state Access At 16 MHz and below read operations from flash may be performed without any wait states ...

Page 34: ...n RAM outside the code space are not cached If the address matches the cache lookup logic and SRAM is enabled Otherwise the cache is bypassed and the access is forwarded to the memory system The cache is then updated when the memory access completes The access filter also disables cache updates for interrupt context accesses if caching in interrupt context is disabled The performance counters when...

Page 35: ...ctors can also be put in RAM to reduce current consumption even further 7 3 5 Erase and Write Operations The AUXHFRCO is used for timing during flash write and erase operations To achieve correct timing the MSC_TIMEBASE register has to be configured according to the settings in CMU_AUXHFRCOCTRL BASE in MSC_TIMEBASE defines how many AUXCLK cycles 1 there is in 1 us or 5 us depending on the configur...

Page 36: ...afely write them in the same flash word this method can be used Write 0xFFFFAAAA word in flash becomes 0xFFFFAAAA Write 0x5555FFFF word in flash becomes 0x5555AAAA Note During a write or erase flash read accesses will be stalled effectively halting code execution from flash Code execution continues upon write erase completion Code residing in RAM may be executed during a write erase operation Note...

Page 37: ...t Enable Register 0x03C MSC_LOCK RW Configuration Lock Register 0x040 MSC_CMD W1 Command Register 0x044 MSC_CACHEHITS R Cache Hits Performance Counter 0x048 MSC_CACHEMISSES R Cache Misses Performance Counter 0x050 MSC_TIMEBASE RW Flash Write and Erase Timebase 7 5 Register Description 7 5 1 MSC_CTRL Memory System Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 38: ...re clock is 14 MHz from the HFRCO but the MODE field of MSC_READCTRL register is set to WS1 This is because the HFRCO may produce a frequency above 16 MHz before it is calibrated If the HFRCO is used as clock source wait until the oscillator is stable on the new frequency to avoid unpredictable behavior Value Mode Description 0 WS0 Zero wait states inserted in fetch or read transfers 1 WS1 One wai...

Page 39: ...Trigger Functions like MSC_CMD_WRITEONCE but will set MSC_STATUS_WORDTIMEOUT if no new data is written to MSC_WDATA within the 30 µs timeout 3 WRITEONCE 0 W1 Word Write Once Trigger Start write of the first word written to MSC_WDATA then add 4 to ADDR and write the next word if available within a 30 µs timeout When ADDR is incremented past the page boundary ADDR is set to the base of the page 2 WR...

Page 40: ...gister is not retained when entering EM2 or lower energy modes 7 5 7 MSC_STATUS Status Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 1 0 0 0 Access R R R R R R R Name PCRUNNING ERASEABORTED WORDTIMEOUT WDATAREADY INVADDR LOCKED BUSY Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with fut...

Page 41: ...10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access R R R R Name CMOF CHOF WRITE ERASE Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 CMOF 0 R Cache Misses Overflow Interrupt Flag Set when MSC_CACHEMISSES overflows 2 CHOF 0 R Cache Hits Overflow Interrupt Flag Set when MSC_CACHEHITS overflows 1 WRITE ...

Page 42: ...Cache Misses Overflow Interrupt Clear Clear the CMOF interrupt flag 2 CHOF 0 W1 Cache Hits Overflow Interrupt Clear Clear the CHOF interrupt flag 1 WRITE 0 W1 Write Done Interrupt Clear Clear the write done bit 0 ERASE 0 W1 Erase Done Interrupt Clear Clear the erase done bit 7 5 11 MSC_IEN Interrupt Enable Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 43: ...access When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 MSC registers are unlocked LOCKED 1 MSC registers are locked Write Operation LOCK 0 Lock MSC registers UNLOCK 0x1B71 Unlock MSC registers 7 5 13 MSC_CMD Command Register Offset Bit Position 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 44: ... cache performance for a particular code section 7 5 15 MSC_CACHEMISSES Cache Misses Performance Counter Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000 Access R Name CACHEMISSES Bit Name Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section...

Page 45: ... 5 us should only be used with 1 MHz AUXHFRCO band Value Mode Description 0 1US TIMEBASE period is 1 us 1 5US TIMEBASE period is 5 us 15 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 0 BASE 0x10 RW Timebase used by MSC to time flash writes and erases Should be set to the number of full AUX clock cycles in the period given by MSC...

Page 46: ... Introduction The Direct Memory Access DMA controller performs memory operations independently of the CPU This has the benefit of reducing the energy consumption and the workload of the CPU and enables the system to stay in low energy modes for example when moving data from the USART to RAM The DMA controller uses the PL230 µDMA controller licensed from ARM 1 Each of the PL230s channels on the EFM...

Page 47: ...ransfer completion Data transfer to from LEUART in EM2 is supported by the DMA providing extremely low energy consumption while performing UART communications 8 3 Block Diagram An overview of the DMA and the modules it interacts with is shown in Figure 8 1 p 47 Figure 8 1 DMA Block Diagram Interrupts APB block APB memory mapped registers AHB block AHB Lite master interface DMA control block DMA Co...

Page 48: ... p 58 In addition to the basic transfer mode the DMA Controller also supports two advanced transfer modes ping pong and scatter gather Ping pong transfers are ideally suited for streaming data for high speed peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately while the processor core is still processing the previous ones and similarly for outgoing...

Page 49: ...r always performs sequences of 2 R transfers until N 2 R remain to be transferred The controller performs the remaining N transfers at the end of the DMA cycle You store the value of the R_power bits in the channel control data structure See Section 8 4 3 3 p 61 for more information about the location of the R_power bits in the data structure 8 4 2 2 Priority When the controller arbitrates it dete...

Page 50: ...r polls all the DMA channels that are available Figure 8 2 p 50 shows the process it uses to determine which DMA transfer to perform next Figure 8 2 Polling flowchart Start polling Is there a channel request Are any channel requests using a high priority level Start DMA transfer Yes Yes Select channel that has the lowest channel number and is set to high priority level Select channel that has the ...

Page 51: ...roller to use either the primary or the alternate data structure After you enable the channel C and the controller receives a request for this channel then the flow for this DMA cycle is as follows 1 The controller performs 2 R transfers If the number of transfers remaining becomes zero then the flow continues at step 3 p 51 2 The controller arbitrates if a higher priority channel is requesting se...

Page 52: ...tion Figure 8 3 Ping pong example Task A Request Request Task A Primary cycle_ctrl b011 2R 4 N 6 dma_done C Task B Request Request Task B Alternate cycle_ctrl b011 2R 4 N 12 dma_done C Request Task C Request Task C Primary cycle_ctrl b011 2R 2 N 2 dma_done C Task D Request Request Task D Alternate cycle_ctrl b011 2R 4 N 5 dma_done C Task E Request Task E Primary cycle_ctrl b011 2R 4 N 7 dma_done C...

Page 53: ...r receives a new request for the channel and it has the highest priority then task C commences Task C 13 The controller performs two DMA transfers 14 The controller sets dma_done C HIGH for one HFCORECLK cycle and enters the arbitration process After task C completes the host processor can configure the primary data structure for task E After the controller receives a new request for the channel a...

Page 54: ...o program the alternate data structure Table 8 4 p 54 lists the fields of the channel_cfg memory location for the primary data structure that you must program with constant values and those that can be user defined Table 8 4 channel_cfg for a primary data structure in memory scatter gather mode Bit Field Value Description Constant value fields 31 30 dst_inc b10 Configures the controller to use wor...

Page 55: ...erate in memory scatter gather mode by setting cycle_ctrl to b100 Because a data structure for a single channel consists of four words then you must set 2 R to 4 In this example there are four tasks and therefore N is set to 16 2 The host processor writes the data structure for tasks A B C and D to the memory locations that the primary src_data_end_ptr specifies 3 The host processor enables the ch...

Page 56: ...iority then it performs another four DMA transfers using the primary data structure It then immediately starts a DMA cycle using the alternate data structure without re arbitrating The controller continues to switch from primary to alternate to primary until either the host processor configures the alternate data structure for a basic cycle it reads an invalid data structure Note After the control...

Page 57: ...DMA transfer that the alternate channel control data structure specifies 1 Configure primary to enable the copy A B C and D operations cycle_ctrl b110 2R 4 N 16 Initialization 2 Write the primary source data in memory using the structure shown in the following table cycle_ctrl b111 2R 4 N 3 cycle_ctrl b111 2R 2 N 8 cycle_ctrl b111 2R 8 N 5 cycle_ctrl b001 2R 4 N 4 src_data_end_ptr dst_data_end_ptr...

Page 58: ...st priority then the process continues with Primary copy D 10 The controller performs four DMA transfers These transfers write the alternate data structure for task D 11 The controller sets the cycle_ctrl bits of the primary data structure to b000 to indicate that this data structure is now invalid Task D 12 The controller performs task D using a basic cycle 13 The controller sets dma_done C HIGH ...

Page 59: ...he elements in the structure and therefore the base address must be at 0xXXXXXX00 You can configure the base address for the primary data structure by writing the appropriate value in the DMA_CTRLBASE register You do not need to set aside the full 256 bytes if all dma channels are not used or if all alternate descriptors are not used If for example only 4 channels are used and they only need the p...

Page 60: ...d Pointer Destination End Pointer Control Unused 0x0F0 0x0F4 0x0F8 0x00C 0x01C 0x07C 0x08C 0x09C 0x0FC Primary data structure Alternate data structure The controller uses the system memory to enable it to access two pointers and the control information that it requires for each channel The following subsections will describe these 32 bit memory locations and how the controller calculates the DMA t...

Page 61: ...transfer the channel_cfg memory location provides the control information for the controller Figure 8 8 p 61 shows the bit assignments for this memory location Figure 8 8 channel_cfg bit assignments 31 21 20 13 4 0 dst_inc src_prot_ctrl R_power n_minus_1 next_useburst 30 29 28 27 26 25 24 23 dst_size src_size src_inc dst_prot_ctrl 18 17 cycle_ctrl 3 14 2 Table 8 9 p 61 lists the bit assignments fo...

Page 62: ...e size of the source data b00 byte b01 halfword b10 word b11 reserved 23 21 dst_prot_ctrl Set the bits to control the state of HPROT when the controller writes the destination data Bit 23 This bit has no effect on the DMA Bit 22 This bit has no effect on the DMA Bit 21 Controls the state of HPROT as follows 0 HPROT is LOW and the access is non privileged 1 HPROT is HIGH and the access is privilege...

Page 63: ...e value of the chnl_useburst_set C bit If the chnl_useburst_set C bit is 0 then for all the remaining DMA cycles in the peripheral scatter gather transaction the controller responds to requests on dma_req and dma_sreq when it performs a DMA cycle that uses an alternate data structure 1 the controller sets the chnl_useburst_set C bit to a 1 Therefore for the remaining DMA cycles in the peripheral s...

Page 64: ...rc_inc specifies and then subtracts the resulting value from the source data end pointer Similarly to calculate the destination address of a DMA transfer it performs a left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies and then subtracts the resulting value from the destination end pointer Depending on the value of src_inc and dst_inc the source address and destin...

Page 65: ...trl 0 2 R_power b11 1 This value is the result of count being shifted left by the value of dst_inc 2 After the controller completes the DMA cycle it invalidates the channel_cfg memory location by clearing the cycle_ctrl field 8 4 4 Interaction with the EMU The DMA interacts with the Energy Management Unit EMU to allow transfers from e g the LEUART to occur in EM2 The EMU can wake up the DMA suffic...

Page 66: ...size b01 halfword transfer size iii src_inc b11 no address increment for source iv src_size 01 halfword transfer size v dst_prot_ctrl 000 no cache buffer privilege vi src_prot_ctrl 000 no cache buffer privilege vii R_power b0000 arbitrate after each DMA transfer viii n_minus_1 d20 transfer 21 halfwords ix next_useburst b0 not applicable x cycle_ctrl b001 basic operating mode 3 Enable the DMA a Wri...

Page 67: ...x028 DMA_CHENS RW1 Channel Enable Set Register 0x02C DMA_CHENC W1 Channel Enable Clear Register 0x030 DMA_CHALTS RW1 Channel Alternate Set Register 0x034 DMA_CHALTC W1 Channel Alternate Clear Register 0x038 DMA_CHPRIS RW1 Channel Priority Set Register 0x03C DMA_CHPRIC W1 Channel Priority Clear Register 0x04C DMA_ERRORC RW Bus Error Clear Register 0xE10 DMA_CHREQSTATUS R Channel Request Status 0xE1...

Page 68: ...d Value Mode Description 0 IDLE Idle 1 RDCHCTRLDATA Reading channel controller data 2 RDSRCENDPTR Reading source data end pointer 3 RDDSTENDPTR Reading destination data end pointer 4 RDSRCDATA Reading source data 5 WRDSTDATA Writing destination data 6 WAITREQCLR Waiting for DMA request to clear 7 WRCHCTRLDATA Writing channel controller data 8 STALLED Stalled 9 DONE Done 10 PERSCATTRANS Peripheral ...

Page 69: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name CTRLBASE Bit Name Reset Access Description 31 0 CTRLBASE 0x00000000 RW Channel Control Data Base Pointer The base pointer for a location in system memory that holds the channel control data structure This register must be written to point to a location in system memory with the channel control data structure before the DMA can be used ...

Page 70: ...hannel 4 Wait on Request Status Status for wait on request for channel 4 3 CH3WAITSTATUS 1 R Channel 3 Wait on Request Status Status for wait on request for channel 3 2 CH2WAITSTATUS 1 R Channel 2 Wait on Request Status Status for wait on request for channel 2 1 CH1WAITSTATUS 1 R Channel 1 Wait on Request Status Status for wait on request for channel 1 0 CH0WAITSTATUS 1 R Channel 0 Wait on Request...

Page 71: ...STS CH1USEBURSTS CH0USEBURSTS Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CH7USEBURSTS 0 RW1H Channel 7 Useburst Set See description for channel 0 6 CH6USEBURSTS 0 RW1H Channel 6 Useburst Set See description for channel 0 5 CH5USEBURSTS 0 RW1H Channel 5 Useburst Set See description for chan...

Page 72: ... for this channel 6 CH6USEBURSTC 0 W1 Channel 6 Useburst Clear Write to 1 to disable useburst setting for this channel 5 CH5USEBURSTC 0 W1 Channel 5 Useburst Clear Write to 1 to disable useburst setting for this channel 4 CH4USEBURSTC 0 W1 Channel 4 Useburst Clear Write to 1 to disable useburst setting for this channel 3 CH3USEBURSTC 0 W1 Channel 3 Useburst Clear Write to 1 to disable useburst set...

Page 73: ...to disable peripheral requests for this channel 8 7 10 DMA_CHREQMASKC Channel Request Mask Clear Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name CH7REQMASKC CH6REQMASKC CH5REQMASKC CH4REQMASKC CH3REQMASKC CH2REQMASKC CH1REQMASKC CH0REQMASKC Bit Name Reset Access Descri...

Page 74: ... 0 RW1 Channel 5 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 4 CH4ENS 0 RW1 Channel 4 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 3 CH3ENS 0 RW1 Channel 3 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 2 CH2ENS 0 RW1 Channel 2 Enable Set Write to 1 to e...

Page 75: ...000 or an ERROR occurs on the AHB Lite bus A read from this field returns the value of CH0ENS from the DMA_CHENS register 8 7 13 DMA_CHALTS Channel Alternate Set Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access RW1 RW1 RW1 RW1 RW1 RW1 RW1 RW1 Name CH7ALTS CH6ALTS CH5ALTS CH4ALTS CH3ALTS CH2ALTS CH1...

Page 76: ...tructure for this channel 5 CH5ALTC 0 W1 Channel 5 Alternate Clear Write to 1 to select the primary structure for this channel 4 CH4ALTC 0 W1 Channel 4 Alternate Clear Write to 1 to select the primary structure for this channel 3 CH3ALTC 0 W1 Channel 3 Alternate Clear Write to 1 to select the primary structure for this channel 2 CH2ALTC 0 W1 Channel 2 Alternate Clear Write to 1 to select the prima...

Page 77: ...l priority status 0 CH0PRIS 0 RW1 Channel 0 High Priority Set Write to 1 to obtain high priority for this channel Reading returns the channel priority status 8 7 16 DMA_CHPRIC Channel Priority Clear Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name CH7PRIC CH6PRIC CH5PRI...

Page 78: ...e Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CH7REQSTATUS 0 R Channel 7 Request Status When this bit is 1 it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel The controller services the request by performing the DMA cyc...

Page 79: ...services the request by performing the DMA cycle using single DMA transfers 6 CH6SREQSTATUS 0 R Channel 6 Single Request Status When this bit is 1 it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel The controller services the request by performing the DMA cycle using single DMA transfers 5 CH5SREQSTATUS 0 R Channel 5 ...

Page 80: ...transfer If the channel is disabled the flag is set when there is a request for the channel 3 CH3DONE 0 R DMA Channel 3 Complete Interrupt Flag Set when the DMA channel has completed its transfer If the channel is disabled the flag is set when there is a request for the channel 2 CH2DONE 0 R DMA Channel 2 Complete Interrupt Flag Set when the DMA channel has completed its transfer If the channel is...

Page 81: ...1 Name ERR CH7DONE CH6DONE CH5DONE CH4DONE CH3DONE CH2DONE CH1DONE CH0DONE Bit Name Reset Access Description 31 ERR 0 W1 DMA Error Interrupt Flag Clear Set to 1 to clear DMA error interrupt flag Note that if an error happened the Bus Error Clear Register must be used to clear the DMA 30 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p ...

Page 82: ...nterrupt on this DMA channel Clear to disable the interrupt 4 CH4DONE 0 RW DMA Channel 4 Complete Interrupt Enable Write to 1 to enable complete interrupt on this DMA channel Clear to disable the interrupt 3 CH3DONE 0 RW DMA Channel 3 Complete Interrupt Enable Write to 1 to enable complete interrupt on this DMA channel Clear to disable the interrupt 2 CH2DONE 0 RW DMA Channel 2 Complete Interrupt ...

Page 83: ...URCESEL 0b000000 NONE 0bxxxx OFF Channel input selection is turned off SOURCESEL 0b001000 ADC0 0b0000 ADC0SINGLE ADC0SINGLE 0b0001 ADC0SCAN ADC0SCAN SOURCESEL 0b001010 DAC0 0b0000 DAC0CH0 DAC0CH0 0b0001 DAC0CH1 DAC0CH1 SOURCESEL 0b001100 USART0 0b0000 USART0RXDATAV USART0RXDATAV REQ SREQ 0b0001 USART0TXBL USART0TXBL REQ SREQ 0b0010 USART0TXEMPTY USART0TXEMPTY SOURCESEL 0b001101 USART1 0b0000 USART...

Page 84: ... Access Description Value Mode Description 0b0011 TIMER1CC2 TIMER1CC2 SOURCESEL 0b110000 MSC 0b0000 MSCWDATA MSCWDATA SOURCESEL 0b110001 AES 0b0000 AESDATAWR AESDATAWR 0b0001 AESXORDATAWR AESXORDATAWR 0b0010 AESDATARD AESDATARD 0b0011 AESKEYWR AESKEYWR SOURCESEL 0b110010 LESENSE 0b0000 LESENSEBUFDATAV LESENSEBUFDATAV REQ SREQ ...

Page 85: ...onsumption The cause of the reset may be read from a register thus providing software with information about the cause of the reset 9 1 Introduction The RMU is responsible for handling the reset functionality of the EFM32TG 9 2 Features Reset sources Power on Reset POR Brown out Detection BOD on the following power domains Regulated domain Unregulated domain Analog Power Domain 0 AVDD0 Analog Powe...

Page 86: ...t Unit PORESETn SYSRESETn LOCKUP POWERONn BROWNOUT_UNREGn RESETn Filter LOCKUPRDIS VDD POR BOD Core Debug Interface Cortex Peripherals VDD_REGULATED RMU_RSTCAUSE BROWNOUT_REGn RCCLR Edge to pulse filter BOD AVDD0 BROWNOUT_AVDD0 BOD AVDD1 BROWNOUT_AVDD1 BOD EM4 wakeup em4 9 3 1 RMU_RSTCAUSE Register The RMU_RSTCAUSE register indicates the reason for the last reset The register should be cleared aft...

Page 87: ...ly voltage VDD has reached the threshold voltage VPORthr see Device Datasheet Electrical Characteristics for details Before the threshold voltage is reached the EFM32TG is kept in reset state The operation of the POR is illustrated in Figure 9 2 p 87 with the active low POWERONn reset signal The reason for the unknown region is that the corresponding supply voltage is too low for any reliable oper...

Page 88: ... up because of an unrecoverable exception following the activation of the processor s built in system state protection hardware For more information about the Cortex M3 lockup conditions see the ARMv7 M Architecture Reference Manual The Lockup reset does not reset the Debug Interface Set the LOCKUPRDIS bit in the RMU_CTRL register in order to disable this reset source 9 3 7 System Reset Request So...

Page 89: ...t Cause Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R R Name BODAVDD1 BODAVDD0 EM4WURST EM4RST SYSREQRST LOCKUPRST WDOGRST EXTRST BODREGRST BODUNREGRST PORST Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits t...

Page 90: ...on how to interpret this bit 2 BODREGRST 0 R Brown Out Detector Regulated Domain Reset Set if a regulated domain brown out detector reset has been performed Must be cleared by software Please see Table 9 1 p 87 for details on how to interpret this bit 1 BODUNREGRST 0 R Brown Out Detector Unregulated Domain Reset Set if a unregulated domain brown out detector reset has been performed Must be cleare...

Page 91: ...t Unit EMU manages all the low energy modes EM in EFM32TG microcontrollers Each energy mode manages if the CPU and the various peripherals are available The energy modes range from EM0 to EM4 where EM0 also called run mode enables the CPU and all peripherals The lowest recoverable energy mode EM3 disables the CPU and most peripherals while maintaining wake up and RAM functionality EM4 disables eve...

Page 92: ...de in which any peripheral function can be enabled and the Cortex M3 core is executing instructions EM1 through EM4 also called low energy modes provide a selection of reduced peripheral functionality that also lead to reduced energy consumption as described below Figure 10 2 p 93 shows the transitions between different energy modes After reset the EMU will always start in EM0 A transition from EM...

Page 93: ...eset power on reset EM4 wakeup No direct transitions between EM1 EM2 or EM3 are available as can also be seen from Figure 10 2 p 93 Instead a wakeup will transition back to EM0 in which software can enter any other low energy mode An overview of the supported energy modes and the functionality available in each mode is shown in Table 10 1 p 94 Most peripheral functionality indicated as On in a par...

Page 94: ...On ACMP On On On On I 2 C receive address recognition On On On On Watchdog On On On On 3 Pin interrupts On On On On RAM voltage regulator RAM retention On On On On Brown Out Reset On On On On Power On Reset On On On On On Pin Reset On On On On On GPIO state retention On On On On On EM4 Reset Wakeup Request On 1 Energy Mode 0 Active Mode 2 Energy Mode 1 2 3 4 3 When the 1 kHz ULFRCO is selected The...

Page 95: ...s entered by first configuring the desired Energy Mode through the EMU_CTRL register and the SLEEPDEEP bit in the Cortex M3 System Control Register see Table 10 2 p 95 A Wait For Interrupt WFI or Wait For Event WFE instruction from the Cortex M3 triggers the transition into a low energy mode The transition into a low energy mode can optionally be delayed until the lowest priority Interrupt Service...

Page 96: ... transmit Yes LEUART Receive transmit Yes Yes LESENSE Any enabled interrupt Yes Yes Yes 3 I 2 C Any enabled interrupt Yes I 2 C Receive address recognition Yes Yes Yes TIMER Any enabled interrupt Yes LETIMER Any enabled interrupt Yes Yes Yes 3 CMU Any enabled interrupt Yes DMA Any enabled interrupt Yes MSC Any enabled interrupt Yes DAC Any enabled interrupt Yes ADC Any enabled interrupt Yes AES An...

Page 97: ...M4CTRL 0x0 RW Energy Mode 4 Control This register is used to enter Energy Mode 4 in which the device only wakes up from an external pin reset or from a power cycle Energy Mode 4 is entered when the EM4 sequence is written to this bitfield 1 EM2BLOCK 0 RW Energy Mode 2 Block This bit is used to prevent the MCU to enter Energy Mode 2 or lower 0 EMVREG 0 RW Energy Mode Voltage Regulator Control Contr...

Page 98: ...UNLOCKED 0 EMU registers are unlocked LOCKED 1 EMU registers are locked Write Operation LOCK 0 Lock EMU registers UNLOCK 0xADE8 Unlock EMU registers 10 5 3 EMU_AUXCTRL Auxiliary Control Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name HRCCLR Bit Name Reset Access Description 31 1 Reserved To ensure compa...

Page 99: ...illator start up times makes duty cycling between active mode and the different low energy modes EM2 EM4 very efficient The calibration feature ensures high accuracy RC oscillators Several interrupts are available to avoid CPU polling of flags 11 1 Introduction The Clock Management Unit CMU is responsible for controlling the oscillators and clocks on board the EFM32TG The CMU provides the capabili...

Page 100: ...s and all peripherals Selectable clocks can be output on two pins for use externally Auxiliary 1 28 MHz RC oscillator AUXHFRCO for flash programming debug trace and LESENSE timing 11 3 Functional Description An overview of the CMU is shown in Figure 11 1 p 101 The number of peripheral modules that are connected to the different clocks varies from device to device ...

Page 101: ...Gate LFBCLKLEUART0 Clock Gate LFBCLKLEUART1 LFBCLK Clock Gate Clock Gate Clock Gate clock switch clock switch clock switch prescaler prescaler prescaler prescaler prescaler HFCORECLKLE CMU_HFCORECLKEN0 LE Clock Gate 2 HFCORECLK HFPERCLK Frame Rate Control ULFRCO PCNTnCLK PCNTn_S0 WDOG WDOG_CTRL CLKSEL CMU_LFCLKSEL LFB LFBE CMU_LFCLKSEL LFA LFAE CMU_LFBCLKEN0 LEUART1 CMU_LCDCTRL FDIV CMU_HFPERCLKDI...

Page 102: ...be a prescaled version of HFCLK This clock drives the High Frequency Peripherals All the peripherals that are driven by this clock can be clock gated completely when not in use This is done by clearing the clock enable bit for the specific peripheral in CMU_HFPERCLKEN0 The frequency of HFPERCLK is set using the CMU_HFPERCLKDIV register The setting can be changed dynamically and the new setting tak...

Page 103: ...or AUXHFRCO This clock is used for flash programming and Serial Wire Output SWO and LESENSE operation During flash programming or if needed by LESENSE this clock will be active If the AUXHFRCO has not been enabled explicitly by software the MSC or LESENSE module will automatically start and stop it The AUXHFRCO is enabled by writing a 1 to AUXHFRCOEN in CMU_OSCENCMD This explicit enabling is requi...

Page 104: ...llator will effectively stop HFCLK and only a reset can recover the system During the start up period HFCLK will stop since the oscillator driving it is not ready This effectively stalls the Core Modules and the High Frequency Peripherals It is possible to avoid this by first enabling the HFXO and then wait for the oscillator to become ready before switching the clock source This way the system co...

Page 105: ...ber to turn off all oscillators not in use 11 3 3 Oscillator Configuration 11 3 3 1 HFXO and LFXO The crystal oscillators are by default configured to ensure safe startup and operation of the most common crystals In order to optimize startup margin startup time and power consumption for a given crystal it is possible to adjust the gain in the oscillator HFXO gain can be increased by setting HFXOBO...

Page 106: ... sure to also update the tuning value The LFRCO and is also calibrated in production and its TUNING value is set to the correct value during reset The CMU has built in HW support to efficiently calibrate the RC oscillators at run time see Figure 11 6 p 107 The concept is to select a reference and compare the RC frequency with the reference frequency When the calibration circuit is started one down...

Page 107: ...ith top value in continouous mode Take snapshot of up counter in up counter bufffer If in continouous mode restart up counter from 0 The counter operation for single and continuous mode are shown in Figure 11 7 p 107 and Figure 11 8 p 107 respectively Figure 11 7 Single Calibration CONT 0 TOP 0 Calibration Started Calibration Stopped counters stopped 0 Down counter Up counter Up counter sampled an...

Page 108: ...T1 A qualified clock will not have any glitches or skewed duty cycle during startup For LFXO and HFXO you need to configure LFXOTIMEOUT and HFXOTIMEOUT in CMU_CTRL correctly to guarantee a qualified clock HFRCO HFXO HFCLK 2 HFCLK 4 HFCLK 8 HFCLK 16 ULFRCO or AUXHFRCO can be output on another pin CMU_OUT0 Note that HFXO and HFRCO clock outputs to pin can be unstable after startup and should not be ...

Page 109: ... 0x028 CMU_LFCLKSEL RW Low Frequency Clock Select Register 0x02C CMU_STATUS R Status Register 0x030 CMU_IF R Interrupt Flag Register 0x034 CMU_IFS W1 Interrupt Flag Set Register 0x038 CMU_IFC W1 Interrupt Flag Clear Register 0x03C CMU_IEN RW Interrupt Enable Register 0x040 CMU_HFCORECLKEN0 RW High Frequency Core Clock Enable Register 0 0x044 CMU_HFPERCLKEN0 RW High Frequency Peripheral Clock Enabl...

Page 110: ...nsure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 25 23 CLKOUTSEL1 0x0 RW Clock Output Select 1 Controls the clock output multiplexer To actually output on the pin set CLKOUT1PEN in CMU_ROUTE Value Mode Description 0 LFRCO LFRCO directly from oscillator 1 LFXO LFXO directly from oscillator 2 HFCLK HFCLK 3 LFXOQ LFXO qualified 4 HFXOQ HFXO qualified ...

Page 111: ... Timeout period of 256 cycles 2 1KCYCLES Timeout period of 1024 cycles 3 16KCYCLES Timeout period of 16384 cycles 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 HFXOGLITCHDETEN 0 RW HFXO Glitch Detector Enable This bit enables the glitch detector which is active as long as the start up ripple counter is counting A detected glitch...

Page 112: ...CLK 4 3 HFCLK8 HFCORECLK HFCLK 8 4 HFCLK16 HFCORECLK HFCLK 16 5 HFCLK32 HFCORECLK HFCLK 32 6 HFCLK64 HFCORECLK HFCLK 64 7 HFCLK128 HFCORECLK HFCLK 128 8 HFCLK256 HFCORECLK HFCLK 256 9 HFCLK512 HFCORECLK HFCLK 512 11 5 3 CMU_HFPERCLKDIV High Frequency Peripheral Clock Division Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Re...

Page 113: ...FRCO Band Select Write this field to set the frequency band in which the HFRCO is to operate When changing this setting there will be no glitches on the HFRCO output hence it is safe to change this setting even while the system is running on the HFRCO To ensure an accurate frequency the HFTUNING value should also be written when changing the frequency band The calibrated tuning value for the diffe...

Page 114: ...ency band in which the AUXHFRCO is to operate When changing this setting there will be no glitches on the AUXHFRCO output hence it is safe to change this setting even while the system is using the AUXHFRCO To ensure an accurate frequency the AUXTUNING value should also be written when changing the frequency band The calibrated tuning value for the different bands can be read from the Device Inform...

Page 115: ...iption 0 HFCLK Select HFCLK for down counter 1 HFXO Select HFXO for down counter 2 LFXO Select LFXO for down counter 3 HFRCO Select HFRCO for down counter 4 LFRCO Select LFRCO for down counter 5 AUXHFRCO Select AUXHFRCO for down counter 2 0 UPSEL 0x0 RW Calibration Up counter Select Selects clock source for the calibration up counter Value Mode Description 0 HFXO Select HFXO as up counter 1 LFXO S...

Page 116: ...LFXODIS 0 W1 LFXO Disable Disables the LFXO LFXOEN has higher priority if written simultaneously 8 LFXOEN 0 W1 LFXO Enable Enables the LFXO 7 LFRCODIS 0 W1 LFRCO Disable Disables the LFRCO LFRCOEN has higher priority if written simultaneously 6 LFRCOEN 0 W1 LFRCO Enable Enables the LFRCO 5 AUXHFRCODIS 0 W1 AUXHFRCO Disable Disables the AUXHFRCO AUXHFRCOEN has higher priority if written simultaneou...

Page 117: ...irm that oscillator is ready before switching Value Mode Description 1 HFRCO Select HFRCO as HFCLK 2 HFXO Select HFXO as HFCLK 3 LFRCO Select LFRCO as HFCLK 4 LFXO Select LFXO as HFCLK 11 5 11 CMU_LFCLKSEL Low Frequency Clock Select Register Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x1 0x1 Access RW RW RW RW Name LFBE...

Page 118: ...d as LFACLK 3 0 HFCORECLKLEDIV2 HFCORECLKLE divided by two is selected as LFACLK 0 1 ULFRCO ULFRCO selected as LFACLK 11 5 12 CMU_STATUS Status Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 Access R R R R R R R R R R R R R R R Name CALBSY LFXOSEL LFRCOSEL HFXOSEL HFRCOSEL LFXORDY LFXOENS ...

Page 119: ...Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 1 Access R R R R R R R Name CALOF CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 CALOF 0 R Calibration...

Page 120: ...Set Write to 1 to set the Calibration Ready completed Interrupt Flag 4 AUXHFRCORDY 0 W1 AUXHFRCO Ready Interrupt Flag Set Write to 1 to set the AUXHFRCO Ready Interrupt Flag 3 LFXORDY 0 W1 LFXO Ready Interrupt Flag Set Write to 1 to set the LFXO Ready Interrupt Flag 2 LFRCORDY 0 W1 LFRCO Ready Interrupt Flag Set Write to 1 to set the LFRCO Ready Interrupt Flag 1 HFXORDY 0 W1 HFXO Ready Interrupt F...

Page 121: ...ady Interrupt Flag 11 5 16 CMU_IEN Interrupt Enable Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW Name CALOF CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future devices always write bits to 0 ...

Page 122: ...able the clock for AES 11 5 18 CMU_HFPERCLKEN0 High Frequency Peripheral Clock Enable Register 0 Offset Bit Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW Name I2C0 DAC0 ADC0 PRS VCMP GPIO TIMER1 TIMER0 USART1 USART0 ACMP1 ACMP0 Bit Name Reset Access Description 31 12 Rese...

Page 123: ...1 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 LFBPRESC0 0 R Low Frequency B Prescaler 0 Busy Used to check the synchronization status of CMU_LFBPRESC0 Value Description 1 CMU_LFBPRESC0 is busy synchronizing new value 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p...

Page 124: ...sly Value Mode Description 0 UPDATE Each write access to a Low Frequency clock control register is updated into the Low Frequency domain as soon as possible 1 FREEZE The LE Clock Control registers are not updated with the new written value 11 5 21 CMU_LFACLKEN0 Low Frequency A Clock Enable Register 0 Async Reg Offset Bit Position 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 125: ...7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0x0 Access RW RW RW RW Name LCD LETIMER0 RTC LESENSE Bit Name Reset Access Description 31 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 12 LCD 0x0 RW Liquid Crystal Display Controller Prescaler Configure Liquid Crystal Display Controller prescaler Value Mode Description 0 DIV16 LFACLKLCD LFACL...

Page 126: ...LKRTC LFACLK 1024 11 DIV2048 LFACLKRTC LFACLK 2048 12 DIV4096 LFACLKRTC LFACLK 4096 13 DIV8192 LFACLKRTC LFACLK 8192 14 DIV16384 LFACLKRTC LFACLK 16384 15 DIV32768 LFACLKRTC LFACLK 32768 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 0 LESENSE 0x0 RW Low Energy Sensor Interface Prescaler Configure Low Energy Sensor Interface pr...

Page 127: ...bit controls which clock that is used for the PCNT Value Mode Description 0 LFACLK LFACLK is clocking PCNT0 1 PCNT0S0 External pin PCNT0_S0 is clocking PCNT0 0 PCNT0CLKEN 0 RW PCNT0 Clock Enable This bit enables disables the clock to the PCNT Value Description 0 PCNT0 is disabled 1 PCNT0 is enabled 11 5 26 CMU_LCDCTRL LCD Control Register Offset Bit Position 0x07C 31 30 29 28 27 26 25 24 23 22 21 ...

Page 128: ...e the LCD bit in CMU_LFACLKEN0 is set to 1 11 5 27 CMU_ROUTE I O Routing Register Offset Bit Position 0x080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 Access RW RW RW Name LOCATION CLKOUT1PEN CLKOUT0PEN Bit Name Reset Access Description 31 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Secti...

Page 129: ... unlock code to lock CMU_CTRL CMU_HFCORECLKDIV CMU_HFPERCLKDIV CMU_HFRCOCTRL CMU_LFRCOCTRL CMU_AUXHFRCOCTRL CMU_OSCENCMD CMU_CMD CMU_LFCLKSEL CMU_HFCORECLKEN0 CMU_HFPERCLKEN0 CMU_LFACLKEN0 CMU_LFBCLKEN0 CMU_LFAPRESC0 CMU_LFBPRESC0 and CMU_PCNTCTRL from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOC...

Page 130: ...liability The failure may e g be caused by an external event such as an ESD pulse or by a software failure 12 2 Features Clock input from selectable oscillators Internal 32 768 Hz RC oscillator Internal 1 kHz RC oscillator External 32 768 Hz XTAL oscillator Configurable timeout period from 9 to 256k watchdog clock cycles Individual selection to keep running or freeze when entering EM2 or EM3 Selec...

Page 131: ...12 3 3 Energy Mode Handling The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3 The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in WDOG_CTRL When the watchdog has been frozen and is re entering an energy mode where it is running the watchdog timer will continue counting where it left off For the watchdog there ...

Page 132: ...s to 0 More information in Section 2 1 p 3 13 12 CLKSEL 0x0 RW Watchdog Clock Select Selects the WDOG oscillator i e the clock on which the watchdog will run Value Mode Description 0 ULFRCO ULFRCO 1 LFRCO LFRCO 2 LFXO LFXO 11 8 PERSEL 0xF RW Watchdog Timeout Period Select Select watchdog timeout period Value Description 0 Timeout period of 9 watchdog clock cycles 1 Timeout period of 17 watchdog cl...

Page 133: ...be entered 4 LOCK 0 RW Configuration lock Set to lock the watchdog configuration This bit can only be cleared by reset Value Description 0 Watchdog configuration can be changed 1 Watchdog configuration cannot be changed 3 EM3RUN 0 RW Energy Mode 3 Run Enable Set to keep watchdog running in EM3 Value Description 0 Watchdog timer is frozen in EM3 1 Watchdog timer is running in EM3 2 EM2RUN 0 RW Ener...

Page 134: ...n 0 UNCHANGED Watchdog timer is unchanged 1 CLEARED Watchdog timer is cleared to 0 12 5 3 WDOG_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access R R Name CMD CTRL Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More...

Page 135: ...ls are called producers The PRS routes these reflex signals to consumer peripherals which apply actions depending on the reflex signals received The format for the reflex signals is not given but edge triggers and other functionality can be applied by the PRS 13 2 Features 8 configurable interconnect channels Each channel can be connected to any producing peripheral Consumers can choose which chan...

Page 136: ...in the PRS Each channel includes an edge detector to enable generation of pulse signals from level signals It is also possible to generate output reflex signals by configuring the SWPULSE and SWLEVEL bits SWLEVEL is a programmable level for each channel and holds the value it is programmed to The SWPULSE will give out a one cycle high pulse if it is written to 1 otherwise a 0 is asserted The SWLEV...

Page 137: ...Input Level Yes Pin 2 Input Level Yes Pin 3 Input Level Yes Pin 4 Input Level Yes Pin 5 Input Level Yes Pin 6 Input Level Yes Pin 7 Input Level Yes Pin 8 Input Level Yes Pin 9 Input Level Yes Pin 10 Input Level Yes Pin 11 Input Level Yes Pin 12 Input Level Yes Pin 13 Input Level Yes Pin 14 Input Level Yes GPIO Pin 15 Input Level Yes Overflow Pulse Yes Compare Match 0 Pulse Yes RTC Compare Match 1 ...

Page 138: ...Trigger Pulse DAC Channel 1 Trigger Pulse CC1 Input Pulse Level CC2 Input Pulse Level TX RX Enable Pulse IrDA Encoder Input USART0 only Pulse USART RX Input Pulse Level Yes LEUART RX Input Pulse Level Yes S0 input Level Yes PCNT S1 input Level Yes Start scan Pulse Level Yes Decoder Bit 0 Level Yes Decoder Bit 1 Level Yes Decoder Bit 2 Level Yes LESENSE Decoder Bit 3 Level Yes Note It is possible t...

Page 139: ...gh PRS input signal Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the single conversion Start TIMER0 with the desired TOP value an overflow PRS signal is output automatically on overflow Note that the ADC results needs to be fetched either by the CPU or DMA Figure 13 2 TIMER0 overflow starting ADC0 single conversions through PRS channel 5 PRS TIMER0 ADC0 ch0 ...

Page 140: ...ster Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name CH7PULSE CH6PULSE CH5PULSE CH4PULSE CH3PULSE CH2PULSE CH1PULSE CH0PULSE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 ...

Page 141: ...EVEL 0 RW Channel 4 Software Level See bit 0 3 CH3LEVEL 0 RW Channel 3 Software Level See bit 0 2 CH2LEVEL 0 RW Channel 2 Software Level See bit 0 1 CH1LEVEL 0 RW Channel 1 Software Level See bit 0 0 CH0LEVEL 0 RW Channel 0 Software Level The value in this register is XOR ed with the corresponding bit in the SWPULSE register and the selected PRS input signal to generate the channel output 13 5 3 P...

Page 142: ... disable synchronization of this reflex signal 27 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 25 24 EDSEL 0x0 RW Edge Detect Select Select edge detection Value Mode Description 0 OFF Signal is left as it is 1 POSEDGE A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal 2 NEGEDGE A one HFPERCLK ...

Page 143: ...AC0 0b000 DAC0CH0 DAC ch0 conversion done DAC0CH0 0b001 DAC0CH1 DAC ch1 conversion done DAC0CH1 SOURCESEL 0b001000 ADC0 0b000 ADC0SINGLE ADC single conversion done ADC0SINGLE 0b001 ADC0SCAN ADC scan conversion done ADC0SCAN SOURCESEL 0b010000 USART0 0b000 USART0IRTX USART 0 IRDA out USART0IRTX 0b001 USART0TXC USART 0 TX complete USART0TXC 0b010 USART0RXDATAV USART 0 RX Data Valid USART0RXDATAV SOU...

Page 144: ...SCANRES register bit 1 LESENSESCANRES1 0b010 LESENSESCANRES2 LESENSE SCANRES register bit 2 LESENSESCANRES2 0b011 LESENSESCANRES3 LESENSE SCANRES register bit 3 LESENSESCANRES3 0b100 LESENSESCANRES4 LESENSE SCANRES register bit 4 LESENSESCANRES4 0b101 LESENSESCANRES5 LESENSE SCANRES register bit 5 LESENSESCANRES5 0b110 LESENSESCANRES6 LESENSE SCANRES register bit 6 LESENSESCANRES6 0b111 LESENSESCA...

Page 145: ...r and slave and supports multi master buses Standard mode fast mode and fast mode plus speeds are supported allowing transmission rates all the way from 10 kbit s up to 1 Mbit s Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system The interface provided to software by the I 2 C module allows both fine grained control of the transmission process and ...

Page 146: ...des collision detection and arbitration to resolve situations where multiple masters transmit data at the same time without data loss Figure 14 2 I 2 C Bus Example I2 C master 1 I2 C master 2 I2 C slave 1 I2 C slave 2 I2 C slave 3 SDA SCL VDD Rp Each device on the bus is addressable by a unique address and an I 2 C master can address all the devices on the bus including other masters Both the bus ...

Page 147: ...n in Figure 14 2 p 146 Figure 14 4 I 2 C Bit Transfer on I 2 C Bus SCL SDA Data stable Data change allowed Data change allowed 14 3 1 2 Bus Transfer When a master wants to initiate a transfer on the bus it waits until the bus is idle and transmits a START condition on the bus The master then transmits the address of the slave it wishes to interact with and a single R W bit telling whether it wishe...

Page 148: ...P Figure 14 7 I 2 C Single Byte Write then Repeated Start and Single Byte Read R Sr ADDR DATA A N P W S ADDR DATA A A 14 3 1 3 Addresses I 2 C supports both 7 bit and 10 bit addresses When using 7 bit addresses the first byte transmitted after the START condition contains the address of the slave that the master wants to contact In the 7 bit address space several addresses are reserved These addre...

Page 149: ...yte transmitted is shown in Figure 14 9 p 149 Figure 14 9 I 2 C Master Receiver Slave Transmitter with 10 bit Address R Sr DATA A N P W S A A ADDR 1st 7 bits Addr 2nd byte ADDR 1st 7 bits 14 3 1 5 Arbitration Clock Synchronization Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi master buses Arbitration occurs when two devices try to drive the bus at the ...

Page 150: ... Thigh Nhigh CLKDIV 1 fHFPERCLK Tlow Nlow CLKDIV 1 fHFPERCLK 14 3 Equation 14 3 p 150 and Equation 14 2 p 150 does not apply for low clock division factors 0 1 and 2 because of synchronization For these clock division factors the formulas for computing high and low periods of the clock signal are given in Table 14 2 p 150 Table 14 2 I 2 C High and Low Periods for Low CLKDIV CLKDIV Standard 4 4 Asy...

Page 151: ...e sensed value is different than the value the I 2 C module tried to output it is interpreted as a simultaneous transmission by another device and that the I 2 C module has lost arbitration Whenever arbitration is lost the ARBLOST interrupt flag in I2Cn_IF is set any lines held are released and the I 2 C device goes idle If an I 2 C master loses arbitration during the transmission of an address an...

Page 152: ...t Otherwise the byte waits in the shift register until space becomes available in the buffer When a byte becomes available in the receive buffer the RXDATAV in I2Cn_STATUS and RXDATAV interrupt flag in I2Cn_IF are set The data can now be fetched from the buffer using I2Cn_RXDATA Reading from this register will pull a byte out of the buffer making room for a new byte and clearing RXDATAV in I2Cn_ST...

Page 153: ...he state machine ending the operation or continuing with a new operation when arriving at the right side of the state machine Branches in the path through the state machine are the results of bus events and choices made by software either directly or indirectly The dotted lines show where I 2 C specific interrupt flags are set along the path and the full drawn circles show places where interaction...

Page 154: ...e possible from a given state the course of action using the highest priority interactions that first has everything it is waiting for is the one that is taken Table 14 4 I 2 C Interactions in Prioritized Order Interaction Priority Software action Automatically continues if STOP 1 Set the STOP command bit in I2Cn_CMD PSTOP is set STOP pending in I2Cn_STATUS ABORT 2 Set the ABORT command bit in I2C...

Page 155: ...ses with little activity the time before the I 2 C module detects that the bus is idle can be significant There are two ways of assuring that the I 2 C module gets out of the busy state Use the ABORT command in I2Cn_CMD When the ABORT command is issued the I 2 C module is instructed that the bus is idle The I 2 C module can then initiate master operations Use the Bus Idle Timeout When SCL has been...

Page 156: ...n In this case the ARBLOST interrupt flag in I2Cn_IF is set If the arbitration was lost during the transfer of an address and SLAVE in I2Cn_CTRL is set the master then checks which address was transmitted If it was the address of the master then the master goes to slave mode After a master has transmitted a START and won any arbitration it owns the bus until it transmits a STOP After a STOP the bu...

Page 157: ... the data register thus has to contain the 7 bit slave address in the 7 most significant bits of the byte and have the least significant bit set When the address has been transmitted the master receives an ACK or a NACK If an ACK is received the ACK interrupt flag in I2Cn_IF is set and if space is available in the receive shift register reception of a byte from the slave begins If the receive buff...

Page 158: ...nt when bus becomes idle ADDR R transmitted TXBL interrupt flag TXC interrupt flag None RXDATA Start receiving STOP STOP will be sent and the bus released START Repeated START will be sent 0x93 ADDR R transmitted ACK received ACK interrupt flag BUSHOLD STOP START STOP will be sent and the bus released Then a START will be sent when the bus becomes idle CONT RXDATA Continue start receiving STOP STO...

Page 159: ...as been received ADDRACK 4 Address ACK NACK being transmitted or received DATA 5 Data being transmitted or received DATAACK 6 Data ACK NACK being transmitted or received Table 14 8 I 2 C Transmission Status Bit Description BUSY Set whenever there is activity on the bus Whether or not this module is responsible for the activity cannot be determined by this byte MASTER Set when operating as a master...

Page 160: ... energy modes except EM4 The slave address i e the address which the I 2 C module should be addressed with is defined in the I2Cn_SADDR register In addition to the address a mask must be specified telling the address comparator which bits of an incoming address to compare with the address defined in I2Cn_SADDR The mask is defined in I2Cn_SADDRMASK and for every zero in the mask the corresponding b...

Page 161: ...K command The slave will in that case go to an idle state and wait for the next start condition To continue the transmission the slave must make sure data is loaded into the transmit buffer and send an ACK The loaded data will then be transmitted to the master and an ACK or NACK will be received from the master Data transmission can also continue after a NACK if a CONT command is issued along with...

Page 162: ...tion that the address transmitted by the master has the R W bit cleared W indicating that the master wishes to write to the slave The slave then goes into slave receiver mode To receive data from the master the slave should respond to the address with an ACK and make sure space is available in the receive buffer Transmission will then continue and the slave will receive a byte from the master If a...

Page 163: ...t up to complete transfers with a minimal amount of interaction 14 3 10 1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer When using DMA software is thus relieved of moving data to and from memory after each transferred byte 14 3 10 2 Automatic ACK When AUTOACK in I2Cn_CTRL is set an ACK is sent automatically whenever an ACK interac...

Page 164: ...ich can be set in I2Cn_CMD to help resolve bus errors When the bus for some reason is locked up and the I 2 C module is in the middle of a transmission it cannot get out of or for some other reason the I 2 C wants to abort a transmission the ABORT command can be used Setting the ABORT command will make the I 2 C module discard any data currently being transmitted or received release the SDA and SC...

Page 165: ...timeout BITO in I2Cn_CTRL can be used to detect situations where the bus goes idle in the middle of a transmission The timeout can be configured in BITO and when the bus has been idle for the given amount of time the BITO interrupt flag in I2Cn_IF is set The bus can also be set idle automatically on a bus idle timeout This is enabled by setting GIBITO in I2Cn_CTRL When the bus idle timer times out...

Page 166: ...nterrupts generated by the I 2 C module are combined into one interrupt vector I2C_INT If I 2 C interrupts are enabled an interrupt will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set 14 3 15 Wake up The I 2 C receive section can be active all the way down to energy mode EM3 and can wake up the CPU on address interrupt All address match mo...

Page 167: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0x0 0x0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW Name CLTO GIBITO BITO CLHR GCAMEN ARBDIS AUTOSN AUTOSE AUTOACK SLAVE EN Bit Name Reset Access Description 31 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 18 16 CLTO 0x0 RW Clock Low T...

Page 168: ... bits to 0 More information in Section 2 1 p 3 9 8 CLHR 0x0 RW Clock Low High Ratio Determines the ratio between the low and high parts of the clock signal generated on SCL as master Value Mode Description 0 STANDARD The ratio between low period and high period counters Nlow Nhigh is 4 4 1 ASYMMETRIC The ratio between low period and high period counters Nlow Nhigh is 6 3 2 FAST The ratio between l...

Page 169: ...OP START Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CLEARPC 0 W1 Clear Pending Commands Set to clear pending commands 6 CLEARTX 0 W1 Clear TX Set to clear transmit buffer and shift register Will not abort ongoing transfer 5 ABORT 0 W1 Abort transmission Abort the current transmission makin...

Page 170: ...if the bus is currently being held by this I 2 C module 3 NACKED 0 R Nack Received Set if a NACK was received and STATE is ADDRACK or DATAACK 2 TRANSMITTER 0 R Transmitter Set when operating as a master transmitter or a slave transmitter When cleared the system may be operating as a master receiver a slave receiver or the current mode is not known 1 MASTER 0 R Master Set when operating as an I 2 C...

Page 171: ...nding and will be transmitted as soon as possible 2 PACK 0 R Pending ACK An acknowledge is pending and will be transmitted as soon as possible 1 PSTOP 0 R Pending STOP A stop condition is pending and will be transmitted as soon as possible 0 PSTART 0 R Pending START A start condition is pending and will be transmitted as soon as possible 14 5 5 I2Cn_CLKDIV Clock Division Register Offset Bit Positi...

Page 172: ...rved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 1 MASK 0x00 RW Slave Address Mask Specifies the significant bits of the slave address Setting the mask to 0x00 will match all addresses while setting it to 0x7F will only match the exact address specified by ADDR 0 Reserved To ensure compatibility with future devices always write bits to 0...

Page 173: ...ccess W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 TXDATA 0x00 W TX Data Use this register to write a byte to the transmit buffer 14 5 11 I2Cn_IF Interrupt Flag Register Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 174: ...7 NACK 0 R Not Acknowledge Received Interrupt Flag Set when a NACK has been received 6 ACK 0 R Acknowledge Received Interrupt Flag Set when an ACK has been received 5 RXDATAV 0 R Receive Data Valid Interrupt Flag Set when data is available in the receive buffer Cleared automatically when the receive buffer is read 4 TXBL 1 R Transmit Buffer Level Interrupt Flag Set when the transmit buffer becomes...

Page 175: ... Set Not Acknowledge Received Interrupt Flag Write to 1 to set the NACK interrupt flag 6 ACK 0 W1 Set Acknowledge Received Interrupt Flag Write to 1 to set the ACK interrupt flag 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 TXC 0 W1 Set Transfer Completed Interrupt Flag Write to 1 to set the TXC interrupt flag 2 ADDR 0 W1 Set...

Page 176: ...errupt Flag Write to 1 to clear the NACK interrupt flag 6 ACK 0 W1 Clear Acknowledge Received Interrupt Flag Write to 1 to clear the ACK interrupt flag 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 TXC 0 W1 Clear Transfer Completed Interrupt Flag Write to 1 to clear the TXC interrupt flag 2 ADDR 0 W1 Clear Address Interrupt Fl...

Page 177: ...errupt when not acknowledge is received 6 ACK 0 RW Acknowledge Received Interrupt Enable Enable interrupt on acknowledge received 5 RXDATAV 0 RW Receive Data Valid Interrupt Enable Enable interrupt on receive buffer full 4 TXBL 0 RW Transmit Buffer level Interrupt Enable Enable interrupt on transmit buffer level 3 TXC 0 RW Transfer Completed Interrupt Enable Enable interrupt on transfer completed ...

Page 178: ...O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 SCLPEN 0 RW SCL Pin Enable When set the SCL pin of the I 2 C is enabled 0 SDAPEN 0 RW SDA Pin Enable When set the SDA pin of t...

Page 179: ...roduction The Universal Synchronous Asynchronous serial Receiver and Transmitter USART is a very flexible serial I O module It supports full duplex asynchronous UART communication as well as RS 485 SPI MicroWire and 3 wire It can also interface with ISO7816 SmartCards and IrDA devices 15 2 Features Asynchronous and synchronous SPI communication Full duplex and half duplex Separate TX RX enable Sep...

Page 180: ...ripheral Bus Baud rate generator USn_CLK Pin ctrl USn_CS U S n_RX IrDA modulator IrDA demodulator RXBLOCK PRS inputs 15 3 1 Modes of Operation The USART operates in either asynchronous or synchronous mode In synchronous mode a separate clock signal is transmitted with the data This clock signal is generated by the bus master and both the master and slave sample and transmit data according to this ...

Page 181: ... 0 Data in Data out Clock in Slave select 1 0 1 Data out Data in Clock out Auto slave select 1 1 0 Data out in Clock in Slave select 1 1 1 Data out in Clock out Auto slave select 15 3 2 Asynchronous Operation 15 3 2 1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking A frame ...

Page 182: ...e inverted by setting TXINV in USARTn_CTRL and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL These bits affect the entire frame not only the data bits An inverted frame has a low idle state a high start bit inverted data and parity bits and low stop bits 15 3 2 1 1 Parity bit Calculation and Handling When parity bits are enabled hardware automatically calculat...

Page 183: ...low the USART clock to be controlled more accurately than what is possible with a standard integral divider The clock divider used in the USART is a 15 bit value with a 13 bit integral part and a 2 bit fractional part The fractional part is configured in the two LSBs of DIV in USART_CLKDIV The lowest achievable baud rate at 32 MHz is about 244 bauds sec Fractional clock division is implemented by ...

Page 184: ...e to become available Transmission is enabled through the command register USARTn_CMD by setting TXEN and disabled by setting TXDIS in the same command register When the transmitter is disabled using TXDIS any ongoing transmission is aborted and any frame currently being transmitted is discarded When disabled the TX output goes to an idle state which by default is a high value Whether or not the t...

Page 185: ...mpty Both the TXBL status flag and the TXBL interrupt flag are cleared automatically when their condition becomes false The transmit buffer including the transmit shift register can be cleared by setting CLEARTX in USARTn_CMD This will prevent the USART from transmitting the data in the buffer and shift register and will make them available for new data Any frame currently being transmitted will n...

Page 186: ...er the RXDATAV flag in USARTn_STATUS and the RXDATAV interrupt flag in USARTn_IF are set and when the buffer becomes full RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set The status flags RXDATAV and RXFULL are automatically cleared by hardware when their condition is no longer true This also goes for the RXDATAV interrupt flag but the RXFULL interrupt flag must be cleare...

Page 187: ...uffer RXBLOCK must be cleared in the instant a frame is fully received by the receiver RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by setting RXBLOCKDIS also in USARTn_CMD There is one exception where data is loaded into the receive buffer even when RXBLOCK is set This is when an address frame is received when operating in multi processor mode See Section 15 3 2 8 p 193 for more...

Page 188: ... 5 p 188 Majority vote can be disabled by setting MVDIS in USARTn_CTRL If the value of the start bit is found to be high the reception of the frame is aborted filtering out false start bits possibly generated by noise on the input Figure 15 5 USART Sampling of Start and Data Bits 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 Idle Start bit Bit 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 1...

Page 189: ..._RXDOUBLEX or USARTn_RXDOUBLEXP registers If ERRSTX in USARTn_CTRL is set the transmitter is disabled on received parity and framing errors If ERRSRX in USARTn_CTRL is set the receiver is disabled on parity and framing errors 15 3 2 4 5 Framing Error and Break Detection A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0 This can be the result of n...

Page 190: ...IS also in USARTn_CMD must be set to enable transmitter output again Whether or not the output is tristated at a given time can be read from TXTRI in USARTn_STATUS If TXTRI is set when transmitting data the data is shifted out of the shift register but is not put out on U S n_TX When operating a half duplex data bus it is common to have a bus master which first transmits a request to one of the bu...

Page 191: ...lso be used for automatic chip slave select when in synchronous mode e g SPI 15 3 2 6 3 Two Data links Some limited devices only support half duplex communication even though two data links are available In this case software is responsible for making sure data is not transmitted when incoming data is expected 15 3 2 7 Large Frames As each frame in the transmit and receive buffers holds a maximum ...

Page 192: ...ipheral Bus 2 1 0 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 0 1 2 Figure 15 10 p 192 illustrates the order of the transmitted bits when an 11 bit frame is transmitted with MSBF set If MSBF is set and the frame is smaller than 10 bits only the contents of transmit buffer 0 will be transmitted When receiving a large frame BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the t...

Page 193: ...ARTn_STATUS Multi processor mode is enabled by setting MPM in USARTn_CTRL and the value of the 9th bit in address frames can be set in MPAB Note that the receiver must be enabled for address frames to be detected The receiver can be blocked however preventing data from being loaded into the receive buffer while looking for address frames Example 15 1 p 193 explains basic usage of the multi process...

Page 194: ...supports the ISO 7816 I O line T0 mode With exception of the stop bits guard time the 7816 data frame is equal to the regular asynchronous frame In this mode the receiver pulls the line low for one baud half a baud into the guard time to indicate a parity error This NAK can for instance be used by the transmitter to re transmit the frame SmartCard mode is a half duplex asynchronous mode so the tra...

Page 195: ... a NACK ed frame The transmitter will retransmit the frame until it is ACK ed by the receiver This only works when the number of databits in a frame is configured to 8 Set SKIPPERRF in USARTn_CTRL to make the receiver discard frames with parity errors The PERR interrupt flag in USARTn_IF is set when a frame is discarded because of a parity error Figure 15 14 USART SmartCard Stop Bit Sampling 13 14...

Page 196: ... 2 bit fractional part USART Synchronous Mode Bit Rate br fHFPERCLK 2 x 1 USARTn_CLKDIV 256 15 3 Given a desired baud rate brdesired the clock divider USARTn_CLKDIV can be calculated using Equation 15 4 p 196 USART Synchronous Mode Clock Division Factor USARTn_CLKDIV 256 x fHFPERCLK 2 x brdesired 1 15 4 When the USART operates in master mode the highest possible bit rate is half the peripheral clo...

Page 197: ...ister using the internal clock When there are no more frames in the transmit buffer and the transmit shift register is empty the clock stops and communication ends When the receiver is enabled it samples data using the internal clock when the transmitter transmits data Operation of the RX and TX buffers is as in asynchronous mode 15 3 3 3 1 Operation of USn_CS Pin When operating in master mode the...

Page 198: ...nderflow interrupt flag TXUF in USARTn_IF will be set if no data is available for transmission to the master If the slave needs to control its own chip select signal this can be achieved by clearing CSPEN in the ROUTE register The internal chip select signal can then be controlled through CSINV in the CTRL register The chip select signal will be CSINV inverted i e if CSINV is cleared the chip sele...

Page 199: ...s 15 3 3 6 2 Major Modes The USART supports a set of different I2S formats as shown in Table 15 9 p 199 but it is not limited to these modes MONO JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format MONO enables mono mode i e one data stream instead of two which is the default JUSTIFY aligns data within a word on the I2S bus either left or right which can be...

Page 200: ... directly after the edge on the word select signal in contradiction to the regular I2S waveform where it comes one bit period after Figure 15 18 USART Left justified I2S waveform USn_CLK USn_CS word select USn_TX USn_RX MSB Left channel Right channel Right channel LSB MSB A right justified stream is shown in Figure 15 19 p 200 The left and right justified streams are equal when the data size is eq...

Page 201: ... USARTn_I2SCTRL In both master and slave mode the USART always starts transmitting on the LEFT channel after being enabled In master mode the transmission will stop if TX becomes empty In that case TXC is set Continuing the transmission in this case will make the data stream continue where it left off To make the USART start on the LEFT channel after going empty disable and re enable TX 15 3 4 PRS...

Page 202: ...room for more data Transmit buffer has room for RIGHT I2S data Only used in I2S mode Even though there are two sources for write requests to the DMA only one should be used at a time since the requests from both sources are cleared even though only one of the requests are used In some cases it may be sensible to temporarily stop DMA access to the USART when an error such as a framing error has occ...

Page 203: ...ut signal is demodulated before it enters the actual USART module The modulator is only available on USART0 and implements the original Rev 1 0 physical layer and one high speed extension which supports speeds from 2 4 kbps to 1 152 Mbps The data from and to the USART is represented in a NRZ Non Return to Zero format where the signal value is at the same level through the entire bit period For IrD...

Page 204: ...d an incoming pulse has to last for 4 consecutive clock cycles to be detected by the IrDA demodulator Note that by default the idle value of the USART data signal is high This means that the IrDA modulator generates negative pulses and the IrDA demodulator expects negative pulses To make the IrDA module use RZI signalling both TXINV and RXINV in USARTn_CTRL must be set The IrDA module can also mod...

Page 205: ...r 0x03C USARTn_TXDOUBLE W TX Buffer Double Data Register 0x040 USARTn_IF R Interrupt Flag Register 0x044 USARTn_IFS W1 Interrupt Flag Set Register 0x048 USARTn_IFC W1 Interrupt Flag Clear Register 0x04C USARTn_IEN RW Interrupt Enable Register 0x050 USARTn_IRCTRL RW IrDA Control Register 0x054 USARTn_ROUTE RW I O Routing Register 0x058 USARTn_INPUT RW USART Input Register 0x05C USARTn_I2SCTRL RW I2...

Page 206: ...ng and parity errors have no effect on receiver 1 Framing and parity errors disable the receiver 22 ERRSDMA 0 RW Halt DMA On Error When set DMA requests will be cleared on framing and parity errors asynchronous mode only Value Description 0 Framing and parity errors have no effect on DMA requests from the USART 1 DMA requests from the USART are blocked while the PERR or FERR interrupt flags are se...

Page 207: ...register determines the action to be performed when slave select is configured as an input and driven low while in master mode Value Mode Description 0 NOACTION No action taken 1 GOTOSLAVEMODE Go to slave mode 10 MSBF 0 RW Most Significant Bit First Decides whether data is sent with the least significant bit first or the most significant bit first Value Description 0 Data is sent with the least si...

Page 208: ...llision check is enabled The receiver must be enabled for the check to be performed 1 LOOPBK 0 RW Loopback Enable Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication Value Description 0 The receiver is connected to and receives data from U S n_RX 1 The receiver is connected to and receives data from U S n_TX 0 SYNC 0 RW USART Synchronous...

Page 209: ...ontains 7 data bits 5 EIGHT Each frame contains 8 data bits 6 NINE Each frame contains 9 data bits 7 TEN Each frame contains 10 data bits 8 ELEVEN Each frame contains 11 data bits 9 TWELVE Each frame contains 12 data bits 10 THIRTEEN Each frame contains 13 data bits 11 FOURTEEN Each frame contains 14 data bits 12 FIFTEEN Each frame contains 15 data bits 13 SIXTEEN Each frame contains 16 data bits ...

Page 210: ... CLEARRX 0 W1 Clear RX Set to clear receive buffer and the RX shift register 10 CLEARTX 0 W1 Clear TX Set to clear transmit buffer and the TX shift register 9 TXTRIDIS 0 W1 Transmitter Tristate Disable Disables tristating of the transmitter output 8 TXTRIEN 0 W1 Transmitter Tristate Enable Tristates the transmitter output 7 RXBLOCKDIS 0 W1 Receiver Block Disable Set to clear RXBLOCK resulting in a...

Page 211: ...ect a single right data or left data Only used in I2S mode 8 RXFULL 0 R RX FIFO Full Set when the RXFIFO is full Cleared when the receive buffer is no longer full When this bit is set there is still room for one more frame in the receive shift register 7 RXDATAV 0 R RX Data Valid Set when data is available in the receive buffer Cleared when the receive buffer is empty 6 TXBL 1 R TX Buffer Level In...

Page 212: ...vices always write bits to 0 More information in Section 2 1 p 3 15 5 7 USARTn_RXDATAX RX Buffer Data Extended Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERR PERR RXDATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 M...

Page 213: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 0 0 0x000 Access R R R R R R Name FERR1 PERR1 RXDATA1 FERR0 PERR0 RXDATA0 Bit Name Reset Access Description 31 FERR1 0 R Data Framing Error 1 Set if data in buffer has a framing error Can be the result of a break condition 30 PERR1 0 R Data Parity Error 1 Set if data in buffer has a parity error asynchronous mode only 29 25 Reserved To ensur...

Page 214: ...5 5 11 USARTn_RXDATAXP RX Buffer Data Extended Peek Register Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERRP PERRP RXDATAP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 FERRP 0 R Data Fra...

Page 215: ...R RX Data 1 Peek Second frame read from FIFO 15 FERRP0 0 R Data Framing Error 0 Peek Set if data in buffer has a framing error Can be the result of a break condition 14 PERRP0 0 R Data Parity Error 0 Peek Set if data in buffer has a parity error asynchronous mode only 13 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 RXDATAP0 0...

Page 216: ...iated at the first opportunity 15 5 14 USARTn_TXDATA TX Buffer Data Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 TXDATA 0x00 W TX Data Th...

Page 217: ...on Set to disable transmitter and release data bus directly after transmission 13 TXBREAK0 0 W Transmit Data As Break Set to send data as a break Recipient will see a framing error or a break condition depending on its configuration and the value of WDATA 12 TXTRIAT0 0 W Set TXTRI After Transmission Set to tristate transmitter by setting TXTRI after transmission 11 UBRXAT0 0 W Unblock RX After Tra...

Page 218: ...is cleared 8 PERR 0 R Parity Error Interrupt Flag Set when a frame with a parity error asynchronous mode only is received while RXBLOCK is cleared 7 TXUF 0 R TX Underflow Interrupt Flag Set when operating as a synchronous slave no data is available in the transmit buffer when the master starts transmission of a new frame 6 TXOF 0 R TX Overflow Interrupt Flag Set when a write is done to the transmi...

Page 219: ...g Error Interrupt Flag Write to 1 to set the FERR interrupt flag 8 PERR 0 W1 Set Parity Error Interrupt Flag Write to 1 to set the PERR interrupt flag 7 TXUF 0 W1 Set TX Underflow Interrupt Flag Write to 1 to set the TXUF interrupt flag 6 TXOF 0 W1 Set TX Overflow Interrupt Flag Write to 1 to set the TXOF interrupt flag 5 RXUF 0 W1 Set RX Underflow Interrupt Flag Write to 1 to set the RXUF interru...

Page 220: ...0 W1 Clear RX Overflow Interrupt Flag Write to 1 to clear the RXOF interrupt flag 3 RXFULL 0 W1 Clear RX Buffer Full Interrupt Flag Write to 1 to clear the RXFULL interrupt flag 2 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 TXC 0 W1 Clear TX Complete Interrupt Flag Write to 1 to clear the TXC interrupt flag 15 5 20 USARTn_IEN ...

Page 221: ...nterrupt on TX complete 15 5 21 USARTn_IRCTRL IrDA Control Register Offset Bit Position 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0 0x0 0 Access RW RW RW RW RW Name IRPRSEN IRPRSSEL IRFILT IRPW IREN Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sect...

Page 222: ...sition 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 0 Access RW RW RW RW RW Name LOCATION CLKPEN CSPEN TXPEN RXPEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATION 0x0 RW I O Location Decides the location of the USART I ...

Page 223: ...ty with future devices always write bits to 0 More information in Section 2 1 p 3 4 RXPRS 0 RW PRS RX Enable When set the PRS channel selected as input to RX 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 0 RXPRSSEL 0x0 RW RX PRS Channel Select Select PRS channel as input to RX Value Mode Description 0 PRSCH0 PRS Channel 0 select...

Page 224: ... bit word 8 bit data 7 W8D8 8 bit word 8 bit data 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 DELAY 0 RW Delay on I2S data Set to add a one cycle delay between a transition on the word clock and the start of the I2S word Should be set for standard I2S format 3 DMASPLIT 0 RW Separate DMA Request For Left Right Data When set D...

Page 225: ...n low energy mode EM2 with most core functionality turned off the LEUART can wait for an incoming UART frame while having an extremely low energy consumption When a UART frame is completely received the CPU can quickly be woken up Alternatively multiple frames can be transferred via the Direct Memory Access DMA module into RAM memory before waking up the CPU Received data can optionally be blocked...

Page 226: ...utomatically IrDA modulator pulse generator pulse extender Multi processor mode Loopback mode Half duplex communication Communication debugging PRS RX input 16 3 Functional Description An overview of the LEUART module is shown in Figure 16 1 p 226 Figure 16 1 LEUART Overview TX Buffer TX Shift Register Signal frame interrupt RX Buffer RX Shift Register LEUn_RX UART Control and status Peripheral Bu...

Page 227: ...p bits INV should only be changed while the receiver is disabled 16 3 1 1 Parity Bit Calculation and Handling Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming frames The possible parity modes are defined in Table 16 1 p 227 When even parity is chosen a parity bit is inserted to make the number of high bits data parity even If odd parity is chos...

Page 228: ...w data a frame from the transmit buffer is loaded into the shift register and if the transmitter is enabled transmission begins When the frame has been transmitted a new frame is loaded into the shift register if available and transmission continues If the transmit buffer is empty the transmitter goes to an idle state waiting for a new frame to become available Transmission is enabled through the ...

Page 229: ...trol d0 d2 d4 d6 d8 d7 d5 d3 d1 control TXDATA TXDATAX BIT8DV Transmit buffer 0 16 3 4 2 Frame Transmission Control The transmission control bits which can be written using LEUARTn_TXDATAX affect the transmission of the written frame The following options are available Generate break By setting WBREAK the output will be held low during the first stop bit period to generate a framing error A receiv...

Page 230: ...ndicate the buffer overflow The receiver can be disabled by setting the command bit RXDIS in LEUARTn_CMD Any frame currently being received when the receiver is disabled is discarded Whether or not the receiver is enabled at a given time can be read out from RXENS in LEUARTn_STATUS 16 3 5 1 Receive Buffer Operation When data becomes available in the receive buffer the RXDATAV flag in LEUARTn_STATU...

Page 231: ... is set The first is when an address frame is received when in operating in multi processor mode as shown in Section 16 3 5 8 p 233 The other case is when receiving a start frame when SFUBRX in LEUARTn_CTRL is set see Section 16 3 5 6 p 232 Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in LEUARTn_IF being set while RXBLOCK is set Hardware ...

Page 232: ... result of noise and baud rate errors but can also be the result of a break generated by the transmitter on purpose When a framing error is detected the framing error bit FERR in the received frame is set The interrupt flag FERR in LEUARTn_IF is also set Frames with framing errors are loaded into the receive buffer like regular frames FERR can be accessed by reading the frame from the receive buff...

Page 233: ... multiple processors and maintain compatibility with the USART the LEUART supports a multi processor mode In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address When multi processor mode is enabled an incoming 9 bit frame with the 9th bit equal to the value of MPAB in LEUARTn_CTRL is identified as an address frame When an a...

Page 234: ...et the LEUART automatically tristates LEUn_TX whenever the transmitter is inactive It is then the responsibility of the software protocol to make sure the transmitter is not transmitting data whenever incoming data is expected The transmitter can also be tristated from software by configuring the GPIO pin as an input and disabling the LEUART output on LEUn_TX Note Another way to tristate the trans...

Page 235: ...te to the transmit buffer using the registers LEUARTn_TXDATA and LEUARTn_TXDATAX and it can read from receive buffer using the registers LEUARTn_RXDATA and LEUARTn_RXDATAX This enables single byte transfers and 9 bit data control status bits transfers both to and from the LEUART The DMA will start up the HFRCO and run from this when it is waken by the LEUART in EM2 The HFRCO is disabled once the t...

Page 236: ...red using PULSEW in LEUARTn_PULSECTRL The generated pulse width is PULSEW 1 cycles of the 32 768 kHz clock which makes pulse width from 31 25µs to 500µs possible Since the incoming signal is only sampled on positive clock edges the width of the incoming pulses must be at least two 32 768 kHz clock periods wide for reliable detection by the LEUART receiver They must also be shorter than half a UART...

Page 237: ...ister 0x03C LEUARTn_PULSECTRL RW Pulse Control Register 0x040 LEUARTn_FREEZE RW Freeze Register 0x044 LEUARTn_SYNCBUSY R Synchronization Busy Register 0x054 LEUARTn_ROUTE RW I O Routing Register 0x0AC LEUARTn_INPUT RW LEUART Input Register 16 5 Register Description 16 5 1 LEUARTn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bi...

Page 238: ...the frame as a multi processor address frame 9 MPM 0 RW Multi Processor Mode Set to enable multi processor mode Value Description 0 The 9th bit of incoming frames have no special function 1 An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 8 SFUBRX 0 RW Start Frame UnBlock RX Clears RXB...

Page 239: ...held high when the transmitter is inactive INV inverts the inactive state 1 LEUn_TX is tristated when the transmitter is inactive 16 5 2 LEUARTn_CMD Command Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1...

Page 240: ...eceive buffer is empty 4 TXBL 1 R TX Buffer Level Indicates the level of the transmit buffer Set when the transmit buffer is empty and cleared when it is full 3 TXC 0 R TX Complete Set when a transmission has completed and no more data is available in the transmit buffer Cleared when a new transmission starts 2 RXBLOCK 0 R Block Incoming Data When set the receiver discards incoming frames An incom...

Page 241: ...ess RW Name STARTFRAME Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 STARTFRAME 0x000 RW Start Frame When a frame matching STARTFRAME is detected by the receiver STARTF interrupt flag is set and if SFUBRX is set RXBLOCK is cleared The start frame is be loaded into the RX buffer 16 5 6 LEUAR...

Page 242: ...14 PERR 0 R Receive Data Parity Error Set if data in buffer has a parity error 13 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 RXDATA 0x000 R RX Data Use this register to access data read from the LEUART Buffer is cleared on read access 16 5 8 LEUARTn_RXDATA Receive Buffer Data Register Offset Bit Position 0x01C 31 30 29 28 2...

Page 243: ...ure devices always write bits to 0 More information in Section 2 1 p 3 8 0 RXDATAP 0x000 R RX Data Peek Use this register to access data read from the LEUART 16 5 10 LEUARTn_TXDATAX Transmit Buffer Data Extended Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 244: ...ta Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 T...

Page 245: ... the transmit buffer for a new frame 0 TXC 0 R TX Complete Interrupt Flag Set after a transmission when both the TX buffer and shift register are empty 16 5 13 LEUARTn_IFS Interrupt Flag Set Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 Name SIGF STARTF MPAF FERR PER...

Page 246: ...ore information in Section 2 1 p 3 10 SIGF 0 W1 Clear Signal Frame Interrupt Flag Write to 1 to clear the SIGF interrupt flag 9 STARTF 0 W1 Clear Start Frame Interrupt Flag Write to 1 to clear the STARTF interrupt flag 8 MPAF 0 W1 Clear Multi Processor Address Frame Interrupt Flag Write to 1 to clear the MPAF interrupt flag 7 FERR 0 W1 Clear Framing Error Interrupt Flag Write to 1 to clear the FER...

Page 247: ...ble Enable interrupt on multi processor address frame 7 FERR 0 RW Framing Error Interrupt Enable Enable interrupt on framing error 6 PERR 0 RW Parity Error Interrupt Enable Enable interrupt on parity error 5 TXOF 0 RW TX Overflow Interrupt Enable Enable interrupt on TX overflow 4 RXUF 0 RW RX Underflow Interrupt Enable Enable interrupt on RX underflow 3 RXOF 0 RW RX Overflow Interrupt Enable Enabl...

Page 248: ... 5 4 3 2 1 0 Reset 0 Access RW Name REGFREEZE Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 REGFREEZE 0 RW Register Update Freeze When set the update of the LEUART is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Ea...

Page 249: ...d 16 5 19 LEUARTn_ROUTE I O Routing Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 Access RW RW RW Name LOCATION TXPEN RXPEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATION 0x0 RW I O Location D...

Page 250: ...s always write bits to 0 More information in Section 2 1 p 3 4 RXPRS 0 RW PRS RX Enable When set the PRS channel selected as input to RX 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 0 RXPRSSEL 0x0 RW RX PRS Channel Select Select PRS channel as input to RX Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Chann...

Page 251: ... The Timer can also count events and control other peripherals through the PRS which offloads the CPU and reduce energy consumption 17 1 Introduction The 16 bit general purpose Timer has 3 compare capture channels for input capture and compare Pulse Width Modulation PWM output 17 2 Features 16 bit auto reload up down counter Dedicated 16 bit reload register which serves as counter maximum 3 Compar...

Page 252: ...rflow Overflow Compare Capture event 17 3 Functional Description An overview of the TIMER module is shown in Figure 17 1 p 252 The Timer module consists of a 16 bit up down counter with 3 Compare Capture channels connected to pins TIMn_CC0 TIMn_CC1 and TIMn_CC2 Figure 17 1 TIMER Block Overview Compare and PWM config Compare and PWM config Compare and PWM config TnCCR0 15 0 TnCCR1 15 0 Compare Matc...

Page 253: ...s set when the counter value shifts from 0 to the next value when counting down In down count mode the next value is TIMERn_TOP In up down count mode the next value is 1 Update event is set on overflow in up count mode and on underflow in down count or up down count mode This event is used to time updates of buffered values 17 3 1 2 Operation Figure 17 2 p 254 shows the hardware Timer Counter cont...

Page 254: ...K can be used as a source with a configurable prescale factor of 2 PRESC where PRESC is an integer between 0 and 10 which is set in PRESC in TIMERn_CTRL However if 2x Count Mode is enabled and the Compare Capture channels are put in PWM mode the CC output is updated on both clock edges so prescaling the peripheral clock will result in incorrect result The prescaler is stopped and reset when the ti...

Page 255: ...01 in CLKSEL in TIMERn_CTRL and OSMEN is set a CC1 capture event will not take place on the update event CC1 rising edge that stops the Timer 17 3 1 5 Top Value Buffer The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB buffer register When writing to the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event...

Page 256: ...er a counter reset from the interrupt service routine By connecting a periodic signal from another timer as input capture on Compare Capture Channel 2 it is also possible to calculate speed and acceleration Figure 17 7 TIMER Quadrature Decoder Configuration Counter Controlled by TIMERn_CTRL Compare Capture channel 1 Controlled by TIMERn_CC1_CTRL Compare Capture channel 0 Controlled by TIMERn_CC0_C...

Page 257: ...p 257 Table 17 2 TIMER Counter Response in X4 Decoding Mode Channel A Channel B Opposite Channel Rising Falling Rising Falling Channel A 0 Decrement Increment Channel A 1 Increment Decrement Channel B 0 Increment Decrement Channel B 1 Decrement Increment Figure 17 9 TIMER X4 Decoding Mode Channel A Channel B 3 4 5 6 7 8 9 10 11 3 4 5 6 7 8 9 10 11 2 2 CNT 17 3 1 6 3 TIMER Rotational Position To ca...

Page 258: ...ompare PWM the behavior of the Compare Capture registers TIMERn_CCx_CCV and buffer registers TIMERn_CCx_CCVB change depending on the mode the channel is set in 17 3 2 2 1 Input Capture mode When running in Input Capture mode TIMERn_CCx_CCV and TIMERn_CCx_CCVB form a FIFO buffer and new capture values are added on a capture event see Figure 17 11 p 259 The first capture can always be read from TIME...

Page 259: ...STATUS indicates whether the TIMERn_CCx_CCVB register contains data that have not yet been written to the TIMERn_CCx_CCV register Note that when writing 0 to TIMERn_CCx_CCVB the CCV value is updated when the timer counts from 0 to 1 Thus the compare match for the next period will not happen until the timer reaches 0 again on the way down Figure 17 12 TIMER Output Compare PWM Buffer Functionality C...

Page 260: ...Capture Channel should be set to capture on a falling edge of the input signal To start the measuring period on either a falling edge or measure the low pulse width of a signal opposite polarities should be chosen Figure 17 14 TIMER Period and or Pulse width Capture 0 Input CNT Clear Start Input Capture frequency capture Input Capture pulse width capture 17 3 2 4 Compare Each Compare Capture chann...

Page 261: ...h and the result is found in the CCPOL bits in TIMERn_STATUS It is also possible to configure the CCPOL to always track the inputs by setting ATI in TIMERn_CTRL The COIST bit in TIMERn_CCx_CTRL is the initial state of the compare PWM output The COIST bit can also be used as an initial value to the compare outputs on a reload start when RSSCOIST is set in TIMERn_CTRL Also the resulting output can b...

Page 262: ...Single slope PWM If the counter is set to up count and the Compare Capture channel is put in PWM mode single slope PWM output will be generated see Figure 17 18 p 262 In up count mode the PWM period is TOP 1 cycles and the PWM output will be high for a number of cycles equal to TIMERn_CCx_CCV This means that a constant high output is achieved by setting TIMER_CCx to TOP 1 or higher The PWM resolut...

Page 263: ... the 2x mode is to generate 2x PWM frequency when the Compare Capture channel is put in PWM mode Since the PWM output is updated on both edges of the clock frequency prescaling will result in incorrect result in this mode The PWM resolution in bits is then given by Equation 17 6 p 263 TIMER 2x PWM Resolution Equation RPWM2xmode log TOP 2 1 log 2 17 6 The PWM frequency is given by Equation 17 7 p 2...

Page 264: ...unt Mode When the Timer is set in 2x mode the TIMER will count up down by two This will in effect make any odd Top value be rounded down to the closest even number Similarly any odd CC value will generate a match on the closest lower even value as shown in Figure 17 21 p 264 Figure 17 21 TIMER CC out in 2x mode 2 4 2 0 2 0 Clock CC Out 4 2 4 2 0 2 0 4 Top 5 CC 1 Top 5 CC 2 The mode is enabled by s...

Page 265: ...x_CCV TIMERn_CCx_CCVB register pair If the interrupt flags are set and the corresponding interrupt enable bits in TIMERn_IEN are set high the Timer will send out an interrupt request Each of the events will also lead to a one HFPERCLKTIMERn cycle high pulse on individual PRS outputs Each of the events will also set a DMA request when they occur The different DMA requests are cleared when certain a...

Page 266: ... Control Register 0x034 TIMERn_CC0_CCV RWH CC Channel Value Register 0x038 TIMERn_CC0_CCVP R CC Channel Value Peek Register 0x03C TIMERn_CC0_CCVB RWH CC Channel Buffer Register 0x040 TIMERn_CC1_CTRL RW CC Channel Control Register 0x044 TIMERn_CC1_CCV RWH CC Channel Value Register 0x048 TIMERn_CC1_CCVP R CC Channel Value Peek Register 0x04C TIMERn_CC1_CCVB RWH CC Channel Buffer Register 0x050 TIMER...

Page 267: ... divided by 4 3 DIV8 The HFPERCLK is divided by 8 4 DIV16 The HFPERCLK is divided by 16 5 DIV32 The HFPERCLK is divided by 32 6 DIV64 The HFPERCLK is divided by 64 7 DIV128 The HFPERCLK is divided by 128 8 DIV256 The HFPERCLK is divided by 256 9 DIV512 The HFPERCLK is divided by 512 10 DIV1024 The HFPERCLK is divided by 1024 23 18 Reserved To ensure compatibility with future devices always write b...

Page 268: ...Value Description 0 Timer is frozen in debug mode 1 Timer is running in debug mode 5 QDM 0 RW Quadrature Decoder Mode Selection This bit sets the mode for the quadrature decoder Value Mode Description 0 X2 X2 mode selected 1 X4 X4 mode selected 4 OSMEN 0 RW One shot Mode Enable Enable disable one shot mode 3 SYNC 0 RW Timer Start Stop Reload Synchronization When this bit is set the Timer is starte...

Page 269: ...on 2 1 p 3 26 CCPOL2 0 R CC2 Polarity In Input Capture mode this bit indicates the polarity of the edge that triggered capture in TIMERn_CC2_CCV In Compare PWM mode this bit indicates the polarity of the selected input to CC channel 2 These bits are cleared when CCMODE is written to 0b00 Off Value Mode Description 0 LOWRISE CC2 polarity low level rising edge 1 HIGHFALL CC2 polarity high level fall...

Page 270: ...MERn_CC2_CCVB registers contain data which have not been written to TIMERn_CC2_CCV These bits are only used in output compare pwm mode and are cleared when CCMODE is written to 0b00 Off Value Description 0 TIMERn_CC2_CCVB does not contain valid data 1 TIMERn_CC2_CCVB contains valid data which will be written to TIMERn_CC2_CCV on the next update event 9 CCVBV1 0 R CC1 CCVB Valid This field indicate...

Page 271: ...sable Compare Capture ch 1 input capture buffer overflow interrupt 8 ICBOF0 0 RW CC Channel 0 Input Capture Buffer Overflow Interrupt Enable Enable disable Compare Capture ch 0 input capture buffer overflow interrupt 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 CC2 0 RW CC Channel 2 Interrupt Enable Enable disable Compare Captu...

Page 272: ...are Capture channel 0 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 UF 0 R Underflow Interrupt Flag This bit indicates that there has been an underflow 0 OF 0 R Overflow Interrupt Flag This bit indicates that there has been an overflow 17 5 6 TIMERn_IFS Interrupt Flag Set Register Offset Bit Position 0x014 31 30 29 28 27 26 25...

Page 273: ...t Capture Buffer Overflow Interrupt Flag Clear Writing a 1 to this bit will clear Compare Capture channel 2 input capture buffer overflow interrupt flag 9 ICBOF1 0 W1 CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear Writing a 1 to this bit will clear Compare Capture channel 1 input capture buffer overflow interrupt flag 8 ICBOF0 0 W1 CC Channel 0 Input Capture Buffer Overflow Interr...

Page 274: ...nter Top Value These bits hold the TOP value for the counter 17 5 9 TIMERn_TOPB Counter Top Value Buffer Register Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name TOPB Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Secti...

Page 275: ... 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 CDTI2PEN 0 RW CC Channel 2 Complementary Dead Time Insertion Pin Enable Enable disable CC channel 2 complementary dead time insertion output connection to pin 9 CDTI1PEN 0 RW CC Channel 1 Complementary Dead...

Page 276: ...DGE BOTH 25 24 ICEDGE 0x0 RW Input Capture Edge Select These bits control which edges the edge detector triggers on The output is used for input capture and external clock input Value Mode Description 0 RISING Rising edges detected 1 FALLING Falling edges detected 2 BOTH Both edges detected 3 NONE No edge detection signal is left as it is 23 22 Reserved To ensure compatibility with future devices ...

Page 277: ... compare match 1 TOGGLE Toggle output on compare match 2 CLEAR Clear output on compare match 3 SET Set output on compare match 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 COIST 0 RW Compare Output Initial State This bit is only used in Output Compare and PWM mode When this bit is set in compare mode the output is set high wh...

Page 278: ...tents of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle In compare mode this fields holds the compare value 17 5 14 TIMERn_CCx_CCVP CC Channel Value Peek Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access R Name CCVP Bit Name Reset Access Description 31 16 Reserved To ensure ...

Page 279: ...o ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 24 DTPRSEN 0 RW DTI PRS Source Enable Enable disable PRS as DTI input 23 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 4 DTPRSSEL 0x0 RW DTI PRS Source Channel Select Select which PRS channel to listen to Value Mode Description ...

Page 280: ...r the rising edge Value Description DTRISET Rise time of DTRISET 1 prescaled HFPERCLK cycles 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 0 DTPRESC 0x0 RW DTI Prescaler Setting Select prescaler for DTI Value Mode Description 0 DIV1 The HFPERCLK is undivided 1 DIV2 The HFPERCLK is divided by 2 2 DIV4 The HFPERCLK is divided by...

Page 281: ...served To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 DTPRS1FSEL 0x0 RW DTI PRS Fault Source 1 Select Select PRS channel for fault source 1 Value Mode Description 0 PRSCH0 PRS Channel 0 selected as fault source 1 1 PRSCH1 PRS Channel 1 selected as fault source 1 2 PRSCH2 PRS Channel 2 selected as fault source 1 3 PRSCH3 PRS Channel 3 sel...

Page 282: ...nables disables output generation for the CC2 output from the DTI 1 DTOGCC1EN 0 RW DTI CC1 Output Generation Enable This bit enables disables output generation for the CC1 output from the DTI 0 DTOGCC0EN 0 RW DTI CC0 Output Generation Enable This bit enables disables output generation for the CC0 output from the DTI 17 5 20 TIMERn_DTFAULT DTI Fault Register Offset Bit Position 0x080 31 30 29 28 27...

Page 283: ...ckup fault 2 DTDBGFC 0 W1 DTI Debugger Fault Clear Write 1 to this bit to clear debugger fault 1 DTPRS1FC 0 W1 DTI PRS1 Fault Clear Write 1 to this bit to clear PRS 1 fault 0 DTPRS0FC 0 W1 DTI PRS0 Fault Clear Write 1 to this bit to clear PRS 0 fault 17 5 22 TIMERn_DTLOCK DTI Configuration Lock Register Offset Bit Position 0x088 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 284: ...endly microcontrollers 2014 07 02 Tiny Gecko Family d0034_Rev1 20 284 www silabs com Bit Name Reset Access Description Mode Value Description Write Operation LOCK 0 Lock TIMER DTI registers UNLOCK 0xCE80 Unlock TIMER DTI registers ...

Page 285: ...r and is clocked either by a 32 768 Hz crystal oscillator a 32 768 Hz RC oscillator or a 1 kHz RC oscillator In addition to energy modes EM0 and EM1 the RTC is also available in EM2 This makes it ideal for keeping track of time since the RTC is enabled in EM2 where most of the device is powered down Using the 1 kHz ULFRCO as input clock the RTC can be used for timekeeping all the way down to EM3 T...

Page 286: ...enabled and will on an overflow simply wrap around and continue counting The RTC is cleared when it is disabled The timer value is both readable and writable and the RTC always starts counting from 0 when enabled The value of the counter can be read or modified using the RTC_CNT register 18 3 1 1 Clock Source The RTC clock source and its prescaler value are defined in the Register Description sect...

Page 287: ...ue for the RTC and the timer is cleared on a compare match with compare channel 0 If using the COMP0TOP setting make sure to set this bit prior to or at the same time the EN bit is set Setting COMP0TOP after the EN bit is set may cause unintended operation i e if CNT COMP0 18 3 2 1 LETIMER Triggers A compare event on either of the compare channels can start the LETIMER See the LETIMER documentatio...

Page 288: ...LFRCO as clock source This is done by clearing CMU_LFCLKSEL_LFA and setting CMU_LFCLKSEL_LFAE to 1 This will make the RTC use the internal 1 kHz ultra low frequency RC oscillator ULFRCO consuming very little energy Please note that the ULFRCO is not accurate over temperature and voltage and it should be verified that the ULFRCO fulfills the timekeeping needs of the application before using this in...

Page 289: ...n about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access RW RW RW Name COMP0TOP DEBUGRUN EN Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP0TOP 0 RW Compare ...

Page 290: ...are Value Register 0 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000000 Access RW Name COMP0 Bit Name Reset Access Description 31 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section...

Page 291: ...ble as a PRS signal 18 5 5 RTC_IF Interrupt Flag Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name COMP1 COMP0 OF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP1 0 R Compare Match 1 Interr...

Page 292: ...Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP1 0 W1 Clear Compare match 1 Interrupt Flag Write to 1 to clear the COMP1 interrupt flag 1 COMP0 0 W1 Clear Compare match 0 Interrupt Flag Write to 1 to clear the COMP0 interrupt flag 0 OF 0 W1 Clear Overflow Interrupt Flag Write to 1 to clear the OF interrupt flag...

Page 293: ...multaneously Value Mode Description 0 UPDATE Each write access to an RTC register is updated into the Low Frequency domain as soon as possible 1 FREEZE The RTC is not updated with the new written value until the freeze bit is cleared 18 5 10 RTC_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res...

Page 294: ...M2 and EM3 19 1 Introduction The unique LETIMER TM the Low Energy Timer is a 16 bit timer that is available in energy mode EM2 and EM3 in addition to EM1 and EM0 Because of this it can be used for timing and output generation when most of the device is powered down allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum The LETIMER can be used...

Page 295: ...REP0 Repeat REP1 Repeat Buffer 1 LETIMER Control and Status Reload Update Update Stop 0 LFACLKLETIMERn Start RTC event SW pin ctrl LETn_O0 Pulse Control Underflow UF interrupt flag REP0 Zero REP0 interrupt flag Buffer Written Repeat load logic pin ctrl LETn_O1 Pulse Control Top load logic 1 REP1 Zero REP1 interrupt flag COMP1 Match COMP1 interrupt flag COMP0 Match COMP0 interrupt flag PRS CH1 PRS ...

Page 296: ...an for instance be used in conjunction with the buffered repeat mode to generate continually changing output waveforms Write operations to LETIMERn_COMP0 have priority over buffer loads 19 3 3 2 Repeat Modes By default the timer wraps around to the top value or 0xFFFF on each underflow and continues counting The repeat counters can be used to get more control of the operation of the timer includin...

Page 297: ...t to 0 and an underflow event will not be generated when LETIMERn_CNT wraps around to the top value or 0xFFFF Since no underflow event is generated no output action is performed LETIMERn_REP0 LETIMERn_REP1 LETIMERn_COMP0 and LETIMERn_COMP1 are also left untouched 19 3 3 2 2 One shot Mode The one shot repeat mode is the most basic repeat mode In this mode the repeat register LETIMERn_REP0 is decrem...

Page 298: ... as long as LETIMERn_REP1 is updated with a nonzero value before LETIMERn_REP0 is finished counting down If the timer is started when both LETIMERn_CNT and LETIMERn_REP0 are zero but LETIMERn_REP1 is non zero LETIMERn_REP1 is loaded into LETIMERn_REP0 and the counter counts the loaded number of times The state machine for the one shot repeat mode is shown in Figure 19 3 p 298 Used in conjunction w...

Page 299: ...much like the one shot repeat mode The difference is that where the one shot mode counts as long as LETIMERn_REP0 is larger than 0 the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0 As an example say LETIMERn_REP0 is 3 and LETIMERn_REP1 is 10 when the timer is started If no further interaction is done with the timer LETIMERn_REP0 will now be decremented 3 time...

Page 300: ... fLFACKL_LETIMERn 32 768 2 LETIMERn 19 1 where the exponent LETIMERn is a 4 bit value in the CMU_LFAPRESC0 register To use this module the LE interface clock must be enabled in CMU_HFCORECLKEN0 in addition to the module clock 19 3 3 4 RTC Trigger The LETIMER can be configured to start on compare match events from the Real Time Counter RTC If RTCC0TEN in LETIMERn_CTRL is set the LETIMER will start ...

Page 301: ...FOA0 and UFOA1 in LETIMERn_CTRL UFOA0 defines the action on output 0 and is connected to LETIMERn_REP0 while UFOA1 defines the action on output 1 and is connected to LETIMERn_REP1 The possible actions are defined in Table 19 2 p 301 Table 19 2 LETIMER Underflow Output Actions UF0A0 UF0A1 Mode Description 00 Idle The output is held at its idle value 01 Toggle The output is toggled on LETIMERn_CNT u...

Page 302: ...n LETn_O0 UFOA0 01 LETn_O0 UFOA0 10 LETn_O0 UFOA0 00 3 0 UFIF 3 0 For the example in Figure 19 7 p 302 the One shot repeat mode has been selected and LETIMERn_REP0 has been written to 3 The resulting behavior is pretty similar to that shown in Figure 6 but in this case the timer stops after counting to zero LETIMERn_REP0 times By using LETIMERn_REP0 the user has full control of the number of pulse...

Page 303: ...3 START 19 3 5 PRS Output The LETIMER outputs can be routed out onto the PRS system LETn_O0 can be routed to PRS channel 0 and LETn_1O can be routed to PRS channel 1 Enabling the RRS connection can be done by setting SOURCESEL to LETIMERx and SIGSEL to LETIMERxCHn in PRS_CHx_CTRL The PRS register description can be found in Section 13 5 p 140 19 3 6 Examples This section presents a couple of usage...

Page 304: ... can update LETIMERn_COMP1 and LETIMERn_REP1 to change the number of pulses and pulse period in each train but if changes are not required software does not have to update the registers between each pulse train For the example in Figure 19 9 p 304 the initial values cause the LETIMER to generate two pulses with 3 cycle periods or a single pulse 3 cycles wide every time the LETIMER is started After...

Page 305: ...0IF UFIF UFIF UFIF UFIF Int flags set Stop final values Write COMP1 2 REP1 2 UFIF UFIF UFIF REP0IF 4 4 4 4 4u 4u 4u 2 2 2u 2u 2u 2u 2 2 1 1 2 2 0 1 2u 2u REP0IF LFACLKLETIMERn LETn_O0 UFOA0 01 LETn_O1 UFOA0 10 Pulse Seq 1 Pulse Seq 2 Pulse Seq 3 4 4 4 4 4 4 2 2 2 2 2 0 0 2u The first two sequences are loaded into the LETIMER before the timer is started LETIMERn_COMP0 is set to 2 cycles 1 and LETIM...

Page 306: ...ral ways of generating PWM output with the LETIMER but the most straight forward way is using the PWM output mode This mode is enabled by setting UFOA0 or OFUA1 in LETIMERn_CTRL to 3 In PWM mode the output is set idle on timer underflow and active on LETIMERn_COMP1 match so if for instance COMP0TOP 1 and OPOL0 0 in LETIMERn_CTRL LETIMERn_COMP0 determines the PWM period and LETIMERn_LETIMERn_COMP1 ...

Page 307: ...his will make the RTC use the internal 1 kHz ultra low frequency RC oscillator ULFRCO consuming very little energy Please note that the ULFRCO is not accurate over temperature and voltage and it should be verified that the ULFRCO fulfills the timekeeping needs of the application before using this in the design 19 3 8 Register access This module is a Low Energy Peripheral and supports immediate syn...

Page 308: ...x034 LETIMERn_SYNCBUSY R Synchronization Busy Register 0x040 LETIMERn_ROUTE RW I O Routing Register 19 5 Register Description 19 5 1 LETIMERn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0x0 0x0 0x0 Acce...

Page 309: ... 1 Defines the action on LETn_O1 on a LETIMER underflow Value Mode Description 0 NONE LETn_O1 is held at its idle value as defined by OPOL1 1 TOGGLE LETn_O1 is toggled on CNT underflow 2 PULSE LETn_O1 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow The output then returns to its idle value as defined by OPOL1 3 PWM LETn_O1 is set idle on CNT underflow and active on compare match...

Page 310: ...O1 0 W1 Clear Toggle Output 1 Set to drive toggle output 1 to its idle value 3 CTO0 0 W1 Clear Toggle Output 0 Set to drive toggle output 0 to its idle value 2 CLEAR 0 W1 Clear LETIMER Set to clear LETIMER 1 STOP 0 W1 Stop LETIMER Set to stop LETIMER 0 START 0 W1 Start LETIMER Set to start LETIMER 19 5 3 LETIMERn_STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 ...

Page 311: ... to read the current value of the LETIMER 19 5 5 LETIMERn_COMP0 Compare Value Register 0 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name COMP0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with...

Page 312: ... please see Section 5 3 p 20 Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name REP0 Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 REP0 0x00 RW Repeat Counter 0 Optional repeat counter 19 5 8 LETIMERn_REP...

Page 313: ...es zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag 2 UF 0 R Underflow Interrupt Flag Set on LETIMER underflow 1 COMP1 0 R Compare Match 1 Interrupt Flag Set when LETIMER reaches the value of COMP1 0 COMP0 0 R Compare Match 0 Interrupt Flag Set when LETIMER reaches the value of COMP0 19 5 10 LETIMERn_IFS Interrupt Flag Set Register Offset Bit Position 0x024 31 30 29 28 2...

Page 314: ... to clear the REP1 interrupt flag 3 REP0 0 W1 Clear Repeat Counter 0 Interrupt Flag Write to 1 to clear the REP0 interrupt flag 2 UF 0 W1 Clear Underflow Interrupt Flag Write to 1 to clear the UF interrupt flag 1 COMP1 0 W1 Clear Compare Match 1 Interrupt Flag Write to 1 to clear the COMP1 interrupt flag 0 COMP0 0 W1 Clear Compare Match 0 Interrupt Flag Write to 1 to clear the COMP0 interrupt flag...

Page 315: ...n set the update of the LETIMER is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to a LETIMER register is updated into the Low Frequency domain as soon as possible 1 FREEZE The LETIMER is not updated with the new written value 19 5 14 LETIMERn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0...

Page 316: ...ION OUT1PEN OUT0PEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATION 0x0 RW I O Location Decides the location of the LETIMER I O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 7 2 Reserved To ensure compatibility with future devic...

Page 317: ...otations 20 1 Introduction The Pulse Counter PCNT can be used for counting incoming pulses on a single input or to decode quadrature encoded inputs It can run from the internal LFACLK EM0 EM2 while counting pulses on the PCNTn_S0IN pin or using this pin as an external clock source EM0 EM3 that runs both the PCNT counter and register access 20 2 Features 16 bit counter with reload register Auxiliar...

Page 318: ...TRL register Additionally the PCNTn_S0IN input may be inverted so that falling edges are counted by setting the EDGE bit in the PCNTn_CTRL register If S1CDIR is cleared PCNTn_S0IN is the only observed input in this mode The PCNTn_S0IN input is sampled by the LFACLK and the number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT The counter may be configured to count down b...

Page 319: ...ion of a rotating shaft as illustrated by Figure 20 2 p 319 hence the direction of the counter register PCNTn_CNT is controlled automatically Figure 20 2 PCNT Quadrature Coding X X 1 cycle sector 4 states 01 11 10 00 X X 1 cycle sector 4 states 00 10 11 01 X sensor position Clockwise direction Counter clockwise direction PCNTn_S0IN PCNTn_S1IN PCNTn_S0IN PCNTn_S1IN PCNTn_CNT Reset 0 0 1 2 PCNTn_CNT...

Page 320: ...er will always wrap to TOP 2 on underflows and overflows This takes the counter away from the area where it might overflow or underflow removing the problem Given a starting value of 0 for the counter the absolute count value when hysteresis is enabled can be calculated with the equations Equation 20 1 p 320 or Equation 20 2 p 320 depending on whether the TOP value is even or odd Absolute position...

Page 321: ...gister accesses to Low Energy Peripherals Note PCNTn_TOP and PCNTn_CNT are read only registers When writing to PCNTn_TOPB make sure that the counter value PCNTn_CNT can not exceed the value written to PCNTn_TOPB within two clock cycles 20 3 5 Clock Sources The 32 kHz LFACLK is one of two possible clock sources The clock select register is described in Chapter 11 p 99 The default clock source is th...

Page 322: ...ag UF is set when the counter counts down from 0 I e when the value of the counter is 0 and a new pulse is received The PCNTn_CNT register is loaded with the PCNTn_TOP value after this event The overflow interrupt flag OF is set when the counter counts up from the PCNTn_TOP reload value I e if PCNTn_CNT PCNTn_TOP and a new pulse is received The PCNTn_CNT register is loaded with the value 0 after t...

Page 323: ...on 20 5 1 PCNTn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0 0 0 0 0 0 0x0 Access RW RW RW RW RW RW RW RW RW Name AUXCNTEV CNTEV S1CDIR HYST RSTEN FILT EDGE CNTDIR MODE Bit Name Reset Access Description 31 1...

Page 324: ...ter is only available in OVSSINGLE mode 3 EDGE 0 RW Edge Select Determines the polarity of the incoming edges This bit should be written when PCNT is in DISABLE mode otherwise the behavior is unpredictable This bit is ignored in EXTCLKSINGLE mode Value Mode Description 0 POS Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode 1 NEG Negative edges on the PCNTn_S0IN inputs are coun...

Page 325: ...eset 0 Access R Name DIR Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 DIR 0 R Current Counter Direction Current direction status of the counter This bit is valid in EXTCLKQUAD mode only Value Mode Description 0 UP Up counter mode clockwise in EXTCLKQUAD mode with the NEDGE bit in PCNTn_CTRL ...

Page 326: ...s written to the PCNTn_CNT register when counting past this value 20 5 6 PCNTn_TOPB Top Value Buffer Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00FF Access RW Name TOPB Bit Name Reset Access Description 31 16 Reserved To ensur...

Page 327: ...Access W1 W1 W1 W1 Name AUXOF DIRCNG OF UF Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 AUXOF 0 W1 Auxiliary Overflow Interrupt Set Write to 1 to set the auxiliary overflow interrupt flag 2 DIRCNG 0 W1 Direction Change Detect Interrupt Set Write to 1 to set the direction change interrupt fla...

Page 328: ...scription 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 AUXOF 0 RW Auxiliary Overflow Interrupt Enable Enable the auxiliary overflow interrupt 2 DIRCNG 0 RW Direction Change Detect Interrupt Enable Enable the direction change detect interrupt 1 OF 0 RW Overflow Interrupt Enable Enable the overflow interrupt 0 UF 0 RW Underflo...

Page 329: ...the PCNT clock domain is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to a PCNT register is updated into the Low Frequency domain as soon as possible 1 FREEZE The PCNT clock domain is not updated with the new written value 20 5 13 PCNTn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x030 3...

Page 330: ...Name S1PRSEN S1PRSSEL S0PRSEN S0PRSSEL Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 S1PRSEN 0 RW S1IN PRS Enable When set the PRS channel is selected as input to S1IN 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 6 S1PRS...

Page 331: ...write bits to 0 More information in Section 2 1 p 3 2 0 S0PRSSEL 0x0 RW S0IN PRS Channel Select Select PRS channel as input to S0IN Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel ...

Page 332: ...oder is capable of processing sensor data without CPU intervention A large result buffer allows the chip to remain in EM2 for long periods of time while autonomously collecting data 21 1 Introduction LESENSE is a low energy sensor interface which utilizes on chip peripherals to perform measurement of a configurable set of sensors The results from sensor measurements can be processed by the LESENSE...

Page 333: ...k is used for storage of configuration and measurement results This allows LESENSE to have a relatively large result buffer enabling the chip to remain in a low energy mode for long periods of time while collecting sensor data Figure 21 1 LESENSE block diagram LESENSE Counter Compare Decoder PRS input DAC0 AUXHFRCO ACMP1 ACMP1_CHn LES_ALTEXn Register bitfields overridden by LESENSE Scaler 1 25 V 2...

Page 334: ...wing the decoder state to define which configuration to use enables easy implementation of for instance hysteresis as different threshold values can be used for the same channel depending on the state of the application Table 21 1 p 334 summarizes how channel configuration is selected for different setting of SCANCONF Table 21 1 LESENSE scan configuration selection SCANCONF DIRMAP INVMAP TOGGLE DE...

Page 335: ... and a high frequency timer running on AUXHFRCO Timing of the excite phase is done using these timers and can be either a number of prescaled AUXHFRCO cycles or a number of prescaled LFACLKLESENSE cycles depending on which one is selected in EXCLK The prescaling can be done by configuring LFPRESC in TIMCTRL for the low frequency timer and the high frequency timer prescaling factor is configured in...

Page 336: ...to perform sensor excitation on another pin than the one to be measured When ALTEX in CHx_INTERACT is set the excitation will occur on the alternative excite pin associated with the given channel All LESENSE channels mapped to ACMP0 have their alternative channel mapped to the corresponding channel on ACMP1 and vice versa Alternatively the alternative excite pins can be routed to the LES_ALTEX pin...

Page 337: ... channel and alternative excite pin in the IDLECONF and ALTEXCONF registers The modes available are the same as the modes available in the excitation phase In the measure phase the pin mode on the active channel is always disabled analog input To enable LESENSE to control GPIO the pin has to be enabled in the ROUTE register In addition the given pin must be configured as push pull IDLECONF configu...

Page 338: ...d many other decoding schemes can be described as a finite state machine To support this type of decoding without CPU intervention LESENSE includes a highly configurable decoder capable of decoding input from up to four sensors The decoder is implemented as a programmable state machine with up to 16 states When doing a sensor scan the results from the sensors are placed in the decoder input regist...

Page 339: ...based on these PRS outputs If SETIF is set the DECODER interrupt flag will be set when the transition occurs If INTMAP in DECCTRL and SETIF is set a transition from state x will set the CHx interrupt flag in addition to the DECODER flag Setting CHAIN in STx_TCONFA enables the decoder to evaluate more than two possible transitions for each state If none of the transitions defined in STx_TCONFA or S...

Page 340: ...SKAi 1 Y N SENSORSTATE MASKBi 1 COMPBi 1 MASKBi 1 Y N SENSORSTATE changed ERRCHK 1 Y N CHAINi 1 1 Y N Note If only one transition from a state is used STx_TCONFA and STx_TCONFB should be configured equally To prevent unnecessary interrupt requests or PRS outputs when the decoder toggles back and forth between two states a hysteresis option is available The hysteresis function is triggered if a typ...

Page 341: ... data read from the result read register BUFDATA is the oldest unread result The location pointers are available in PTR The result buffer has three status flags BUFDATAV BUFHALFFULL and BUFFULL The flags indicate when new data is available when the buffer is half full and when it is full respectively The interrupt flag BUFDATAV is set when data is available in the buffer BUFLEVEL is set when the b...

Page 342: ...L The DAC interface runs on AUXHFRCO and will enable this when it is needed The DACPRESC bit field in PERCTRL is used to prescale the AUXHFRCO to achieve wanted clock frequency for the LESENSE DAC interface The frequency should not exceed 500kHz i e DACPRESC has to be set to at least 1 The prescaler may also be used to tune how long the DAC should drive its outputs in sample off mode Bias configur...

Page 343: ...t to DONTTOUCH LESENSE will not control the bias module 21 3 11 DMA requests LESENSE issues a DMA request when the result buffer is either full or half full depending on the configuration of BUFIDL in CTRL The request is cleared when the buffer level drops below the threshold defined in BUFIDL A single DMA request is also set whenever there is unread data in the buffer DMAWU in CTRL configures at ...

Page 344: ...PLEDLY LFACLKLESENSE seconds MEASUREDLY should be set to 0 5 Set CTRTHRESHOLD to an appropriate value An interrupt will be issued if the counter value for a sensor is below this threshold after the measurement phase 6 Enable interrupts on channels 0 through 3 7 Start scan sequence by writing a 1 to START in CMD In a capacitive sense application it might be required to calibrate the threshold value...

Page 345: ...to damp the oscillations 4 Configure the ACMP to use scaled Vdd as negative input refer to ACMP chapter for details 5 Enable and configure PCNT and asynchronous PRS 6 Configure the GPIOs used as PUSHPULL 7 Configure the following bit fields in CHx_CONF for channels 0 through 3 a Set EXCLK to AUXHFRCO AUXHFRCO is needed to achieve short excitation time b Set EXTIME to an appropriate value Excitatio...

Page 346: ...d by the decoder b Configure the remaining bit fields in STx_TCONFA and STx_TCONFB as described in Table 21 3 p 346 Table 21 3 LESENSE decoder configuration Register TCONFA_NEXTSTATE TCONFA_COMP TCONFA_PRSACT TCONFB_NEXTSTATE TCONFB_COMP TCONFB_PRSACT ST0 1 0b001 UP 7 0b100 DOWN ST1 2 0b011 UP 0 0b000 DOWN ST2 3 0b010 UP 1 0b001 DOWN ST3 4 0b110 UP 2 0b011 DOWN ST4 5 0b111 UP 3 0b010 DOWN ST5 6 0b...

Page 347: ...6 0b0010 0b1000 ST2_TCONFA 8 0b1000 0b0111 1 ST2_TCONFB 4 0b0011 0b1000 ST3_TCONFA 0 0b0000 0b1000 0 ST3_TCONFB 0 0b0000 0b1000 ST4_TCONFA 8 0b1000 0b0111 1 ST4_TCONFB 6 0b0010 0b1000 ST5_TCONFA 2 0b0001 0b1000 0 ST5_TCONFB 2 0b0001 0b1000 ST6_TCONFA 8 0b1000 0b0111 1 ST6_TCONFB 0 0b0000 0b1000 ST7_TCONFA 4 0b0011 0b1000 0 ST7_TCONFB 4 0b0011 0b1000 2 To initialize the decoder run one scan and rea...

Page 348: ...iguration 0x040 LESENSE_IF R Interrupt Flag Register 0x044 LESENSE_IFC W1 Interrupt Flag Clear Register 0x048 LESENSE_IFS W1 Interrupt Flag Set Register 0x04C LESENSE_IEN RW Interrupt Enable Register 0x050 LESENSE_SYNCBUSY R Synchronization Busy Register 0x054 LESENSE_ROUTE RW I O Routing Register 0x058 LESENSE_POWERDOWN RW LESENSE RAM power down register 0x200 LESENSE_ST0_TCONFA RW State transiti...

Page 349: ...U 0x0 RW DMA wake up from EM2 Value Mode Description 0 DISABLE No DMA wake up from EM2 1 BUFDATAV DMA wake up from EM2 when data is valid in the result buffer 2 BUFLEVEL DMA wake up from EM2 when the result buffer is full half full depending on BUFIDL configuration 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 18 BUFIDL 0 RW Resu...

Page 350: ...defines the CONF registers to be used 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 2 PRSSEL 0x0 RW Scan start PRS select Select PRS source for scan start if SCANMODE is set to PRS Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 P...

Page 351: ...IV64 The period counter clock frequency is LFACLKLESENSE 64 7 DIV128 The period counter clock frequency is LFACLKLESENSE 128 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 4 LFPRESC 0x0 RW Prescaling factor for low frequency timer Value Mode Description 0 DIV1 Low frequency timer is clocked with LFACLKLESENSE 1 1 DIV2 Low frequen...

Page 352: ...CMP1 Value Mode Description 0 DISABLE LESENSE does not control ACMP1 1 MUX LESENSE controls the input mux POSSEL of ACMP1 2 MUXTHRES LESENSE controls the input mux and the threshold value VDDLEVEL of ACMP1 21 20 ACMP0MODE 0x0 RW ACMP0 mode Configure how LESENSE controls ACMP0 Value Mode Description 0 DISABLE LESENSE does not control ACMP0 1 MUX LESENSE controls the input mux POSSEL of ACMP0 2 MUXT...

Page 353: ... 0 is driven in sample hold mode 3 SAMPLEOFF DAC channel 0 is driven in sample off mode 1 DACCH1DATA 0 RW DAC CH1 data selection Configure DAC data control Value Mode Description 0 DACDATA DAC data is defined by CH1DATA in the DAC interface 1 ACMPTHRES DAC data is defined by ACMPTHRES in CHx_INTERACT 0 DACCH0DATA 0 RW DAC CH0 data selection Value Mode Description 0 DACDATA DAC data is defined by C...

Page 354: ...ices always write bits to 0 More information in Section 2 1 p 3 16 14 PRSSEL1 0x0 RW Select PRS input for the bit 1 of the LESENSE decoder Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected a...

Page 355: ...uppressing changes on PRS channel 0 2 INTMAP 0 RW Enable decoder to channel interrupt mapping When set a transition from state x in the decoder will set interrupt flag CHx 1 ERRCHK 0 RW Enable check of current state When set the decoder checks the current state in addition to the states defined in TCONF 0 DISABLE 0 RW Disable the decoder When set the decoder is disabled When disabled the decoder w...

Page 356: ...anning of sensors If issued during a scan the command will take effect after scan completion 0 START 0 W1 Start scanning of sensors 21 5 7 LESENSE_CHEN Channel enable Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW N...

Page 357: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access R R R R R R Name DACACTIVE SCANACTIVE RUNNING BUFFULL BUFHALFFULL BUFDATAV Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 DACACTIVE 0 R LESENSE DAC interface is active 4 SCANACTIVE 0 R LESENS...

Page 358: ...se bits show the index of the oldest unread data in the result buffer Incremented on read from BUFDATA 21 5 11 LESENSE_BUFDATA Result buffer data register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXX Access R Name BUFDATA Bit Name R...

Page 359: ... 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 0 DECSTATE 0x0 RWH Shows the current decoder state 21 5 14 LESENSE_SENSORSTATE Decoder input register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 360: ... CH14 output is low in idle phase 3 DACCH1 CH14 output is connected to DAC CH1 output in idle phase 27 26 CH13 0x0 RW Channel 13 idle phase configuration Value Mode Description 0 DISABLE CH13 output is disabled in idle phase 1 HIGH CH13 output is high in idle phase 2 LOW CH13 output is low in idle phase 3 DACCH1 CH13 output is connected to DAC CH1 output in idle phase 25 24 CH12 0x0 RW Channel 12 ...

Page 361: ...le phase 1 HIGH CH6 output is high in idle phase 2 LOW CH6 output is low in idle phase 11 10 CH5 0x0 RW Channel 5 idle phase configuration Value Mode Description 0 DISABLE CH5 output is disabled in idle phase 1 HIGH CH5 output is high in idle phase 2 LOW CH5 output is low in idle phase 9 8 CH4 0x0 RW Channel 4 idle phase configuration Value Mode Description 0 DISABLE CH4 output is disabled in idle...

Page 362: ...nfiguration Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name AEX7 AEX6 AEX5 AEX4 AEX3 AEX2 AEX1 AEX0 IDLECONF7 IDLECONF6 IDLECONF5 IDLE...

Page 363: ... phase configuration Value Mode Description 0 DISABLE ALTEX4 output is disabled in idle phase 1 HIGH ALTEX4 output is high in idle phase 2 LOW ALTEX4 output is low in idle phase 7 6 IDLECONF3 0x0 RW ALTEX3 idle phase configuration Value Mode Description 0 DISABLE ALTEX3 output is disabled in idle phase 1 HIGH ALTEX3 output is high in idle phase 2 LOW ALTEX3 output is low in idle phase 5 4 IDLECONF...

Page 364: ...e bits to 0 More information in Section 2 1 p 3 22 CNTOF 0 R Set when the LESENSE counter overflows 21 BUFOF 0 R Set when the result buffer overflows 20 BUFLEVEL 0 R Set when the data buffer is full 19 BUFDATAV 0 R Set when data is available in the result buffer 18 DECERR 0 R Set when the decoder detects an error 17 DEC 0 R Set when the decoder has issued and interrupt request 16 SCANCOMPLETE 0 R ...

Page 365: ... W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name CNTOF BUFOF BUFLEVEL BUFDATAV DECERR DEC SCANCOMPLETE CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Bit Name Reset Access Description 31 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 CNTOF 0 W1 Write to 1 to clear CNTOF interrupt...

Page 366: ...upt flag 4 CH4 0 W1 Write to 1 to clear CH4 interrupt flag 3 CH3 0 W1 Write to 1 to clear CH3 interrupt flag 2 CH2 0 W1 Write to 1 to clear CH2 interrupt flag 1 CH1 0 W1 Write to 1 to clear CH1 interrupt flag 0 CH0 0 W1 Write to 1 to clear CH0 interrupt flag 21 5 19 LESENSE_IFS Interrupt Flag Set Register Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 367: ...upt flag 14 CH14 0 W1 Write to 1 to set the CH14 interrupt flag 13 CH13 0 W1 Write to 1 to set the CH13 interrupt flag 12 CH12 0 W1 Write to 1 to set the CH12 interrupt flag 11 CH11 0 W1 Write to 1 to set the CH11 interrupt flag 10 CH10 0 W1 Write to 1 to set the CH10 interrupt flag 9 CH9 0 W1 Write to 1 to set the CH9 interrupt flag 8 CH8 0 W1 Write to 1 to set the CH8 interrupt flag 7 CH7 0 W1 W...

Page 368: ... interrupt flag 20 BUFLEVEL 0 RW Set to enable interrupt on the BUFLEVEL interrupt flag 19 BUFDATAV 0 RW Set to enable interrupt on the BUFDATAV interrupt flag 18 DECERR 0 RW Set to enable interrupt on the DECERR interrupt flag 17 DEC 0 RW Set to enable interrupt on the DEC interrupt flag 16 SCANCOMPLETE 0 RW Set to enable interrupt on the SCANCOMPLETE interrupt flag 15 CH15 0 RW Set to enable int...

Page 369: ...ys write bits to 0 More information in Section 2 1 p 3 26 EVAL 0 R LESENSE_CHx_EVAL Register Busy Set when the value written to LESENSE_CHx_EVAL is being synchronized 25 INTERACT 0 R LESENSE_CHx_INTERACT Register Busy Set when the value written to LESENSE_CHx_INTERACT is being synchronized 24 TIMING 0 R LESENSE_CHx_TIMING Register Busy Set when the value written to LESENSE_CHx_TIMING is being sync...

Page 370: ...ten to LESENSE_CMD is being synchronized 4 BIASCTRL 0 R LESENSE_BIASCTRL Register Busy Set when the value written to LESENSE_BIASCTRL is being synchronized 3 DECCTRL 0 R LESENSE_DECCTRL Register Busy Set when the value written to LESENSE_DECCTRL is being synchronized 2 PERCTRL 0 R LESENSE_PERCTRL Register Busy Set when the value written to LESENSE_PERCTRL is being synchronized 1 TIMCTRL 0 R LESENS...

Page 371: ... 0 RW ALTEX1 Pin Enable 16 ALTEX0PEN 0 RW ALTEX0 Pin Enable 15 CH15PEN 0 RW CH15 Pin Enable 14 CH14PEN 0 RW CH14 Pin Enable 13 CH13PEN 0 RW CH13 Pin Enable 12 CH12PEN 0 RW CH12 Pin Enable 11 CH11PEN 0 RW CH11 Pin Enable 10 CH10PEN 0 RW CH10 Pin Enable 9 CH9PEN 0 RW CH9 Pin Enable 8 CH8PEN 0 RW CH8 Pin Enable 7 CH7PEN 0 RW CH7 Pin Enable 6 CH6PEN 0 RW CH6 Pin Enable 5 CH5PEN 0 RW CH5 Pin Enable 4 C...

Page 372: ...ase see Section 5 3 p 20 Offset Bit Position 0x200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset X X 0xX 0xX 0xX 0xX Access RW RW RW RW RW RW Name CHAIN SETIF PRSACT NEXTSTATE MASK COMP Bit Name Reset Access Description 31 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 18 CHAIN X RW En...

Page 373: ...d when sensor state equals COMP 21 5 25 LESENSE_STx_TCONFB State transition configuration B Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset X 0xX 0xX 0xX 0xX Access RW RW RW RW RW Name SETIF PRSACT NEXTSTATE MASK COMP Bit Name Reset Access De...

Page 374: ...compare value State transition is triggered when sensor state equals COMP 21 5 26 LESENSE_BUFx_DATA Scan results Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x280 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXX Access RW Name DATA Bit Name Reset Access Description 31 16 Reserved To en...

Page 375: ...RW RW RW RW RW Name ALTEX SAMPLECLK EXCLK EXMODE SETIF SAMPLE ACMPTHRES Bit Name Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 19 ALTEX X RW Use alternative excite pin If set alternative excite pin will be used for excitation 18 SAMPLECLK X RW Select clock used for timing of sample delay Value Mode Des...

Page 376: ... 1 0 Reset X X X X 0xXXXX Access RW RW RW RW RW Name SCANRESINV STRSAMPLE DECODE COMP COMPTHRES Bit Name Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 19 SCANRESINV X RW Enable inversion of result If set the bit stored in SCANRES will be inverted 18 STRSAMPLE X RW Select if counter result should be sto...

Page 377: ... the world s most energy friendly microcontrollers 2014 07 02 Tiny Gecko Family d0034_Rev1 20 377 www silabs com ...

Page 378: ...rnal reference 22 1 Introduction The Analog Comparator is used to compare the voltage of two analog inputs with a digital output indicating which input voltage is higher Inputs can either be one of the selectable internal references or from external pins Response time and thereby also the current consumption can be configured by altering the current supply to the comparator 22 2 Features 8 selecta...

Page 379: ...an the voltage on the negative input the digital output is high and vice versa The output of the comparator can be read in the ACMPOUT bit in ACMPn_STATUS It is possible to switch inputs while the comparator is enabled but all other configuration should only be changed while the comparator is disabled 22 3 1 Warm up Time The analog comparator is enabled by setting the EN bit in ACMPn_CTRL When thi...

Page 380: ...le 22 1 Bias Configuration Bias Current µA HYSTSEL 0 BIASPROG FULLBIAS 0 HALFBIAS 1 FULLBIAS 0 HALFBIAS 0 FULLBIAS 1 HALFBIAS 1 FULLBIAS 1 HALFBIAS 0 0b0000 0 05 0 1 3 3 6 5 0b0001 0 1 0 2 6 5 13 0b0010 0 2 0 4 13 26 0b0011 0 3 0 6 20 39 0b0100 0 4 0 8 26 52 0b0101 0 5 1 0 33 65 0b0110 0 6 1 2 39 78 0b0111 0 7 1 4 46 91 0b1000 1 0 2 0 65 130 0b1001 1 1 2 2 72 143 0b1010 1 2 2 4 78 156 0b1011 1 3 2...

Page 381: ... on the mux inputs when the EN bit is toggled 22 3 5 Capacitive Sense Mode The analog comparator includes specialized hardware for capacitive sensing of passive push buttons Such buttons are traces on PCB laid out in a way that creates a parasitic capacitor between the button and the ground node Because a human finger will have a small intrinsic capacitance to ground the capacitance of the button ...

Page 382: ...through the EDGE bit in ACMPn_IEN The edge interrupt can also be used to wake up the device from EM3 EM1 The analog comparator also includes an interrupt flag WARMUP in ACMPn_IF which is set when a warm up sequence has finished An interrupt request will be sent if the WARMUP interrupt flag in ACMPn_IF is set and enabled through the WARMUP bit in ACMPn_IEN The comparator output is also available as...

Page 383: ...as current in accordance with Table 22 1 p 380 30 HALFBIAS 1 RW Half Bias Current Set this bit to 1 to halve the bias current in accordance with Table 22 1 p 380 29 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 27 24 BIASPROG 0x7 RW Bias Configuration These bits control the bias current level in accordance with Table 22 1 p 380 2...

Page 384: ...T6 50 mV hysteresis 7 HYST7 57 mV hysteresis 3 GPIOINV 0 RW Comparator GPIO Output Invert Set this bit to 1 to invert the comparator alternate function output to GPIO Value Mode Description 0 NOTINV The comparator output to GPIO is not inverted 1 INV The comparator output to GPIO is inverted 2 INACTVAL 0 RW Inactive Value The value of this bit is used as the comparator output when the comparator i...

Page 385: ...bled 1 Low power mode enabled 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 8 VDDLEVEL 0x00 RW VDD Reference Level Select scaling factor for VDD reference level VDD_SCALED VDD VDDLEVEL 63 7 4 NEGSEL 0x8 RW Negative Input Select Select negative input Value Mode Description 0 CH0 Channel 0 as negative input 1 CH1 Channel 1 as...

Page 386: ...mparator Active Analog comparator active status 22 5 4 ACMPn_IEN Interrupt Enable Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name WARMUP EDGE Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARM...

Page 387: ... EDGE Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARMUP 0 W1 Warm up Interrupt Flag Set Write to 1 to set warm up finished interrupt flag 0 EDGE 0 W1 Edge Triggered Interrupt Flag Set Write to 1 to set edge triggered interrupt flag 22 5 7 ACMPn_IFC Interrupt Flag Clear Register Offset Bit ...

Page 388: ...PPEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATION 0x0 RW I O Location Decides the location of the ACMP I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 7 1 Reserved To ensure compatibility with future devices always write bits to 0 More inform...

Page 389: ...arator is used to monitor the supply voltage from software An interrupt can be generated when the supply falls below or rises above a programmable threshold Note Note that VCMP comes in addition to the Power on Reset and Brown out Detector peripherals that both generate reset signals when the voltage supply is insufficient for reliable operation VCMP does not generate reset only interrupt Also not...

Page 390: ...od is called the warm up time The warm up time is a configurable number of HFPERCLK cycles set in WARMTIME which should be set to at least 10 µs When the comparator is enabled and warmed up the VCMPACT bit in VCMP_STATUS will be set to indicate that the comparator is active As long as the comparator is not enabled or not warmed up VCMPACT will be cleared and the comparator output value is set to t...

Page 391: ...t uninteresting input fluctuations around zero and only show changes that are big enough to breach the hysteresis threshold Figure 23 2 VCMP 20 mV Hysteresis Enabled InNEG VCMPOUT with hysteresis InNEG 20mV InNEG 20mV VCMPOUT without hysteresis Time InPOS 23 3 4 Input Selection The positive comparator input is always connected to the scaled power supply input The negative comparator input is conne...

Page 392: ... comparator output respectively An interrupt request will be sent if the EDGE interrupt flag in VCMP_IF is set and enabled through the EDGE bit in VCMPn_IEN The edge interrupt can also be used to wake up the device from EM3 EM1 VCMP also includes an interrupt flag WARMUP in VCMP_IF which is set when a warm up sequence has finished An interrupt request will be sent if the WARMUP interrupt flag in V...

Page 393: ...ore information in Section 2 1 p 3 30 HALFBIAS 1 RW Half Bias Current Set this bit to 1 to halve the bias current Table 23 1 p 390 29 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 27 24 BIASPROG 0x7 RW VCMP Bias Programming Value These bits control the bias current level Table 23 1 p 390 23 18 Reserved To ensure compatibility wit...

Page 394: ...disable voltage supply comparator 23 5 2 VCMP_INPUTSEL Input Selection Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access RW RW Name LPREF TRIGLEVEL Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 LPREF 0 ...

Page 395: ...e Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARMUP 0 RW Warm up Interrupt Enable Enable disable interrupt on finished warm up 0 EDGE 0 RW Edge Trigger Interrupt Enable Enable disable edge triggered interrupt 23 5 5 VCMP_IF Interrupt Flag Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 2...

Page 396: ...Flag Set Write to 1 to set warm up finished interrupt flag 0 EDGE 0 W1 Edge Triggered Interrupt Flag Set Write to 1 to set edge triggered interrupt flag 23 5 7 VCMP_IFC Interrupt Flag Clear Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access W1 W1 Name WARMUP EDGE Bit Name Reset Access Description 31 2 Reserved T...

Page 397: ... duty cycled to reduce the energy consumption 24 1 Introduction The ADC is a Successive Approximation Register SAR architecture with a resolution of up to 12 bits at up to one million samples per second The integrated input mux can select inputs from 8 external pins and 6 internal signals 24 2 Features Programmable resolution 6 8 12 bit 13 prescaled clock ADC_CLK cycles per conversion Maximum 1 MS...

Page 398: ...pt flag set when overwriting unread results Hardware oversampling support 1st order accumulate and dump filter From 2 to 4096 oversampling ratio OSR Results in 16 bit representation Enabled individually for scan sequence and single sample mode Common OSR select Individually selectable voltage reference for scan and single mode Internal 1 25V reference Internal 2 5V reference VDD Internal 5 V diffe...

Page 399: ...tion during the approximation phase The acquisition time can be configured independently for scan and single conversions see Section 24 3 7 p 403 by setting AT in ADCn_SINGLECTRL ADCn_SCANCTRL The acquisition times can be set to any integer power of 2 from 1 to 256 ADC_CLK cycles Note For high impedance sources the acquisition time should be adjusted to allow enough time for the internal sample ca...

Page 400: ...cted for scan mode can be kept warm If a different bandgap reference is selected for single mode the warm up time still applies NORMAL ADC and references are shut off when there are no samples waiting a in Figure 24 3 p 401 shows this mode used with an internal bandgap reference Figure d shows this mode when using VDD or an external reference FASTBG Bandgap warm up is eliminated but with reduced r...

Page 401: ...SINGLECTRL and ADCn_SCANCTRL For offset calibration purposes it is possible to internally short the differential ADC inputs and thereby measure a 0 V differential Differential 0 V is selected by writing the DIFF bit to 1 and INPUTSEL to 4 in ADCn_SINGLECTRL Calibration is described in detail in Section 24 3 10 p 406 Note When VDD 3 is sampled the acquisition time should be above a lower limit The ...

Page 402: ... for the device 24 3 5 Reference Selection The reference voltage can be selected from these sources 1 25 V internal bandgap 2 5 V internal bandgap VDD 5 V internal differential bandgap External single ended input from Ch 6 Differential input 2x Ch 6 Ch 7 Unbuffered 2xVDD The 2 5 V reference needs a supply voltage higher than 2 5 V The differential 5 V reference needs a supply voltage higher than 2...

Page 403: ...scan samples 24 3 7 1 Single Sample Mode The single sample mode can be used to convert a single sample either once per trigger or repetitively The configuration of the single sample mode is done in the ADCn_SINGLECTRL register and the results are found in the ADCn_SINGLEDATA register The SINGLEDV bit in ADCn_STATUS is set high when there is valid data in the result register and is cleared when the...

Page 404: ...cleared The SINGLEACT and SCANACT bits in ADCn_STATUS are set high when the modes are actively converting or have pending conversions It is also possible to trigger conversions from PRS signals The system requires one HFPERCLK cycle pulses to trigger conversions Setting PRSEN in ADCn_SINGLECTRL ADCn_SCANCTRL enables triggering from PRS input Which PRS channel to listen to is defined by PRSSEL in A...

Page 405: ... individually for each mode Set RES in ADCn_SINGLECTRL ADCn_SCANCTRL to 0x3 The oversampling rate OVSRSEL in ADCn_CTRL can be set to any integer power of 2 from 2 to 4096 and the configuration is shared between the scan and single sample mode OVSRSEL field in ADCn_CTRL With oversampling each selected input is sampled a number given by the OVSR of times and the results are filtered by a first order...

Page 406: ...es have separate interrupt flags indicating finished conversions Setting one of these flags will result in an ADC interrupt if the corresponding interrupt enable bit is set in ADCn_IEN In addition to the finished conversion flags there is a scan and single sample result overflow flag which signalizes that a result from a scan sequence or single sample has been overwritten before being read A finis...

Page 407: ...of the ADCn_SINGLECTRL register to 16CYCLES 3 Set the INPUTSEL bitfield of the ADCn_SINGLECTRL register to DIFF0 and set the DIFF bitfield to 1 for enabling differential input Since the input voltage is 0 the expected ADC output is the half of the ADC code range as it is in differential mode 4 A binary search is used to find the offset calibration value Set the SINGLESTART bit in the ADCn_CMD regi...

Page 408: ...W Calibration Register 0x03C ADCn_BIASPROG RW Bias Programming Register 24 5 Register Description 24 5 1 ADCn_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x1F 0x00 0x0 0 0x0 Access RW RW RW RW RW RW Name OVSRSEL TIMEBASE PRESC LPFMODE TAILGATE WARMUPMODE Bit Name Reset Access Description 31 28 Reser...

Page 409: ... bits to 0 More information in Section 2 1 p 3 5 4 LPFMODE 0x0 RW Low Pass Filter Mode These bits control the filtering of the ADC input Details on the filter characteristics can be found in the device datasheets Value Mode Description 0 BYPASS No filter or decoupling capacitor 1 DECAP On chip decoupling capacitor selected 2 RCFILT On chip RC filter selected 3 TAILGATE 0 RW Conversion Tailgating E...

Page 410: ...inates Value Mode Description 0 CH0 Single ended mode SCANDATA result originates from ADCn_CH0 Differential mode SCANDATA result originates from ADCn_CH0 ADCn_CH1 1 CH1 Single ended mode SCANDATA result originates from ADCn_CH1 Differential mode SCANDATA result originates from ADCn_CH2_ADCn_CH3 2 CH2 Single ended mode SCANDATA result originates from ADCn_CH2 Differential mode SCANDATA result origi...

Page 411: ...Select PRS trigger for single sample Value Mode Description 0 PRSCH0 PRS ch 0 triggers single sample 1 PRSCH1 PRS ch 1 triggers single sample 2 PRSCH2 PRS ch 2 triggers single sample 3 PRSCH3 PRS ch 3 triggers single sample 4 PRSCH4 PRS ch 4 triggers single sample 5 PRSCH5 PRS ch 5 triggers single sample 6 PRSCH6 PRS ch 6 triggers single sample 7 PRSCH7 PRS ch 7 triggers single sample 27 25 Reserv...

Page 412: ...ct input to ADC single sample mode in either single ended mode or differential mode DIFF 0 Mode Value Description CH0 0 ADCn_CH0 CH1 1 ADCn_CH1 CH2 2 ADCn_CH2 CH3 3 ADCn_CH3 CH4 4 ADCn_CH4 CH5 5 ADCn_CH5 CH6 6 ADCn_CH6 CH7 7 ADCn_CH7 TEMP 8 Temperature reference VDDDIV3 9 VDD 3 VDD 10 VDD VSS 11 VSS VREFDIV2 12 VREF 2 DAC0OUT0 13 DAC0 output 0 DAC0OUT1 14 DAC0 output 1 DIFF 1 Mode Value Descriptio...

Page 413: ...ccess RW RW RW RW RW RW RW RW RW Name PRSSEL PRSEN AT REF INPUTMASK RES ADJ DIFF REP Bit Name Reset Access Description 31 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 PRSSEL 0x0 RW Scan Sequence PRS Trigger Select Select PRS trigger for scan sequence Value Mode Description 0 PRSCH0 PRS ch 0 triggers scan sequence 1 PRSCH1 PRS...

Page 414: ... Unbuffered 2xVDD 15 8 INPUTMASK 0x00 RW Scan Sequence Input Mask Set one or more bits in this mask to select which inputs are included the scan sequence in either single ended or differential mode DIFF 0 Mode Value Description CH0 00000001 ADCn_CH0 included in mask CH1 00000010 ADCn_CH1 included in mask CH2 00000100 ADCn_CH2 included in mask CH3 00001000 ADCn_CH3 included in mask CH4 00010000 ADC...

Page 415: ... 5 6 ADCn_IEN Interrupt Enable Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access RW RW RW RW Name SCANOF SINGLEOF SCAN SINGLE Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 SCANOF 0 RW Scan Result Over...

Page 416: ...lete when this bit is set 0 SINGLE 0 R Single Conversion Complete Interrupt Flag Indicates single conversion complete when this bit is set 24 5 8 ADCn_IFS Interrupt Flag Set Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access W1 W1 W1 W1 Name SCANOF SINGLEOF SCAN SINGLE Bit Name Reset Access Description 31 10...

Page 417: ... Flag Clear Write to 1 to clear single result overflow interrupt flag 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 SCAN 0 W1 Scan Conversion Complete Interrupt Flag Clear Write to 1 to clear scan conversion complete interrupt flag 0 SINGLE 0 W1 Single Conversion Complete Interrupt Flag Clear Write to 1 to clear single convers...

Page 418: ...t Data The register holds the results from the last scan conversion Reading this field clears the SCANDV bit in the ADCn_STATUS register 24 5 12 ADCn_SINGLEDATAP Single Conversion Result Data Peek Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATAP Bit Name Reset Access Description 31 0 DATAP ...

Page 419: ...value for the 1V25 internal reference during reset hence the reset value might differ from device to device The field is unsigned Higher values lead to higher ADC results 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 16 SCANOFFSET 0x00 RW Scan Mode Offset Calibration Value This register contains the offset calibration value us...

Page 420: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x7 1 0x7 Access RW RW RW Name COMPBIAS HALFBIAS BIASPROG Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 8 COMPBIAS 0x7 RW Comparator Bias Value These bits are used to adjust the bias current to the ADC Comparator 7 Reserv...

Page 421: ... convert a digital value to an analog output voltage The DAC is fully differential rail to rail with 12 bit resolution It has two single ended output buffers which can be combined into one differential output The DAC may be used for a number of different applications such as sensor interfaces or sound output 25 2 Features 500 ksamples s operation Two single ended output channels Can be combined in...

Page 422: ... Hold Mode In sample hold mode the DAC core converts data on a triggered conversion and then holds the output in a sample hold element When not converting the DAC core is turned off between samples which reduces the power consumption Because of output voltage drift the sample hold element will only hold the output for a certain period without a refresh conversion The reader is referred to the elec...

Page 423: ...a prescaler setting higher than 0 there will be an unpredictable delay from the time the conversion was triggered to the time the actual conversion takes place This is because the conversions is controlled by the prescaled clock and the conversion can arrive at any time during a prescaled clock DAC_CLK period However if the CH0PRESCRST bit in DACn_CTRL is set the prescaler will be reset every time...

Page 424: ...ngle Ended Output When operating in single ended mode the channel 0 output is on DACn_OUT0 and the channel 1 output is on DACn_OUT1 The output voltage can be calculated using Equation 25 2 p 424 DAC Single Ended Output Voltage VOUT VDACn_OUTx VSS Vref x CHxDATA 4095 25 2 where CHxDATA is a 12 bit unsigned integer 25 3 4 2 Differential Output When operating in differential mode both DAC outputs are...

Page 425: ...at new data can be written to the data registers Setting one of these flags will result in a DAC interrupt if the corresponding interrupt enable bit is set in DACn_IEN All generated interrupts from the DAC will activate the same interrupt vector when enabled The DAC has two PRS outputs which will carry a one cycle HFPERCLK high pulse when the corresponding channel has finished a conversion 25 3 7 ...

Page 426: ...hrough the CHxOFFSET bit fields Gain is calibrated in one common register field GAIN The gain calibration is linked to the reference and when the reference is changed the gain must be re calibrated Gain and offset for the 1V25 2V5 and VDD references are calibrated during production and the calibration values for these can be found in the Device Information page During reset the gain and offset cal...

Page 427: ...OPA0MUX RW Operational Amplifier Mux Configuration Register 0x060 DACn_OPA1MUX RW Operational Amplifier Mux Configuration Register 0x064 DACn_OPA2MUX RW Operational Amplifier Mux Configuration Register 25 5 Register Description 25 5 1 DACn_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0 0 0x1 ...

Page 428: ...start Value Description 0 Prescaler not reset on channel 0 start 1 Prescaler reset on channel 0 start 6 OUTENPRS 0 RW PRS Controlled Output Enable Enable PRS Control of DAC output enable Value Description 0 DAC output enable always on 1 DAC output enable controlled by PRS signal selected for CH1 5 4 OUTMODE 0x1 RW Output Mode Select output mode Value Mode Description 0 DISABLE DAC output to pin an...

Page 429: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 Access RW RW RW RW Name PRSSEL PRSEN REFREN EN Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 4 PRSSEL 0x0 RW Channel 0 PRS Trigger Select Select Channel 0 PRS input channel Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 0 conversion 1 ...

Page 430: ...igger Select Select Channel 1 PRS input channel Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 1 conversion 1 PRSCH1 PRS ch 1 triggers channel 1 conversion 2 PRSCH2 PRS ch 2 triggers channel 1 conversion 3 PRSCH3 PRS ch 3 triggers channel 1 conversion 4 PRSCH4 PRS ch 4 triggers channel 1 conversion 5 PRSCH5 PRS ch 5 triggers channel 1 conversion 6 PRSCH6 PRS ch 6 triggers channel 1 conv...

Page 431: ... channel 1 conversion complete interrupt 0 CH0 0 RW Channel 0 Conversion Complete Interrupt Enable Enable disable channel 0 conversion complete interrupt 25 5 6 DACn_IF Interrupt Flag Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access R R R R Name CH1UF CH0UF CH1 CH0 Bit Name Reset Access Description 31 6 Re...

Page 432: ...n complete interrupt flag 0 CH0 0 W1 Channel 0 Conversion Complete Interrupt Flag Set Write to 1 to set channel 0 conversion complete interrupt flag 25 5 8 DACn_IFC Interrupt Flag Clear Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access W1 W1 W1 W1 Name CH1UF CH0UF CH1 CH0 Bit Name Reset Access Description 3...

Page 433: ...hannel 1 Data Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 Access RW Name DATA Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 0 DATA 0x000 RW Channel 1 Data This register contains the value which will be ...

Page 434: ...future devices always write bits to 0 More information in Section 2 1 p 3 13 8 CH1OFFSET 0x00 RW Channel 1 Offset Calibration Value This register contains the offset calibration value used with channel 1 conversions This field is set to the production channel 1 offset calibration value for the 1V25 internal reference during reset hence the reset value might differ from device to device The field i...

Page 435: ...me Reset Access Description 31 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 24 OPA2SHORT 0 RW Short the non inverting and inverting input Set to short the non inverting and inverting input 23 OPA1SHORT 0 RW Short the non inverting and inverting input Set to short the non inverting and inverting input 22 OPA0SHORT 0 RW Short the ...

Page 436: ... input while output still remains rail to rail The input voltage to the opamp while HCM is disabled is restricted between VSS and VDD 1 2V 5 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 OPA2EN 0 RW OPA2 Enable Set to enable OPA2 clear to disable 1 OPA1EN 0 RW OPA1 Enable Set to enable OPA1 clear to disable CH1EN in DAC_CH1CTRL ...

Page 437: ... 8 7 RES7 R2 15 x R1 15 16 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 26 NEXTOUT 0 RW OPA0 Next Enable Makes output of OPA0 available to OPA1 25 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 23 22 OUTMODE 0x1 RW Output Select Select output channel Value Mode ...

Page 438: ...ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 0 POSSEL 0x0 RW OPA0 non inverting Input Mux These bits selects the source for the non inverting input on OPA0 Value Mode Description 0 DISABLE Input disabled 1 DAC DAC as input 2 POSPAD POS PAD as input 3 OPA0INP OPA0 as input 4 OPATAP OPA0 Resistor ladder as input 25 5 17 DACn_OPA1MUX Operationa...

Page 439: ... to enable output clear to disable output OUT ENABLE VALUE Description OUT0 xxxx1 Alternate Output 0 OUT1 xxx1x Alternate Output 1 OUT2 xx1xx Alternate Output 2 OUT3 x1xxx Alternate Output 3 OUT4 1xxxx Alternate Output 4 13 NPEN 0 RW OPA1 Negative Pad Input Enable Connects pad to the negative input mux 12 PPEN 0 RW OPA1 Positive Pad Input Enable Connects pad to the positive input mux 11 Reserved T...

Page 440: ...tion in Section 2 1 p 3 30 28 RESSEL 0x0 RW OPA2 Resistor Ladder Select Configures the resistor ladder tap for OPA2 Value Mode Resistor Value Inverting Mode Gain R2 R1 Non inverting Mode Gain 1 R2 R1 0 RES0 R2 1 3 x R1 1 3 1 1 3 1 RES1 R2 R1 1 2 2 RES2 R2 1 2 3 x R1 1 2 3 2 2 3 3 RES3 R2 2 x R1 2 1 5 3 1 5 4 RES4 R2 3 x R1 3 4 5 RES5 R2 4 1 3 x R1 4 1 3 5 1 3 6 RES6 R2 7 x R1 7 8 7 RES7 R2 15 x R1...

Page 441: ...D NEG PAD connected 3 POSPAD POS PAD connected 4 VSS VSS connected 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 4 NEGSEL 0x0 RW OPA2 inverting Input Mux These bits selects the source for the inverting input on OPA2 Value Mode Description 0 DISABLE Input disabled 1 UG Unity Gain feedback path 2 OPATAP OPA2 Resistor ladder as i...

Page 442: ... and differential to differential driver modes The opamps can also be configured as a one two or three step cascaded PGA and for all of the built in modes no external components are necessary 26 1 Introduction The opamps are highly configurable general purpose opamps suitable for simple filters and buffer applications The three opamps can be configured to support various operational amplifier func...

Page 443: ...ew OPA0 DAC OPA0 Alternative outputs OPA0 Main output OPA0NEXT OPA1 OPA1 Alternative outputs OPA1 Main output OPA1NEXT OPA2 OPA2 Main outputs ADC CH5 input mux POS0 NEG0 POS1 NEG1 POS2 NEG2 ADC CH0 input mux ADC CH1 input mux ADC CH0 input mux A more detailed view of the three opamps including the mux network is shown in Figure 26 2 p 444 There is a set of input muxes for each opamp making it poss...

Page 444: ..._OPACTRL 26 3 1 1 Input Configuration The inputs to the opamps are controlled through a set of input muxes The mux connected to the positive input is configured by the POSSEL bit field in the DACn_OPAxMUX register Similarly the mux connected to the negative input is configured by setting the NEGSEL bit field in DACn_OPAxMUX To connect the pins to the input muxes the pin switches must also be enabl...

Page 445: ...two main outputs can be connected to ADC input mux CH0 and ADC input mux CH5 respectively when enabled See Section 24 3 4 p 401 in the ADC chapter for information on how to configure the ADC input mux 26 3 1 3 Gain Programming The feedback path of each mux includes a resistor ladder which can be used to select a set of gain values The gain can be selected by the RESSEL bit field located in DACn_OP...

Page 446: ...ilable are described in the following sections 26 3 2 1 General Opamp Mode In this mode the resistor ladder is isolated from the feedback path and input signal routing is defined by OPAxPOSSEL and OPAxNEGSEL in DACn_OPAxMUX The output signal routing is defined by OUTPEN in DACn_OPAxMUX Table 26 1 General Opamp Mode Configuration OPA bit fields OPA Configuration OPAx POSSEL POSPADx OPAx NEGSEL OPAT...

Page 447: ...OS R1 R2 POS VIN Table 26 3 Inverting input PGA Configuration OPA bit fields OPA Configuration OPAx POSSEL POSPADx OPAx NEGSEL OPATAP OPAx RESINMUX NEXTOUT NEGPADx POSPADx 26 3 2 4 Non inverting PGA Figure 26 6 p 447 shows the non inverting input configuration In this mode the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit field to OPATAP in DACn_OPAxMUX This sett...

Page 448: ...gure 26 7 Cascaded Inverting PGA Overview R1 R2 VIN POS0 VOUT1 VIN POS0 x R2 R1 POS0 VOUT2 VOUT1 POS1 x R2 R1 POS1 VOUT3 VOUT2 POS3 x R2 R1 POS3 R1 R2 POS1 R1 R2 POS2 Table 26 5 Cascaded Inverting PGA Configuration OPA OPA bit fields OPA Configuration OPA0 POSSEL POSPAD0 OPA0 NEGSEL OPA0TAP OPA0 RESINMUX NEGPAD0 OPA0 NEXTOUT 1 OPA1 POSSEL POSPAD1 OPA1 NEGSEL OPATAP OPA1 RESINMUX OPA0INP OPA1 NEXTO...

Page 449: ...y input by configuring the OPA0POSSEL bit field in DACn_OPA0MUX The OPA0 feedback path must be configured to unity gain by setting the OPA0NEGSEL bit field to UG in DACn_OPA0MUX In addition the OPA0RESINMUX bit field must be set to DISABLED The OPA0OUT must be connected to OPA1 by setting NEXTOUT in DACn_OPA0MUX and OPA1RESINMUX to OPA0INP The positive input on OPA1 can be set by configuring OPA1P...

Page 450: ...elds OPA Configuration OPA1 POSSEL POSPAD1 OPA1 NEGSEL UG OPA1 RESINMUX DISABLE OPA1 NEXTOUT 1 OPA2 POSSEL POSPAD1 OPA2 NEGSEL OPATAP OPA2 RESINMUX OPA1INP 26 3 2 8 Three Opamp Differential Amplifier This mode enables the three opamps to be internally configured to form a three opamp differential amplifier as shown in Figure 26 10 p 451 Both OPA0 and OPA1 can be configured in the same unity gain m...

Page 451: ...erent gain values available 1 3 1 and 3 can be programmed as shown in the table below Table 26 9 Three Opamp Differential Amplifier Gain Programming Gain OPA0 RESSEL OPA2 RESSEL 1 3 4 0 1 1 1 3 0 4 Table 26 10 Three Opamp Differential Amplifier Configuration OPA OPA bit fields OPA Configuration OPA0 POSSEL POSPAD OPA0 NEGSEL UG OPA0 RESINMUX DISABLE OPA1 POSSEL POSPAD OPA1 NEGSEL UG OPA1 RESINMUX ...

Page 452: ...it is not possible to use both DAC channels and all three opamps at the same time If both DAC channels are used only OPA2 is available out of the 3 opamps However it is possible to use one of the DAC channels in combination with OPA0 OPA1 OPA1 is available when DAC channel 0 is in use and OPA0 is available when DAC channel 1 is used When using the opamp DAC combination the DAC CONVMODE can only be...

Page 453: ...ith 256 bit keys The AES module is an AHB slave which enables efficient access to the data and key registers All write accesses to the AES module must be 32 bit operations i e 8 or 16 bit operations are not supported 27 2 Features AES hardware encryption decryption 128 bit key 54 HFCORECLK cycles 256 bit key 75 HFCORECLK cycles Efficient CPU DMA support Interrupt on finished encryption decryption ...

Page 454: ...able byte ordering which is configured in BYTEORDER in AES_CTRL Figure 27 2 p 454 illustrates how data written to the AES registers is mapped to the key and state defined in the Advanced Encryption Standard FIPS 197 The figure presents the key byte order for 256 bit keys In 128 bit mode with BYTEORDER cleared a16 represents the first byte of the 128 bit key When BYTEORDER is set a0 represents the ...

Page 455: ...e the contents of the key registers will be turned into the CipherKey during the encryption The opposite applies when decrypting where you have to re supply the CipherKey between each block However in AES128 mode KEY4 KEY7 can be used as a buffer register to hold an extra copy of the KEY3 KEY0 registers When KEYBUFEN is set in AES_CTRL the contents of KEY7 KEY4 are copied to KEY3 KEY0 when an encr...

Page 456: ...erform Cipher Block Chaining with 128 bit keys Example 27 1 AES Cipher Block Chaining 1 Configure module to encryption key buffer enabled and XORSTART in AES_CTRL 2 Write 128 bit initialization vector to AES_DATA starting with least significant word 3 Write PlainKey to AES_KEYHn starting with least significant word 4 Write PlainText to AES_XORDATA starting with least significant word Encryption wi...

Page 457: ...ster 0x04C AES_KEYHD RW KEY High Register 27 5 Register Description 27 5 1 AES_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access RW RW RW RW RW RW Name BYTEORDER XORSTART DATASTART KEYBUFEN AES256 DECRYPT Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future de...

Page 458: ...Reset 0 0 Access W1 W1 Name STOP START Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 STOP 0 W1 Encryption Decryption Stop Set to stop encryption decryption 0 START 0 W1 Encryption Decryption Start Set to start encryption decryption 27 5 3 AES_STATUS Status Register Offset Bit Position 0x008 3...

Page 459: ...10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name DONE Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 DONE 0 R Encryption Decryption Done Interrupt Flag Set when an encryption decryption has finished 27 5 6 AES_IFS Interrupt Flag Set...

Page 460: ...formation in Section 2 1 p 3 0 DONE 0 W1 Encryption Decryption Done Interrupt Flag Clear Write to 1 to clear encryption decryption done interrupt flag 27 5 8 AES_DATA DATA Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name DATA Bit Name Reset Access Description 31 0 DATA 0x00000000 RW Data Access ...

Page 461: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYLA Bit Name Reset Access Description 31 0 KEYLA 0x00000000 RW Key Low Access A Access the low key words through this register 27 5 11 AES_KEYLB KEY Low Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name...

Page 462: ... Key Low Access C Access the low key words through this register 27 5 13 AES_KEYLD KEY Low Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYLD Bit Name Reset Access Description 31 0 KEYLD 0x00000000 RW Key Low Access D Access the low key words through this register 27 5 14 AES_KEYHA KEY High ...

Page 463: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYHB Bit Name Reset Access Description 31 0 KEYHB 0x00000000 RW Key High Access B Access the high key words through this register 27 5 16 AES_KEYHC KEY High Register Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name ...

Page 464: ...m 27 5 17 AES_KEYHD KEY High Register Offset Bit Position 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYHD Bit Name Reset Access Description 31 0 KEYHD 0x00000000 RW Key High Access D Access the high key words through this register ...

Page 465: ...nt locations thus solving congestion issues that may arise with multiple functions on the same pin Fully asynchronous interrupts can also be generated from any pin 28 1 Introduction In the EFM32TG devices the General Purpose Input Output GPIO pins are organized into ports with up to 16 pins each These pins can individually be configured as either an output or input More advanced configurations lik...

Page 466: ...al GPIO pin is called Pxn where x indicates the port A B C and n indicates the pin number 0 1 15 Fewer than 16 bits may be available on some ports depending on the total number of I O pins on the package After a reset both input and output is disabled for all pins on the device except for debug pins To use a pin the port GPIO_Px_MODEL GPIO_Px_MODEH registers must be configured for the pin to make ...

Page 467: ...rotection block against over voltage 28 3 1 Pin Configuration In addition to setting the pins as either outputs or inputs the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations GPIO_Px_MODEL contains 8 bit fields named MODEn n 0 1 7 which control pins 0 7 while GPIO_Px_MODEH contains 8 bit fields named MODEn n 8 9 15 which control pins 8 15 In some modes GPIO_Px...

Page 468: ...ngth pull up and filter MODEn determines which mode the pin is in at a given time Setting MODEn to 0b0000 disables the pin reducing power consumption to a minimum When the output driver is disabled the pin can be used as a connection for an analog module e g ADC LCD Input is enabled by setting MODEn to any value other than 0b0000 The pull up pull down and filter function can optionally be applied ...

Page 469: ...O_Px_CTRL In all other output modes the drive strength is set to STANDARD 28 3 1 1 Configuration Lock GPIO_Px_MODEL GPIO_Px_MODEH GPIO_Px_CTRL GPIO_Px_PINLOCKN GPIO_EXTIPSELL GPIO_EXTIPSELH GPIO_INSENSE and GPIO_ROUTE can be locked by writing any other value than 0xA534 to GPIO_LOCK Writing the value 0xA534 to the GPIOx_LOCK register unlocks the configuration registers In addition to configuration...

Page 470: ... EM4 wake up reset bits should be set It is possible to determine which pin caused the reset by reading the GPIO_EM4WUCAUSE register The mapping between pins and the bits in the GPIO_EM4WUEN GPIO_EM4WUPOL and GPIO_EM4WUCAUSE registers are described in Table 28 2 p 470 Table 28 2 EM4 WU Register bits to pin mapping Wake up Registers Bits Pin bit 0 A0 bit 1 A6 bit 2 C9 bit 3 F1 bit 4 F2 bit 5 E13 28...

Page 471: ...e as enabled If you do disable the debug pins make sure you have at least a 3 second timeout at the start of your program code before you disable the debug pins This way the debugger will have time to halt the device after a reset before the pins are disabled The Serial Wire Viewer Output pin SWO can be enabled by setting the SWOPEN bit in GPIO_ROUTE This bit can also be routed to alternate locati...

Page 472: ...t on which the output n should be taken is selected by the EXTIPSELn 3 0 bits in the GPIO_EXTIPSELL or the GPIO_EXTIPSELH registers 28 3 7 Synchronization To avoid metastability in synchronous logic connected to the pins all inputs are synchronized with double flip flops The flip flops for the input data run on the HFCORECLK Consequently when a pin changes state the change will have propagated to ...

Page 473: ...Data Out Toggle Register 0x040 GPIO_PB_DIN R Port Data In Register 0x044 GPIO_PB_PINLOCKN RW Port Unlocked Pins Register 0x048 GPIO_PC_CTRL RW Port Control Register 0x04C GPIO_PC_MODEL RW Port Pin Mode Low Register 0x050 GPIO_PC_MODEH RW Port Pin Mode High Register 0x054 GPIO_PC_DOUT RW Port Data Out Register 0x058 GPIO_PC_DOUTSET W1 Port Data Out Set Register 0x05C GPIO_PC_DOUTCLR W1 Port Data Ou...

Page 474: ...ster 0x100 GPIO_EXTIPSELL RW External Interrupt Port Select Low Register 0x104 GPIO_EXTIPSELH RW External Interrupt Port Select High Register 0x108 GPIO_EXTIRISE RW External Interrupt Rising Edge Trigger Register 0x10C GPIO_EXTIFALL RW External Interrupt Falling Edge Trigger Register 0x110 GPIO_IEN RW Interrupt Enable Register 0x114 GPIO_IF R Interrupt Flag Register 0x118 GPIO_IFS W1 Interrupt Fla...

Page 475: ...ration is equal to MODE0 23 20 MODE5 0x0 RW Pin 5 Mode Configure mode for pin 5 Enumeration is equal to MODE0 19 16 MODE4 0x0 RW Pin 4 Mode Configure mode for pin 4 Enumeration is equal to MODE0 15 12 MODE3 0x0 RW Pin 3 Mode Configure mode for pin 3 Enumeration is equal to MODE0 11 8 MODE2 0x0 RW Pin 2 Mode Configure mode for pin 2 Enumeration is equal to MODE0 7 4 MODE1 0x0 RW Pin 1 Mode Configur...

Page 476: ...umeration is equal to MODE8 15 12 MODE11 0x0 RW Pin 11 Mode Configure mode for pin 11 Enumeration is equal to MODE8 11 8 MODE10 0x0 RW Pin 10 Mode Configure mode for pin 10 Enumeration is equal to MODE8 7 4 MODE9 0x0 RW Pin 9 Mode Configure mode for pin 9 Enumeration is equal to MODE8 3 0 MODE8 0x0 RW Pin 8 Mode Configure mode for pin 8 Value Mode Description 0 DISABLED Input disabled Pullup if DO...

Page 477: ...ut on port 28 5 5 GPIO_Px_DOUTSET Port Data Out Set Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name DOUTSET Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DOUTSET 0x0000 W1 Data Out Set Wri...

Page 478: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name DOUTTGL Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DOUTTGL 0x0000 W1 Data Out Toggle Write bits to 1 to toggle corresponding bits in GPIO_Px_DOUT Bits written to 0 will have no effect 28 5 8 GPIO_Px_DIN Port Data In Register O...

Page 479: ...ess Description 31 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 EXTIPSEL7 0x0 RW External Interrupt 7 Port Select Select input port for external interrupt 7 Value Mode Description 0 PORTA Port A pin 7 selected for external interrupt 7 1 PORTB Port B pin 7 selected for external interrupt 7 2 PORTC Port C pin 7 selected for ext...

Page 480: ...More information in Section 2 1 p 3 14 12 EXTIPSEL3 0x0 RW External Interrupt 3 Port Select Select input port for external interrupt 3 Value Mode Description 0 PORTA Port A pin 3 selected for external interrupt 3 1 PORTB Port B pin 3 selected for external interrupt 3 2 PORTC Port C pin 3 selected for external interrupt 3 3 PORTD Port D pin 3 selected for external interrupt 3 4 PORTE Port E pin 3 s...

Page 481: ...ved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 EXTIPSEL15 0x0 RW External Interrupt 15 Port Select Select input port for external interrupt 15 Value Mode Description 0 PORTA Port A pin 15 selected for external interrupt 15 1 PORTB Port B pin 15 selected for external interrupt 15 2 PORTC Port C pin 15 selected for external interrupt ...

Page 482: ...PORTB Port B pin 11 selected for external interrupt 11 2 PORTC Port C pin 11 selected for external interrupt 11 3 PORTD Port D pin 11 selected for external interrupt 11 4 PORTE Port E pin 11 selected for external interrupt 11 5 PORTF Port F pin 11 selected for external interrupt 11 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10...

Page 483: ...1 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name EXTIRISE Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 EXTIRISE 0x0000 RW External Interrupt n Rising Edge Trigger Enable Set bit n to enable triggering of external interrupt n on rising edge Value Description EXTIRISE n 0 Rising edge t...

Page 484: ...re compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 EXT 0x0000 RW External Interrupt n Enable Set bit n to enable external interrupt from pin n Value Description EXT n 0 Pin n external interrupt disabled EXT n 1 Pin n external interrupt enabled 28 5 15 GPIO_IF Interrupt Flag Register Offset Bit Position 0x114 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 485: ... 0 EXT 0x0000 W1 External Interrupt Flag n Set Write bit n to 1 to set interrupt flag n Value Description EXT n 0 Pin n external interrupt flag unchanged EXT n 1 Pin n external interrupt flag set 28 5 17 GPIO_IFC Interrupt Flag Clear Register Offset Bit Position 0x11C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name EXT Bit Name Rese...

Page 486: ...the pin back to a default state as enabled If you disable this pin make sure you have at least a 3 second timeout at the start of you program code before you disable the pin This way the debugger will have time to halt the device after a reset before the pin is disabled 0 SWCLKPEN 1 RW Serial Wire Clock Pin Enable Enable Serial Wire Clock connection to pin WARNING When this pin is disabled the dev...

Page 487: ...N EPISELL EIPSELH INSENSE and SWDPROUTE from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 GPIO registers are unlocked LOCKED 1 GPIO registers are locked Write Operation LOCK 0 Lock GPIO registers UNLOCK 0xA534 Unlock GPIO registers 28 5 21 GPIO_CTRL GPIO Control Register Offset Bit Position ...

Page 488: ... 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name EM4WUEN Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 0 EM4WUEN 0x00 RW EM4 Wake up enable Write 1 to enable wake up request write 0 to disable wake up request Value Mode Description 0x01 A0 E...

Page 489: ...USE EM4 Wake up Cause Register Offset Bit Position 0x13C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name EM4WUCAUSE Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 0 EM4WUCAUSE 0x00 R EM4 wake up cause Bit n indicates which pin the ...

Page 490: ...optimal choice for battery driven systems with LCD panels 29 1 Introduction The LCD driver is capable of driving a segmented LCD display combination of 1x24 2x24 3x24 4x24 6x22 or 8x20 segments A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device In addition an animation feature can run custom animations on the LCD display withou...

Page 491: ...d or disabled individually to prevent the LCD driver from occupying more I O resources than required Figure 29 1 LCD Block Diagram LCD voltage generator VINT VEXT VBOOST VLC1 VLC0 VLC1 VLC0 Disable SEG out Disable COM out LCD_SEGx LCD_COMx VLCDSEL LCD control and status LCD segment data register LCD animation registers LCD sequence generator Contrast and bias setting Mux and framerate setting Disp...

Page 492: ...OM5 are used making 22 segments available located in SEG0 SEG19 and SEG22 SEG23 Finally when octaplex multiplexing is selected LCD_COM0 LCD_COM3 together with SEG20 SEG23 as LCD_COM4 LCD_COM7 are used making the 36 segments available located in SEG0 SEG19 and SEG24 SEG39 See Section 29 3 3 p 493 for waveforms for the different bias and multiplexing settings The waveforms generated by the LCD contr...

Page 493: ... 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End 29 3 3 Waveform Examples The numbers on the illustration s y axes in the following sections only indicate different voltage levels All examples are shown with low power waveforms 29 3 3 1 Waveforms with Static Bias and Multiplexing With static bias and multiplexing each segment line can be connected to LCD_COM0 When the segment line has the same w...

Page 494: ...e 29 6 LCD 1 2 Bias and Duplex Multiplexing LCD_COM1 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End 1 2 bias and duplex multiplexing LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the LCD_COM lines in order to turn on and off LCD pixels As illustrated in the figures below this waveform will turn ON pixels c...

Page 495: ...lexing LCD_SEG0 LCD_COM1 DC voltage 0 over one frame VRMS 0 35 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform Figure 29 10 LCD 1 2 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM1 VLC0 VLCD VLC3 VSS VLC0 VLCD Frame Start Frame End VLC1 1 2VLCD VLC1 1 2VLCD 29 3 3 3 Waveforms with 1 3 Bias and Duplex Multiplexing In this mode each frame is div...

Page 496: ...h the COM lines in order to turn on and off LCD pixels As illustrated in the figures below this waveform will turn ON pixels connected to LCD_COM0 while pixels connected to LCD_COM1 will be turned OFF Figure 29 13 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 VLC0 VLCD VLC3 VSS Frame Start Frame End VLC1 2 3VLCD VLC2 1 3VLCD Figure 29 14 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 Connection com...

Page 497: ... with this waveform Figure 29 16 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM1 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 29 3 3 4 Waveforms with 1 2 Bias and Triplex Multiplexing In this mode each frame is divided into 6 periods LCD_COM 2 0 lines can be multiplexed with all segment lines Figures show 1 2 bias and triplex multipl...

Page 498: ...s below this waveform will turn ON pixels connected to LCD_COM1 while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF Figure 29 20 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End Figure 29 21 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 Connection com1 com2 com0 seg0 1 2 bias and triplex multiplexing LCD_SEG0 LCD_COM0 DC voltage 0...

Page 499: ...lexing LCD_SEG0 LCD_COM2 DC voltage 0 over one frame VRMS 0 4 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 29 24 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM2 VLC0 VLCD VLC3 VSS VLC0 VLCD VLC1 1 2VLCD VLC1 1 2VLCD Frame Start Frame End 29 3 3 5 Waveforms with 1 3 Bias and Triplex Multiplexing In this mode each frame is di...

Page 500: ...ment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels As illustrated in the figures below this waveform will turn ON pixels connected to LCD_COM1 while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF Figure 29 28 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 VLC0 VLCD VLC3 VSS VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End Figure 29 29 LCD 1 3 B...

Page 501: ... LCD_SEG0 LCD_COM1 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and triplex multiplexing LCD_SEG0 LCD_COM2 DC voltage 0 over one frame VRMS 0 33 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 29 32 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM2 VLC3 VSS VLC0 ...

Page 502: ... Multiplexing LCD_COM2 VLC0 VLCD VLC1 2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End Figure 29 36 LCD 1 3 Bias and Quadruplex Multiplexing LCD_COM3 VLC0 VLCD VLC1 2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lin...

Page 503: ...quadruplex multiplexing LCD_SEG0 LCD_COM0 DC voltage 0 over one frame VRMS 0 58 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform Figure 29 39 LCD 1 3 Bias and Quadruplex Multiplexing LCD_SEG0 LCD_COM0 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD_...

Page 504: ...ultiplexing LCD_SEG0 LCD_COM2 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD_SEG0 LCD_COM2 DC voltage 0 over one frame VRMS 0 33 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM3 will be OFF with this waveform Figure 29 42 LCD 1 3 Bias and Quadruplex Multiplexing LCD_SEG0 LCD_CO...

Page 505: ...Range 00 00000 11111 VLCD_OUT VLCD x 0 61 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 61VLCD CONLEV 31 VLCD_OUT VLCD 01 00000 11111 VLCD_OUT VLCD x 0 53 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 53VLCD CONLEV 31 VLCD_OUT VLCD 10 00000 11111 VLCD_OUT VLCD x 0 61 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 61VLCD CONLEV 31 VLCD_OUT VLCD 11 00000 11111 VLCD_OUT VLCD x 0 61 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 61VLCD CO...

Page 506: ... Rx VLCD_OUT VLCD R3 VLC4 VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD Rx VLCD_OUT R3 VLC4 VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD VLCD_OUT R3 VLC4 1 3 bias VLC0 VLC1 VLC2 VLC3 R0 R1 R2 Rx VLCD_OUT VLCD VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD Rx VLCD_OUT VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD VLCD_OUT 1 2 bias VLC0 VLC1 VLC3 VLCD R0 R1 Rx VLCD_OUT VLC0 VLC1 VLC3 VLCD R0 R1 Rx VLCD_OUT VLC0 VLC1 VLC3 VLCD R0 R1 VLCD_OUT Stati...

Page 507: ...e booster should be disabled Table 29 7 LCD VLCD VLCDSEL Mode VLCD 0 VDD VDD same as main external power 1 VBOOST Voltage booster External VDD 29 3 6 VBOOST Control The boost voltage is configurable By programming the VBLEV bits in LCD_DISPCTRL the boost voltage level can be adjusted between 3 0V and 3 6V The boost circuit will use an update frequency given by the VBFDIV bits in CMU_LCDCTRL see Ta...

Page 508: ...ax Min Max Min Max Static LFACLKLCD 2 128 1024 64 512 32 256 16 128 Duplex LFACLKLCD 4 64 512 32 256 16 128 8 64 Triplex LFACLKLCD 6 43 341 21 171 11 85 5 43 Quadruplex LFACLKLCD 8 32 256 16 128 8 64 4 32 Sextaplex LFACLKLCD 12 21 33 170 67 10 67 85 33 5 33 42 67 2 67 21 33 Octaplex LFACLKLCD 16 16 128 8 64 4 32 2 16 Table settings Min FDIV 7 Max FDIV 0 29 3 8 Data Update The LCD Driver logic that...

Page 509: ...s bias levels can be set in SEGD0 SEGD3 while the COM line bias levels can be set in SEGD4 To represent the different bias levels 2 bits per SEG lines are needed For example SEG0 s bias levels can be set using SEGD0 1 0 and SEG1 can be controlled through SEGD0 3 2 etc Bias level encoding is shown in Table 29 11 p 509 Table 29 11 DSC BIAS Encoding SEGD Mode Bias setting 00 Static Static 2 levels 01...

Page 510: ...Hz and the LCD event frequency should be set up to 2 seconds Example 29 1 LCD Event Frequency Example Write FCPRESC to 3 CLKFC 8Hz 0 125 seconds Write FCTOP to 15 CLKEVENT 0 5Hz 2 seconds If higher resolution is required configure a lower prescaler value and increase the FCPRESC in LCD_BACTRL accordingly e g FCPRESC 2 FCTOP 31 Figure 29 43 LCD Clock System in LCD Driver LFXO LFRCO Counter FDIV 2 0...

Page 511: ...nd AREGBSC in LCD_BACTRL as shown in the table below Note also that the FC must be on for animation to work as it is the FC event that drives the animation state machine Table 29 13 LCD Animation Shift Register AREGnSC n A or B Mode Description 00 NOSHIFT No Shift operation 01 SHIFTLEFT Animation register is shifted left LCD_AREGA is shifted every odd state LCD_AREGB is shifted every even state 10...

Page 512: ...011100 8 00001100 00001100 00001100 9 00000110 00001100 00001110 10 00000110 00000110 00000110 11 00000011 00000110 00000111 12 00000011 00000011 00000011 13 10000001 00000011 10000011 14 10000001 10000001 10000001 15 11000000 10000001 11000001 In the table AREGASC 10 AREGBSC 10 ALOGSEL 1 and the resulting data is to be displayed on segment lines 7 0 multiplexed with LCD_COM0 Figure 29 44 LCD Bloc...

Page 513: ...ion State machine changes state In the interrupt handler read back the current state ASTATE Knowing the current state of the Animation State Machine makes it possible to calculate what data that is currently output Modify data as required Data will be updated at the next Frame Counter Event It is important that new data is written before the next Frame Counter Event 29 3 13 LCD in Low Energy Modes...

Page 514: ...w Register 1 0x048 LCD_SEGD2L RW Segment Data Low Register 2 0x04C LCD_SEGD3L RW Segment Data Low Register 3 0x060 LCD_FREEZE RW Freeze Register 0x064 LCD_SYNCBUSY R Synchronization Busy Register 0x0CC LCD_SEGD4L RW Segment Data Low Register 4 0x0D0 LCD_SEGD5L RW Segment Data Low Register 5 0x0D4 LCD_SEGD6L RW Segment Data Low Register 6 0x0D8 LCD_SEGD7L RW Segment Data Low Register 7 29 5 Registe...

Page 515: ... 6 5 4 3 2 1 0 Reset 0 0x3 0 0 0x1F 0 0x0 0x0 Access RW RW RW RW RW RW RW RW Name MUXE VBLEV VLCDSEL CONCONF CONLEV WAVE BIAS MUX Bit Name Reset Access Description 31 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 MUXE 0 RW Extended Mux Configuration This bit redefines the meaning of the MUX field Value Mode Description 0 MUX M...

Page 516: ...ion 2 1 p 3 4 WAVE 0 RW Waveform Selection This bit configures the output waveform Value Mode Description 0 LOWPOWER Low power waveform 1 NORMAL Normal waveform 3 2 BIAS 0x0 RW Bias Configuration These bits set the bias mode for the LCD Driver Value Mode Description 0 STATIC Static 1 ONEHALF 1 2 Bias 2 ONETHIRD 1 3 Bias 3 ONEFOURTH 1 4 Bias 1 0 MUX 0x0 RW Mux Configuration These bits set the multi...

Page 517: ...Section 2 1 p 3 23 18 FCTOP 0x00 RW Frame Counter Top Value These bits contain the Top Value for the Frame Counter CLKEVENT CLKFC 1 FCTOP 5 0 17 16 FCPRESC 0x0 RW Frame Counter Prescaler These bits controls the prescaling value for the Frame Counter input clock Value Mode Description 0 DIV1 CLKFC CLKFRAME 1 1 DIV2 CLKFC CLKFRAME 2 2 DIV4 CLKFC CLKFRAME 4 3 DIV8 CLKFC CLKFRAME 8 15 9 Reserved To en...

Page 518: ...LCD_STATUS Status Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 Access R R Name BLINK ASTATE Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 BLINK 0 R Blink State This bits indicates the blink status If this ...

Page 519: ...REGB Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 AREGB 0x00 RW Animation Register B Data This register contains the B data for generating animation pattern 29 5 8 LCD_IF Interrupt Flag Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 520: ...31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 FC 0 W1 Frame Counter Interrupt Flag Clear Write to 1 to clear FC interrupt flag 29 5 11 LCD_IEN Interrupt Enable Register Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name FC Bit Name Reset Acces...

Page 521: ...nt lines 0 23 for COM0 29 5 13 LCD_SEGD1L Segment Data Low Register 1 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000000 Access RW Name SEGD1L Bit Name Reset Access Description 31 24 Reserved To ensure compatibility with future devices ...

Page 522: ...29 5 15 LCD_SEGD3L Segment Data Low Register 3 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000000 Access RW Name SEGD3L Bit Name Reset Access Description 31 24 Reserved To ensure compatibility with future devices always write bits to 0 ...

Page 523: ...formation in Section 2 1 p 3 19 SEGD7L 0 R SEGD7L Register Busy Set when the value written to SEGD7L is being synchronized 18 SEGD6L 0 R SEGD6L Register Busy Set when the value written to SEGD6L is being synchronized 17 SEGD5L 0 R SEGD5L Register Busy Set when the value written to SEGD5L is being synchronized 16 SEGD4L 0 R SEGD4L Register Busy Set when the value written to SEGD4L is being synchron...

Page 524: ... RW COM4 Segment Data This register contains segment data for segment lines 0 23 for COM4 29 5 19 LCD_SEGD5L Segment Data Low Register 5 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x0D0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000000 Access RW Name SEGD5L Bit Name Reset Access Desc...

Page 525: ... RW COM6 Segment Data This register contains segment data for segment lines 0 23 for COM6 29 5 21 LCD_SEGD7L Segment Data Low Register 7 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x0D8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000000 Access RW Name SEGD7L Bit Name Reset Access Desc...

Page 526: ...tion number for LEAURT and I2C Updated CMU LFA LFAE and LFB LFBE CLKSEL description Updated info page size for Flash memory Updated DI page table with family part number and corrected the address of AUXHFRCO calibration value Updated package types Updated LETIMER Async Support in Reflex Producers table Updated the I2C Clock Mode table and added the Maximum Data Hold Time formula Added the minimum ...

Page 527: ... Changed formula in VDDLEVEL bitfield in ACMPn_INPUTSEL Added sine wave minimum amplitude to BUFEXTCLK Changed description of IRQERASEABORT Updated description of WARMUPMODE in ADC section Added documentation for DMA_CHREQSTATUS DMA_CHSREQSTATUS Renamed DMA_WAITSTATUS to DMA_CHWAITSTATUS and updated bit fields Updated general description of bus system Updated frequency limitations when clocking TI...

Page 528: ...ontrollers 2014 07 02 Tiny Gecko Family d0034_Rev1 20 528 www silabs com Updated EM0 EM4 current consumption 30 4 Revision 0 90 December 21th 2010 Major updates to all chapters 30 5 Revision 0 80 October 1st 2010 Initial preliminary revision ...

Page 529: ... High Frequency RC Oscillator CC Compare Capture CLK Clock CMD Command CMU Clock Management Unit CTRL Control DAC Digital to Analog Converter DBG Debug DMA Direct Memory Access DRD Dual Role Device EFM Energy Friendly Microcontroller EM Energy Mode EM0 Energy Mode 0 also called active mode EM1 to EM4 Energy Mode 1 to Energy Mode 4 also called low energy modes EMU Energy Management Unit ENOB Effect...

Page 530: ...ing Ratio OTG On the go PCNT Pulse Counter PGA Programmable Gain Array PHY Physical Layer PRS Peripheral Reflex System PSRR Power Supply Rejection Ratio PWM Pulse Width Modulation RC Resistance and Capacitance RMU Reset Management Unit RTC Real Time Clock SAR Successive Approximation Register SOF Start of Frame SPI Serial Peripheral Interface SW Software THD Total Harmonic Distortion USART Univers...

Page 531: ... to design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are gene...

Page 532: ...34_Rev1 20 532 www silabs com C Contact Information Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 Please visit the Silicon Labs Technical Support web page http www silabs com support pages contacttechnicalsupport aspx and register to submit a technical support request ...

Page 533: ...ase 26 6 5 Register Map 28 6 6 Register Description 28 7 MSC Memory System Controller 30 7 1 Introduction 30 7 2 Features 31 7 3 Functional Description 31 7 4 Register Map 37 7 5 Register Description 37 8 DMA DMA Controller 46 8 1 Introduction 46 8 2 Features 46 8 3 Block Diagram 47 8 4 Functional Description 48 8 5 Examples 65 8 6 Register Map 67 8 7 Register Description 68 9 RMU Reset Management...

Page 534: ...ction 285 18 2 Features 285 18 3 Functional Description 286 18 4 Register Map 289 18 5 Register Description 289 19 LETIMER Low Energy Timer 294 19 1 Introduction 294 19 2 Features 294 19 3 Functional Description 295 19 4 Register Map 308 19 5 Register Description 308 20 PCNT Pulse Counter 317 20 1 Introduction 317 20 2 Features 317 20 3 Functional Description 317 20 4 Register Map 323 20 5 Registe...

Page 535: ...Map 457 27 5 Register Description 457 28 GPIO General Purpose Input Output 465 28 1 Introduction 465 28 2 Features 465 28 3 Functional Description 466 28 4 Register Map 473 28 5 Register Description 474 29 LCD Liquid Crystal Display Driver 490 29 1 Introduction 490 29 2 Features 490 29 3 Functional Description 491 29 4 Register Map 514 29 5 Register Description 514 30 Revision History 526 30 1 Rev...

Page 536: ...nversions through PRS channel 5 139 14 1 I 2 C Overview 146 14 2 I 2 C Bus Example 146 14 3 I 2 C START and STOP Conditions 147 14 4 I 2 C Bit Transfer on I 2 C Bus 147 14 5 I 2 C Single Byte Write to Slave 148 14 6 I 2 C Double Byte Read from Slave 148 14 7 I 2 C Single Byte Write then Repeated Start and Single Byte Read 148 14 8 I 2 C Master Transmitter Slave Receiver with 10 bit Address 149 14 ...

Page 537: ...0 19 6 LETIMER Simple Waveforms Output 302 19 7 LETIMER Repeated Counting 302 19 8 LETIMER Dual Output 303 19 9 LETIMER Triggered Operation 304 19 10 LETIMER Continuous Operation 305 19 11 LETIMER LETIMERn_CNT Not Initialized to 0 306 20 1 PCNT Overview 318 20 2 PCNT Quadrature Coding 319 20 3 PCNT Direction Change Interrupt DIRCNG Generation 322 21 1 LESENSE block diagram 333 21 2 Scan sequence 3...

Page 538: ...LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM1 497 29 17 LCD 1 2 Bias and Triplex Multiplexing LCD_COM0 497 29 18 LCD 1 2 Bias and Triplex Multiplexing LCD_COM1 497 29 19 LCD 1 2 Bias and Triplex Multiplexing LCD_COM2 498 29 20 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 498 29 21 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 Connection 498 29 22 LCD 1 2 Bias and Triplex Multiplexing L...

Page 539: ...esses 148 14 2 I 2 C High and Low Periods for Low CLKDIV 150 14 3 I 2 C Clock Mode 151 14 4 I 2 C Interactions in Prioritized Order 154 14 5 I 2 C Master Transmitter 156 14 6 I 2 C Master Receiver 158 14 7 I 2 C STATE Values 159 14 8 I 2 C Transmission Status 159 14 9 I 2 C Slave Transmitter 162 14 10 I 2 C Slave Receiver 163 14 11 I 2 C Bus Error Response 164 15 1 USART Asynchronous vs Synchronou...

Page 540: ... Opamp Differential Amplifier Configuration 451 26 11 Dual Buffer ADC Driver Configuration 452 28 1 Pin Configuration 467 28 2 EM4 WU Register bits to pin mapping 470 29 1 LCD Mux Settings 492 29 2 LCD BIAS Settings 492 29 3 LCD Wave Settings 493 29 4 LCD Contrast 505 29 5 LCD Contrast Function 505 29 6 LCD Principle of Contrast Adjustment for Different Bias Settings 506 29 7 LCD VLCD 507 29 8 LCD...

Page 541: ...Multi processor Mode Example 193 19 1 LETIMER Triggered Output Generation 304 19 2 LETIMER Continuous Output Generation 305 19 3 LETIMER PWM Output 306 19 4 LETIMER PWM Output 306 27 1 AES Cipher Block Chaining 456 28 1 GPIO Interrupt Example 472 29 1 LCD Event Frequency Example 510 29 2 LCD Animation Enable Example 513 29 3 LCD Animation Dependence Example 513 ...

Page 542: ... PWM Resolution Equation 262 17 4 TIMER Up count PWM Frequency Equation 262 17 5 TIMER Up count Duty Cycle Equation 263 17 6 TIMER 2x PWM Resolution Equation 263 17 7 TIMER 2x Mode PWM Frequency Equation Up count 263 17 8 TIMER 2x Mode Duty Cycle Equation 263 17 9 TIMER Up Down count PWM Resolution Equation 264 17 10 TIMER Up Down count PWM Frequency Equation 264 17 11 TIMER Up Down count Duty Cyc...

Page 543: ......

Reviews:

No comments

Related manuals for EFM32TG

Y-Solar Smart-MPPT Li Series User Manual preview
Smart-MPPT Li Series
Brand: Y-Solar Pages: 6
Abicor Binzel EWR Quick Install Instructions preview
EWR
Brand: Abicor Binzel Pages: 8
DayTronic 3700 Series Instruction Manual preview
3700 Series
Brand: DayTronic Pages: 22
OES ISC-9000 Operational Instructions preview
ISC-9000
Brand: OES Pages: 3
National Instruments NI 9514 User Manual preview
NI 9514
Brand: National Instruments Pages: 72
Festo CPS-Gate Operating Instructions Manual preview
CPS-Gate
Brand: Festo Pages: 109
Topworx Valvetop DXP Installation, Operation & Maintenance Manual preview
Valvetop DXP
Brand: Topworx Pages: 8
Vimar by-me Eikon 20526 Quick Start Manual preview
by-me Eikon 20526
Brand: Vimar Pages: 6
Powtran PR5200 011G3 User Manual preview
PR5200 011G3
Brand: Powtran Pages: 40
DAPAudio IPS-VC3 User Manual preview
IPS-VC3
Brand: DAPAudio Pages: 11
Akytec SMI200 User Manual preview
SMI200
Brand: Akytec Pages: 15
VALPES ER PLUS Installation Manual preview
ER PLUS
Brand: VALPES Pages: 28
KORINS EPIP-40 /30A(I) Instruction Manual preview
EPIP-40 /30A(I)
Brand: KORINS Pages: 3
Citadele Digipass 320 Operation Instructions Manual preview
Digipass 320
Brand: Citadele Pages: 6
Grifco C10A Installation And User Manual preview
C10A
Brand: Grifco Pages: 20
YASKAWA SI-T/ V7 Technical Manual preview
SI-T/ V7
Brand: YASKAWA Pages: 157
Translux Fair-Play MP-50 Series Quick Reference preview
Fair-Play MP-50 Series
Brand: Translux Pages: 20
Eaton Smart Home Controller 2.0 Quick Installation Manual preview
Smart Home Controller 2.0
Brand: Eaton Pages: 24

Brands by name

Popular brands

Load more brands