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Silicon Laboratories EFM8 Series, Reference Manual

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17.3  Functional Description

17.3.1  Signals

The SPI interface consists of up to four signals: MOSI, MISO, SCK, and NSS.

Master Out, Slave In (MOSI):

 The MOSI signal is the data output pin when configured as a master device and the data input pin when

configured as a slave. It is used to serially transfer data from the master to the slave. Data is transferred on the MOSI pin most-signifi-
cant bit first. When configured as a master, MOSI is driven from the internal shift register in both 3- and 4-wire mode.

Master In, Slave Out (MISO):

 The MISO signal is the data input pin when configured as a master device and the data output pin when

configured as a slave. It is used to serially transfer data from the slave to the master. Data is transferred on the MISO pin most-signifi-
cant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled or when the SPI operates in 4-wire
mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven from the internal shift register.

Serial Clock (SCK):

 The SCK signal is an output from the master device and an input to slave devices. It is used to synchronize the

transfer of data between the master and slave on the MOSI and MISO lines. The SPI module generates this signal when operating as a
master and receives it as a slave. The SCK signal is ignored by a SPI slave when the slave is not selected in 4-wire slave mode.

Slave Select (NSS):

 The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD bitfield. There are three

possible modes that can be selected with these bits:

• NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: The SPI operates in 3-wire mode, and NSS is disabled. When operating as

a slave device, the SPI is always selected in 3-wire mode. Since no select signal is present, the SPI must be the only slave on the
bus in 3-wire mode. This is intended for point-to-point communication between a master and a single slave.

• NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: The SPI operates in 4-wire mode, and NSS is configured as an input. When

operating as a slave, NSS selects the SPI device. When operating as a master, a 1-to- 0 transition of the NSS signal disables the
master function of the SPI module so that multiple master devices can be used on the same SPI bus.

• NSSMD[1:0]  =  1x:  4-Wire  Master  Mode:  The  SPI  operates  in  4-wire  mode,  and  NSS  is  enabled  as  an  output.  The  setting  of

NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating the SPI as a
master device.

The setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be map-
ped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device.

Slave Device

Master Device

MISO

MOSI

SCK

MISO

MOSI

SCK

NSS

NSS

Figure 17.2.  4-Wire Connection Diagram

Slave Device

Master Device

MISO

MOSI

SCK

MISO

MOSI

SCK

Figure 17.3.  3-Wire Connection Diagram

EFM8UB3 Reference Manual

Serial Peripheral Interface (SPI0)

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Summary of Contents for EFM8 Series

Page 1: ...og comparators with internal voltage DAC as reference input Six 16 bit timers UART and SMBus master slave Priority crossbar for flexible pin mapping USB I O controls Docking stations USB hubs Dongles Consumer electronics USB Type C converters USB Type C billboard alternate mode Security I O Ports Core Memory Clock Management CIP 51 8051 Core 48 MHz High Frequency 48 MHz RC Oscillator Energy Manage...

Page 2: ...al Function Registers 28 3 1 Special Function Register Access 28 3 2 Special Function Register Memory Map 30 3 3 SFR Access Control Registers 37 3 3 1 SFRPAGE SFR Page 37 3 3 2 SFRPGCN SFR Page Control 38 3 3 3 SFRSTACK SFR Page Stack 38 4 Flash Memory 39 4 1 Introduction 39 4 2 Features 39 4 3 Functional Description 40 4 3 1 Security Options 40 4 3 2 Programming the Flash Memory 41 4 3 3 Flash Wr...

Page 3: ...Priority 1 High 58 6 3 7 EIE2 Extended Interrupt Enable 2 59 6 3 8 EIP2 Extended Interrupt Priority 2 60 6 3 9 EIP2H Extended Interrupt Priority 2 High 61 7 Power Management and Internal Regulators 62 7 1 Introduction 62 7 2 Features 63 7 3 Idle Mode 64 7 4 Stop Mode 64 7 5 Suspend Mode 64 7 6 Snooze Mode 65 7 7 Shutdown Mode 65 7 8 5V to 3 3V Regulator 65 7 9 Power Management Control Registers 66...

Page 4: ... 9 3 6 Comparator CMP0 Reset 81 9 3 7 Watchdog Timer Reset 81 9 3 8 Flash Error Reset 81 9 3 9 Software Reset 81 9 3 10 USB Reset 81 9 4 Reset Sources and Supply Monitor Control Registers 82 9 4 1 RSTSRC Reset Source 82 9 4 2 VDM0CN Supply Monitor Control 83 10 CIP 51 Microcontroller Core 84 10 1 Introduction 84 10 2 Features 85 10 3 Functional Description 85 10 3 1 Programming and Debugging Suppo...

Page 5: ...1 Match 113 11 4 13 P1 Port 1 Pin Latch 114 11 4 14 P1MDIN Port 1 Input Mode 115 11 4 15 P1MDOUT Port 1 Output Mode 116 11 4 16 P1SKIP Port 1 Skip 117 11 4 17 P2MASK Port 2 Mask 118 11 4 18 P2MAT Port 2 Match 118 11 4 19 P2 Port 2 Pin Latch 119 11 4 20 P2MDIN Port 2 Input Mode 119 11 4 21 P2MDOUT Port 2 Output Mode 120 11 5 INT0 and INT1 Control Registers 121 11 5 1 IT01CF INT0 INT1 Configuration ...

Page 6: ...147 13 2 Features 147 13 3 Functional Description 148 13 3 1 Response Time and Supply Current 148 13 3 2 Hysteresis 148 13 3 3 Input Selection 148 13 3 4 Output Routing 153 13 4 CMP0 Control Registers 155 13 4 1 CMP0CN0 Comparator 0 Control 0 155 13 4 2 CMP0MD Comparator 0 Mode 157 13 4 3 CMP0MX Comparator 0 Multiplexer Selection 158 13 4 4 CMP0CN1 Comparator 0 Control 1 159 13 5 CMP1 Control Regi...

Page 7: ...gurable Logic Unit 3 Configuration 181 15 Cyclic Redundancy Check CRC0 182 15 1 Introduction 182 15 2 Features 182 15 3 Functional Description 183 15 3 1 16 bit CRC Algorithm 183 15 3 2 Using the CRC on a Data Stream 184 15 3 3 Using the CRC to Check Code Memory 184 15 3 4 Bit Reversal 184 15 4 CRC0 Control Registers 185 15 4 1 CRC0CN0 CRC0 Control 0 185 15 4 2 CRC0IN CRC0 Data Input 185 15 4 3 CR...

Page 8: ... 17 PCA0CPH2 PCA Channel 2 Capture Module High Byte 212 17 Serial Peripheral Interface SPI0 213 17 1 Introduction 213 17 2 Features 213 17 3 Functional Description 214 17 3 1 Signals 214 17 3 2 Master Mode Operation 215 17 3 3 Slave Mode Operation 216 17 3 4 Clock Phase and Polarity 217 17 3 5 Basic Data Transfer 218 17 3 6 Using the SPI FIFOs 218 17 3 7 SPI Timing Diagrams 221 17 4 SPI0 Control R...

Page 9: ... 0 1 Control 271 19 4 4 TMOD Timer 0 1 Mode 272 19 4 5 TL0 Timer 0 Low Byte 273 19 4 6 TL1 Timer 1 Low Byte 273 19 4 7 TH0 Timer 0 High Byte 274 19 4 8 TH1 Timer 1 High Byte 274 19 4 9 TMR2CN0 Timer 2 Control 0 275 19 4 10 TMR2RLL Timer 2 Reload Low Byte 276 19 4 11 TMR2RLH Timer 2 Reload High Byte 276 19 4 12 TMR2L Timer 2 Low Byte 276 19 4 13 TMR2H Timer 2 High Byte 277 19 4 14 TMR2CN1 Timer 2 C...

Page 10: ...al Port Data Buffer 302 20 4 4 SBCON1 UART1 Baud Rate Generator Control 303 20 4 5 SBRLH1 UART1 Baud Rate Generator High Byte 303 20 4 6 SBRLL1 UART1 Baud Rate Generator Low Byte 304 20 4 7 UART1FCN0 UART1 FIFO Control 0 305 20 4 8 UART1FCN1 UART1 FIFO Control 1 307 20 4 9 UART1FCT UART1 FIFO Count 308 20 4 10 UART1LIN UART1 LIN Configuration 309 20 4 11 UART1PCF UART1 Configuration 310 21 Univers...

Page 11: ...t Interrupt Enable 338 21 4 19 CMIE USB0 Common Interrupt Enable 339 21 4 20 E0CSR USB0 Endpoint0 Control 340 21 4 21 E0CNT USB0 Endpoint0 Data Count 341 21 4 22 EENABLE USB0 Endpoint Enable 342 21 4 23 EINCSRL USB0 IN Endpoint Control Low 343 21 4 24 EINCSRH USB0 IN Endpoint Control High 344 21 4 25 EOUTCSRL USB0 OUT Endpoint Control Low 345 21 4 26 EOUTCSRH USB0 OUT Endpoint Control High 346 21 ...

Page 12: ...1 C2ADD C2 Address 359 23 4 2 C2DEVID C2 Device ID 359 23 4 3 C2REVID C2 Revision ID 359 23 4 4 C2FPCTL C2 Flash Programming Control 360 23 4 5 C2FPDAT C2 Flash Programming Data 360 24 Revision History 361 silabs com Building a more connected world Rev 0 2 12 ...

Page 13: ...ecoder Port I O Configuration CRC 2 Comparators 12 10 bit ADC Temp Sensor VREF VDD VDD Internal Reference UART1 Timers 0 1 2 3 4 5 3 ch PCA I2C SMBus SPI Port 0 Drivers Port 1 Drivers P0 n Port 2 Drivers P2 n P1 n 1 KB RAM Low Power Crossbar Control Config Logic Units 4 Figure 1 1 Detailed EFM8UB3 Block Diagram This section describes the EFM8UB3 family at a high level For more information on the d...

Page 14: ...ors stopped Regulators in low bias current mode for energy sav ings Timer 3 and 4 may clock from LFOSC0 Code resumes execution on wake event 1 Switch SYSCLK to HFOSC0 2 Set SNOOZE bit in PCON1 USB0 Bus Activity Timer 4 Event SPI0 Activity Port Match Event Comparator 0 Falling Edge CLUn Interrupt Enabled Event Shutdown All internal power nets shut down 5V regulator remains active if enabled Interna...

Page 15: ...s CPU intervention than standard counter timers The PCA consists of a dedicated 16 bit counter timer and one 16 bit capture compare mod ule for each channel The counter timer is driven by a programmable timebase that has flexible external and internal clocking options Each capture compare module may be configured to operate independently in one of five modes Edge Triggered Capture Software Timer H...

Page 16: ...C0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend snooze power modes Timer 4 is a low power wake source and can be chained together with Timer 3 16 bit auto reload timer mode Dual 8 bit auto reload timer mode External pin capture LFOSC0 capture Comparator 0 capture USB Start of Frame SOF capture Configurable Logic output capture Watchdog Timer WDT0 The device includes a...

Page 17: ...FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs UART1 provides the following features Asynchronous transmissions and receptions Dedicated baud rate generator supports baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 5 6 7 8 or 9 bit data Automatic start and stop generation Automatic parity generation and checking Four byte FIFO on transmit and receive A...

Page 18: ...flash memory verification and communications protocols The CRC module supports the standard CCITT 16 16 bit polynomial 0x1021 and includes the following features Support for CCITT 16 polynomial Byte level bit reversal Automatic CRC of flash contents on one or more 256 byte blocks Initial seed selection of 0x0000 or 0xFFFF Configurable Logic Units CLU0 CLU1 CLU2 and CLU3 The Configurable Logic bloc...

Page 19: ... and window compare interrupts supported Flexible output data formatting Includes an internal fast settling reference with two levels 1 65 V and 2 4 V and support for external reference and signal ground Integrated temperature sensor Low Current Comparators CMP0 CMP1 Analog comparators are used to compare the voltage of two analog inputs with a digital output indicating which input voltage is high...

Page 20: ...STb pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0x0000 Reset sources on the device include Power on reset External reset pin Comparator reset Software triggered reset Supply monitor reset monitors VD...

Page 21: ...he device will jump to the reset vector of 0x0000 after any reset More information about the bootloader protocol and usage can be found in AN945 EFM8 Factory Bootloader User Guide Application notes can be found on the Silicon Labs website www silabs com 8bit appnotes or within Simplicity Studio in the Documentation area Reserved 0xFBFF 0x0000 Bootloader Vector Reset Vector 0x9A00 Bootloader Securi...

Page 22: ...y of Pins for Bootload Mode Entry Device Package Pin for Bootload Mode Entry QFN24 P2 0 C2D QSOP24 P2 0 C2D QFN20 P2 0 C2D EFM8UB3 Reference Manual System Overview silabs com Building a more connected world Rev 0 2 22 ...

Page 23: ...cessed using MOVX instructions Total RAM varies based on the specific device The device memory map has more details about the specific amount of RAM available in each area for the different device variants Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF The lower 128 bytes of data memo ry are used for general purpose registers and scratch p...

Page 24: ...grammer s stack can be located anywhere in the 256 byte data memory The stack area is designated using the Stack Pointer SP SFR The SP will point to the last location used The next value pushed on the stack is placed at SP 1 and then SP is incremen ted A reset initializes the stack pointer to location 0x07 Therefore the first value pushed on the stack is placed at location 0x08 which is also the f...

Page 25: ...te 0xFBFD Bootloader Signature Byte Bootloader 40 KB Flash 79 x 512 Byte pages 0x9DFF Read Only 64 Bytes 0xFFC0 0xFFFF Read Only 64 Bytes 0xFFC0 0xFFFE 0xFFFF Memory Lock 128 bit UUID 0xFFCF 0xFFD0 Reserved Figure 2 1 Flash Memory Map 40 KB Devices EFM8UB3 Reference Manual Memory silabs com Building a more connected world Rev 0 2 25 ...

Page 26: ...n Chip RAM Accessed with MOV Instructions as Indicated Figure 2 2 Direct Indirect RAM Memory On Chip XRAM Accessed with MOVX Instructions XRAM 2048 Bytes SYSCLK Domain 0x0000 0x07FF USB FIFO XRAM 1024 Bytes USBCLK Domain 0x0BFF 0x0800 0x0C00 Shadow XRAM Duplicates 0x0000 0x0BFF On 3 KB boundaries 0xFFFF Figure 2 3 XRAM Memory EFM8UB3 Reference Manual Memory silabs com Building a more connected wor...

Page 27: ... Select The XRAM Page Select field provides the high byte of the 16 bit data memory address when using 8 bit MOVX commands effectively selecting a 256 byte page of RAM Since the upper unused bits of the register are always zero the PGSEL field determines which page of XRAM is accessed For example if PGSEL 0x01 addresses 0x0100 to 0x01FF will be accessed by 8 bit MOVX instructions EFM8UB3 Reference...

Page 28: ...re reserved for future use Accessing these areas will have an indeterminate effect and should be avoided SFR Paging The CIP 51 features SFR paging allowing the device to map many SFRs into the 0x80 to 0xFF memory address space The SFR memory space has 256 pages In this way each memory location from 0x80 to 0xFF can access up to 256 SFRs The EFM8UB3 devices utilize multiple SFR pages All of the com...

Page 29: ...terrupt occurs hardware performs the following operations 1 The value if any in the SFRPGIDX 011b location is pushed to the SFRPAGE 100b location 2 The value if any in the SFRPGIDX 010b location is pushed to the SFRPAGE 011b location 3 The value if any in the SFRPGIDX 001b location is pushed to the SFRPAGE 010b location 4 The current SFRPAGE value is pushed to the SFRPGIDX 001b location in the sta...

Page 30: ...IE0 0x8E CKCON0 0xCE CRC0CN0 EIE2 CRC0CN0 0x8F PSCTL 0xCF CRC0FLIP SFRPGCN CRC0FLIP 0x90 P1 0xD0 PSW 0x91 TMR3CN0 CLU2MX 0xD1 REF0CN 0x92 TMR3RLL CLU3MX 0xD2 CRC0ST TMR5RLL CRC0ST 0x93 TMR3RLH SMOD1 0xD3 CRC0CNT TMR5RLH CRC0CNT 0x94 TMR3L SBCON1 0xD4 P0SKIP TMR5L P0SKIP 0x95 TMR3H SBRLL1 0xD5 P1SKIP TMR5H P1SKIP 0x96 PCA0POL SBRLH1 0xD6 SMB0ADM HFO1CAL SMB0ADM 0x97 WDTCN 0xD7 SMB0ADR SFRSTACK SMB0...

Page 31: ...IVID PSTAT0 CLU0FN 0xED P1MAT P1MAT 0xAE USB0ADR 0xEE P1MASK P1MASK 0xAF USB0DAT 0xEF RSTSRC HFOCN SMB0FCT 0xB0 0xF0 B 0xB1 LFO0CN CLU0CF 0xF1 P0MDIN TMR5CN1 P0MDIN 0xB2 ADC0CN1 USB0AEC 0xF2 P1MDIN IPH P1MDIN 0xB3 ADC0AC USB0XCN 0xF3 EIP1 P2MDIN 0xB4 0xF4 EIP2 0xB5 DEVICEID USB0CF 0xF5 EIP1H 0xB6 REVID USB0CDCF 0xF6 PRTDRV EIP2H PRTDRV 0xB7 FLKEY 0xF7 PCA0PWM SPI0FCT 0xB8 IP 0xF8 SPI0CN0 SPI0CN0 0...

Page 32: ...er Control ADC0TK 0xB9 0x00 0x10 ADC0 Burst Mode Track Time B 0xF0 ALL B Register CKCON0 0x8E ALL Clock Control 0 CKCON1 0xA6 0x10 Clock Control 1 CLEN0 0xCB 0x20 Configurable Logic Enable 0 CLIE0 0xCD 0x20 Configurable Logic Interrupt Enable 0 CLIF0 0xE8 0x20 Configurable Logic Interrupt Flag 0 CLKSEL 0xA9 ALL Clock Select CLOUT0 0xD9 0x20 Configurable Logic Output 0 CLU0CF 0xB1 0x20 Configurable...

Page 33: ...RC0 Data Input CRC0ST 0xD2 0x00 0x20 CRC0 Automatic Flash Sector Start DERIVID 0xAD 0x00 Derivative Identification DEVICEID 0xB5 0x00 Device Identification DPH 0x83 ALL Data Pointer High DPL 0x82 ALL Data Pointer Low EIE1 0xE6 0x00 0x10 Extended Interrupt Enable 1 EIE2 0xCE 0x10 Extended Interrupt Enable 2 EIP1 0xF3 0x00 0x10 Extended Interrupt Priority 1 Low EIP1H 0xF5 0x10 Extended Interrupt Pri...

Page 34: ...ar Control PCA0CN0 0xD8 0x00 0x10 PCA Control PCA0CPH0 0xFC 0x00 0x10 PCA Channel 0 Capture Module High Byte PCA0CPH1 0xEA 0x00 0x10 PCA Channel 1 Capture Module High Byte PCA0CPH2 0xEC 0x00 0x10 PCA Channel 2 Capture Module High Byte PCA0CPL0 0xFB 0x00 0x10 PCA Channel 0 Capture Module Low Byte PCA0CPL1 0xE9 0x00 0x10 PCA Channel 1 Capture Module Low Byte PCA0CPL2 0xEB 0x00 0x10 PCA Channel 2 Cap...

Page 35: ...N 0xCF 0x10 SFR Page Control SFRSTACK 0xD7 0x10 SFR Page Stack SMB0ADM 0xD6 0x00 0x20 SMBus 0 Slave Address Mask SMB0ADR 0xD7 0x00 0x20 SMBus 0 Slave Address SMB0CF 0xC1 0x00 0x20 SMBus 0 Configuration SMB0CN0 0xC0 0x00 0x20 SMBus 0 Control SMB0DAT 0xC2 0x00 0x20 SMBus 0 Data SMB0FCN0 0xC3 0x20 SMBus 0 FIFO Control 0 SMB0FCN1 0xC4 0x20 SMBus 0 FIFO Control 1 SMB0FCT 0xEF 0x20 SMBus 0 FIFO Count SM...

Page 36: ...93 0x00 0x10 Timer 3 Reload High Byte TMR3RLL 0x92 0x00 0x10 Timer 3 Reload Low Byte TMR4CN0 0x98 0x10 Timer 4 Control 0 TMR4CN1 0xFF 0x10 Timer 4 Control 1 TMR4H 0xA5 0x10 Timer 4 High Byte TMR4L 0xA4 0x10 Timer 4 Low Byte TMR4RLH 0xA3 0x10 Timer 4 Reload High Byte TMR4RLL 0xA2 0x10 Timer 4 Reload Low Byte TMR5CN0 0xC0 0x10 Timer 5 Control 0 TMR5CN1 0xF1 0x10 Timer 5 Control 1 TMR5H 0xD5 0x10 Tim...

Page 37: ...itor Control WDTCN 0x97 ALL Watchdog Timer Control XBR0 0xE1 0x00 0x20 Port I O Crossbar 0 XBR1 0xE2 0x00 0x20 Port I O Crossbar 1 XBR2 0xE3 0x00 0x20 Port I O Crossbar 2 3 3 SFR Access Control Registers 3 3 1 SFRPAGE SFR Page Bit 7 6 5 4 3 2 1 0 Name SFRPAGE Access RW Reset 0x00 SFR Page ALL SFR Address 0xA7 Bit Name Reset Access Description 7 0 SFRPAGE 0x00 RW SFR Page Specifies the SFR Page use...

Page 38: ...ACK contains the value of the fifth byte of the SFR page stack 3 1 Reserved Must write reset value 0 SFRPGEN 1 RW SFR Automatic Page Control Enable This bit is used to enable automatic page switching on ISR entry exit When set to 1 the current SFRPAGE value will be pushed onto the SFR page stack and SFRPAGE will be set to the page corresponding to the flag which generated the in terrupt upon ISR e...

Page 39: ...ector 0x9A00 Bootloader Security Page 512 Bytes 0xFA00 0xFBFE Lock Byte 0xFBFD Bootloader Signature Byte Bootloader 40 KB Flash 79 x 512 Byte pages 0x9DFF Read Only 64 Bytes 0xFFC0 0xFFFF Read Only 64 Bytes 0xFFC0 0xFFFE 0xFFFF Memory Lock 128 bit UUID 0xFFCF 0xFFD0 Reserved Figure 4 1 Flash Memory Map 40 KB Devices 4 2 Features The flash memory has the following features Up to 40 KB in 512 byte s...

Page 40: ...y the Security Lock Byte Some devices may also include a read only area in the flash memory space for constants such as UID and calibra tion values Note The page containing the flash Security Lock Byte is unlocked when no other flash pages are locked all bits of the Lock Byte are 1 and locked when any other flash pages are locked any bit of the Lock Byte is 0 Table 4 1 Security Byte Decoding Secur...

Page 41: ... the cor rect key codes in sequence before flash operations may be performed The key codes are 0xA5 and 0xF1 The timing does not mat ter but the codes must be written in order If the key codes are written out of order or the wrong codes are written flash writes and erases will be disabled until the next system reset Flash writes and erases will also be disabled if a flash write or erase is attempt...

Page 42: ...ly Maintenance and the Supply Monitor If the system power supply is subject to voltage or current spikes add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded Make certain that the minimum supply rise time specification is met If the system cannot meet this rise time specification then add an...

Page 43: ...t use the internal oscillator or use an external CMOS clock If operating from the external oscillator switch to the internal oscillator during flash write or erase operations The external oscillator can continue to run and the CPU can switch back to the external oscillator after the flash operation has completed 4 4 Flash Control Registers 4 4 1 PSCTL Program Store Control Bit 7 6 5 4 3 2 1 0 Name...

Page 44: ...to FLKEY are performed incorrectly or if a flash write or erase operation is attempted while these operations are disabled the flash will be permanently locked from writes or erasures until the next device reset If an application never writes to flash it can intentionally lock the flash by writing a non 0xA5 value to FLKEY from firmware Read When read bits 1 0 indicate the current flash lock state...

Page 45: ...it is guaranteed unique The UUID resides in the read only area of flash memory which cannot be erased or written in the end application The UUID can be read by firmware or through the debug interface at flash locations 0xFFC0 0xFFCF Table 5 1 UID Location in Memory Device Flash Addresses EFM8UB30F40G EFM8UB31F40G EFM8UB32F40G MSB 0xFFCF 0xFFCE 0xFFCD 0xFFCC 0xFFCB 0xFFCA 0xFFC9 0xFFC8 0xFFC7 0xFFC...

Page 46: ...he ordering code The revision letter may be determined by decoding the REVID register Value Name Description 0x00 EFM8UB30F40G_QFN 20 EFM8UB30F40G R QFN20 0x01 EFM8UB31F40G_QFN 24 EFM8UB31F40G R QFN24 0x02 EFM8UB31F40G_QSO P24 EFM8UB31F40G R QSOP24 5 3 3 REVID Revision Identifcation Bit 7 6 5 4 3 2 1 0 Name REVID Access R Reset Varies SFR Page 0x0 SFR Address 0xB6 Bit Name Reset Access Description...

Page 47: ... next instruction 6 2 Interrupt Sources and Vectors The CIP51 core supports interrupt sources for each peripheral on the device Software can simulate an interrupt for many peripherals by setting any interrupt pending flag to logic 1 If interrupts are enabled for the flag an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt pending flag Ref...

Page 48: ...ed or the new interrupt is of greater priority occurs when the CPU is performing an RETI instruc tion followed by a DIV as the next instruction In this case the response time is 18 system clock cycles 1 clock cycle to detect the interrupt 5 clock cycles to execute the RETI 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR If the CPU is executing an I...

Page 49: ...RFRQE SPI0FCN0_TFRQE SPI0FCN1_SPIFEN SPI0CN0_MODF SPI0CN0_RXOVRN SPI0CN0_SPIF SPI0CN0_WCOL SPI0FCN1_RFRQ SPI0FCN1_TFRQ SMBus 0 0x003B 7 EIE1_ESMB0 SMB0CN0_SI Port Match 0x0043 8 EIE1_EMAT ADC0 Window Compare 0x004B 9 EIE1_EWADC0 ADC0CN0_ADWINT ADC0 End of Conversion 0x0053 10 EIE1_EADC0 ADC0CN0_ADINT PCA0 0x005B 11 EIE1_EPCA0 PCA0CPM0_ECCF PCA0CPM1_ECCF PCA0CPM2_ECCF PCA0PWM_ECOV PCA0CN0_CCF0 PCA0...

Page 50: ...SB0CDCF_SDIE USB0CF_VBUSIE USB0CDSTA_DCDI USB0CDSTA_ERR USB0CDSTA_PDI USB0CDSTA_SDI USB0CF_VBUSI Timer 4 Overflow Cap ture 0x008B 17 EIE2_ET4 TMR4CN0_TF4CEN TMR4CN0_TF4LEN TMR4CN0_TF4H TMR4CN0_TF4L Timer 5 Overflow Cap ture 0x0093 18 EIE2_ET5 TMR5CN0_TF5CEN TMR5CN0_TF5LEN TMR5CN0_TF5H TMR5CN0_TF5L Reserved 0x009B 19 Reserved 0x00A3 20 Configurable Logic 0x00AB 21 EIE2_CL0 CLIE0_C0FIE CLIE0_C0RIE C...

Page 51: ... Description 0 DISABLED Disable all SPI0 interrupts 1 ENABLED Enable interrupt requests generated by SPI0 5 ET2 0 RW Timer 2 Interrupt Enable This bit sets the masking of the Timer 2 interrupt Value Name Description 0 DISABLED Disable Timer 2 interrupt 1 ENABLED Enable interrupt requests generated by the TF2L or TF2H flags 4 ES1 0 RW UART1 Interrupt Enable This bit sets the masking of the UART1 in...

Page 52: ...le This bit sets the masking of the Timer 0 interrupt Value Name Description 0 DISABLED Disable all Timer 0 interrupt 1 ENABLED Enable interrupt requests generated by the TF0 flag 0 EX0 0 RW External Interrupt 0 Enable This bit sets the masking of External Interrupt 0 Value Name Description 0 DISABLED Disable external interrupt 0 1 ENABLED Enable interrupt requests generated by the INT0 input EFM8...

Page 53: ...pt 4 PS1 0 RW UART1 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the UART1 interrupt 3 PT1 0 RW Timer 1 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Timer 1 interrupt 2 PX1 0 RW External Interrupt 1 Priority Control LSB This bit sets the LSB of the priority field for the External Interrupt 1 interrupt 1 PT0 0 RW Timer 0 Interr...

Page 54: ... 4 PHS1 0 RW UART1 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the UART1 interrupt 3 PHT1 0 RW Timer 1 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 1 interrupt 2 PHX1 0 RW External Interrupt 1 Priority Control MSB This bit sets the MSB of the priority field for the External Interrupt 1 interrupt 1 PHT0 0 RW Timer 0 Inte...

Page 55: ...e comparator 1 CPRIF or CPFIF flags 5 ECP0 0 RW Comparator0 CP0 Interrupt Enable This bit sets the masking of the CP0 interrupt Value Name Description 0 DISABLED Disable CP0 interrupts 1 ENABLED Enable interrupt requests generated by the comparator 0 CPRIF or CPFIF flags 4 EPCA0 0 RW Programmable Counter Array PCA0 Interrupt Enable This bit sets the masking of the PCA0 interrupts Value Name Descri...

Page 56: ...RW Port Match Interrupts Enable This bit sets the masking of the Port Match Event interrupt Value Name Description 0 DISABLED Disable all Port Match interrupts 1 ENABLED Enable interrupt requests generated by a Port Match 0 ESMB0 0 RW SMBus SMB0 Interrupt Enable This bit sets the masking of the SMB0 interrupt Value Name Description 0 DISABLED Disable all SMB0 interrupts 1 ENABLED Enable interrupt ...

Page 57: ... interrupt 4 PPCA0 0 RW Programmable Counter Array PCA0 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the PCA0 interrupt 3 PADC0 0 RW ADC0 Conversion Complete Interrupt Priority Control LSB This bit sets the LSB of the priority field for the ADC0 Conversion Complete interrupt 2 PWADC0 0 RW ADC0 Window Comparator Interrupt Priority Control LSB This bit sets the LSB ...

Page 58: ...P0 interrupt 4 PHPCA0 0 RW Programmable Counter Array PCA0 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the PCA0 interrupt 3 PHADC0 0 RW ADC0 Conversion Complete Interrupt Priority Control MSB This bit sets the MSB of the priority field for the ADC0 Conversion Complete interrupt 2 PHWADC0 0 RW ADC0 Window Comparator Interrupt Priority Control MSB This bit sets the...

Page 59: ...rupt requests generated by the TF5L or TF5H flags 2 ET4 0 RW Timer 4 Interrupt Enable This bit sets the masking of the Timer 4 interrupt Value Name Description 0 DISABLED Disable Timer 4 interrupts 1 ENABLED Enable interrupt requests generated by the TF4L or TF4H flags 1 EVBUS 0 RW VBUS and USB Charger Detect Interrupt This bit sets the masking of the VBUS and VBUS and USB Charger Detect interrupt...

Page 60: ...set value 3 PT5 0 RW Timer 5 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Timer 5 interrupt 2 PT4 0 RW Timer 4 Interrupt Priority Control LSB This bit sets the LSB of the priority field for the Timer 4 interrupt 1 PVBUS 0 RW VBUS and USB Charger Detect Interrupt Priority Control LSB This bit sets the LSB of the priority field for the VBUS and USB Charger Detec...

Page 61: ...e reset value 3 PHT5 0 RW Timer 5 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 5 interrupt 2 PHT4 0 RW Timer 4 Interrupt Priority Control MSB This bit sets the MSB of the priority field for the Timer 4 interrupt 1 PHVBUS 0 RW VBUS and USB Charger Detect Interrupt Priority Control MSB This bit sets the MSB of the priority field for the VBUS and USB Charge...

Page 62: ... System Block Diagram Table 7 1 Power Modes Power Mode Details Mode Entry Wake Up Sources Normal Core and all peripherals clocked and fully operational Idle Core halted All peripherals clocked and fully operational Code resumes execution on wake event Set IDLE bit in PCON0 Any interrupt Suspend Core and peripheral clocks halted HFOSC0 and HFOSC1 oscillators stopped Regulators in normal bias mode f...

Page 63: ...power management features of these devices include Supports five power modes 1 Normal mode Core and all peripherals fully operational 2 Idle mode Core halted peripherals fully operational core waiting for interrupt to continue 3 Suspend mode High frequency internal clocks halted select peripherals active waiting for wake signal to continue 4 Snooze mode High frequency internal clocks halted select...

Page 64: ...vides the opportunity for additional power savings allowing the system to remain in the idle mode indefi nitely waiting for an external stimulus to wake up the system 7 4 Stop Mode In stop mode the CPU is halted and peripheral clocks are stopped Analog peripherals remain in their selected states Setting the STOP bit in the PCON0 register causes the controller core to enter stop mode as soon as the...

Page 65: ...o 3 3 V regulator is powered from the VREGIN pin on the device When active it regulates the input voltage to 3 3 V at the VDD pin providing up to 100 mA for the device and system In addition to the normal mode of operation the regulator has two low power modes which may be used to reduce the supply current and may be disabled when not in use Table 7 2 Voltage Regulator Operational Modes Regulator ...

Page 66: ...al purpose flag for use under firmware control 4 GF2 0 RW General Purpose Flag 2 This flag is a general purpose flag for use under firmware control 3 GF1 0 RW General Purpose Flag 1 This flag is a general purpose flag for use under firmware control 2 GF0 0 RW General Purpose Flag 0 This flag is a general purpose flag for use under firmware control 1 STOP 0 RW Stop Mode Select Setting this bit will...

Page 67: ...High speed oscillators will be halted the SYSCLK signal will be gated off and the internal regulator will be placed in a low power state 6 SUSPEND 0 RW Suspend Mode Select Setting this bit will place the device in suspend mode High speed oscillators will be halted and the SYSCLK signal will be gated off 5 0 Reserved Must write reset value EFM8UB3 Reference Manual Power Management and Internal Regu...

Page 68: ...ent occurred 3 SPI0WK 0 RW SPI0 Slave Wake up Event Value Name Description 0 NOT_SET The SPI0 Slave did not receive a byte 1 SET The SPI0 Slave received a byte 2 TMR4WK 0 RW Timer 4 Wake up Event Value Name Description 0 NOT_SET A Timer 4 overflow event did not occur 1 SET A Timer 4 overflow event occurred 1 PMATWK 0 RW Port Match Wake up Event Value Name Description 0 NOT_SET A Port Match event d...

Page 69: ...his bit configures the regulator s behavior when the device enters stop mode Value Name Description 0 ACTIVE Regulator is still active in stop mode Any enabled reset source will re set the device 1 SHUTDOWN Regulator is shut down in stop mode device enters Shutdown mode Only the RSTb pin or power cycle can reset the device 2 0 Reserved Must write reset value EFM8UB3 Reference Manual Power Manageme...

Page 70: ...he BIASENB bit disables the regulator bias voltage when set to 1 Value Name Description 0 ENABLED Regulator bias is enabled 1 DISABLED Regulator bias is disabled 1 SUSEN 0 RW Voltage Regulator 1 Suspend Enable When set to 1 this bit places the 5V regulator into suspend mode Value Name Description 0 NORMAL The 5V regulator is in normal power mode Normal mode is the highest performance mode for the ...

Page 71: ...gs for flexible clock scaling Divide the selected clock source by 1 2 4 8 16 32 64 or 128 HFOSC0 and HFOSC1 include 1 5x pre scalers for further flexibility 8 3 Functional Description 8 3 1 Clock Selection The CLKSEL register is used to select the clock source for the system SYSCLK The CLKSL field selects which oscillator source is used as the system clock while CLKDIV controls the programmable di...

Page 72: ...y little start up time and may be selected as the system clock immediately following the register write which enables the oscillator Calibrating LFOSC0 On chip calibration of the LFOSC0 can be performed using a timer to capture the oscillator period when running from a known time base When a timer is configured for L F Oscillator capture mode a falling edge of the low frequency oscillator s output...

Page 73: ..._DIV_4 SYSCLK is equal to selected clock source divided by 4 0x3 SYSCLK_DIV_8 SYSCLK is equal to selected clock source divided by 8 0x4 SYSCLK_DIV_16 SYSCLK is equal to selected clock source divided by 16 0x5 SYSCLK_DIV_32 SYSCLK is equal to selected clock source divided by 32 0x6 SYSCLK_DIV_64 SYSCLK is equal to selected clock source divided by 64 0x7 SYSCLK_DIV_128 SYSCLK is equal to selected cl...

Page 74: ...0 When set to 0x00 the oscillator operates at its fastest set ting When set to 0xFF the oscillator operates at its slowest setting The reset value is factory calibrated and the oscillator will revert to the calibrated frequency upon reset 8 4 3 HFO1CAL High Frequency Oscillator 1 Calibration Bit 7 6 5 4 3 2 1 0 Name Reserved HFO1CAL Access R RW Reset 0 Varies SFR Page 0x10 SFR Address 0xD6 Bit Nam...

Page 75: ...ted by any block in the device or selected as the SYSCLK source 1 ENABLED Force High Frequency Oscillator 1 to run 6 4 Reserved Must write reset value 3 HFO0EN 0 RW HFOSC0 Oscillator Enable Value Name Description 0 DISABLED Disable High Frequency Oscillator 0 HFOSC0 will still turn on if re quested by any block in the device or selected as the SYSCLK source 1 ENABLED Force High Frequency Oscillato...

Page 76: ...zed 1 SET Internal L F Oscillator frequency stabilized 5 2 OSCLF Varies RW Internal L F Oscillator Frequency Control Fine tune control bits for the Internal L F oscillator frequency When set to 0000b the L F oscillator operates at its fastest setting When set to 1111b the L F oscillator operates at its slowest setting The OSCLF bits should only be changed by firmware when the L F oscillator is dis...

Page 77: ...n open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0x0000 Reset Sources RSTb Supply Moni...

Page 78: ...e ly lost even though the data on the stack is not altered The port I O latches are reset to 0xFF all logic ones in open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state Note During a power on event there may be a short delay before the POR circuitry fires and the RSTb pin is driv...

Page 79: ...ircuit releases the device from reset On exit from a power on reset the PORSF flag is set by hardware to logic 1 When PORSF is set all of the other reset flags in the RSTSRC register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset T...

Page 80: ... firmware performs a software reset the supply monitor will remain disabled and de selected after the reset To protect the integrity of flash contents the supply monitor must be enabled and selected as a reset source if software contains rou tines that erase or write flash memory If the supply monitor is not enabled any erase or write performed on flash memory will be ignor ed t volts Supply Volta...

Page 81: ...e erase or program read targets an illegal address a system reset is generated This may occur due to any of the following A flash write or erase is attempted above user code space A flash read is attempted above user code space A program read is attempted above user code space i e a branch instruction to the reserved area A flash read write or erase attempt is restricted due to a flash security se...

Page 82: ...rflow caused the last reset 2 MCDRSF Varies RW Missing Clock Detector Enable and Flag Read This bit reads 1 if a missing clock detector timeout caused the last reset Write Writing a 1 to this bit enables the missing clock detector The MCD triggers a reset if a missing clock condition is detected 1 PORSF Varies RW Power On Supply Monitor Reset Flag and Supply Monitor Reset Enable Read This bit read...

Page 83: ...zed may generate a system reset In systems where this reset would be undesirable a delay should be introduced between enabling the supply monitor and selecting it as a reset source Value Name Description 0 DISABLED Supply Monitor Disabled 1 ENABLED Supply Monitor Enabled 6 VDDSTAT Varies R Supply Status This bit indicates the current power supply status supply monitor output Value Name Description...

Page 84: ...n or control system solution DATA BUS TMP1 TMP2 PRGM ADDRESS REG PC INCREMENTER ALU PSW DATA BUS DATA BUS MEMORY INTERFACE MEM_ADDRESS D8 PIPELINE BUFFER DATA POINTER INTERRUPT INTERFACE SYSTEM_IRQs EMULATION_IRQ MEM_CONTROL CONTROL LOGIC A16 PROGRAM COUNTER PC STOP CLOCK RESET IDLE POWER CONTROL REGISTER DATA BUS SFR BUS INTERFACE SFR_ADDRESS SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA D8 D8 B REGIS...

Page 85: ... routines examination of the program s call stack and reading writing the contents of registers and memory This method of on chip debugging is completely non intrusive requiring no RAM stack timers or other on chip resources The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs provides an integrated develop ment environment IDE including editor debugg...

Page 86: ...onic number of bytes and number of clock cycles for each instruction Table 10 2 CIP 51 Instruction Set Summary Mnemonic Description Bytes Clock Cycles prefetch off prefetch on Arithmetic Operations ADD A Rn Add register to A 1 1 1 ADD A direct Add direct byte to A 2 2 2 ADD A Ri Add indirect RAM to A 1 2 2 ADD A data Add immediate to A 2 2 2 ADDC A Rn Add register to A with carry 1 1 1 ADDC A dire...

Page 87: ...ive OR immediate to A 2 2 2 XRL direct A Exclusive OR A to direct byte 2 2 2 XRL direct data Exclusive OR immediate to direct byte 3 3 3 CLR A Clear A 1 1 1 CPL A Complement A 1 1 1 RL A Rotate A left 1 1 1 RLC A Rotate A left through Carry 1 1 1 RR A Rotate A right 1 1 1 RRC A Rotate A right through Carry 1 1 1 SWAP A Swap nibbles of A 1 1 1 Data Transfer MOV A Rn Move Register to A 1 1 1 MOV A d...

Page 88: ...r with A 1 1 1 XCH A direct Exchange direct byte with A 2 2 2 XCH A Ri Exchange indirect RAM with A 1 2 2 XCHD A Ri Exchange low nibble of indirect RAM with A 1 2 2 Boolean Manipulation CLR C Clear Carry 1 1 1 CLR bit Clear direct bit 2 2 2 SETB C Set Carry 1 1 2 SETB bit Set direct bit 2 2 2 CPL C Complement Carry 1 1 1 CPL bit Complement direct bit 2 2 2 ANL C bit AND direct bit to Carry 2 2 2 A...

Page 89: ...direct rel Decrement direct byte and jump if not zero 3 3 or 4 3 or 7 NOP No operation 1 1 1 Notes Rn Register R0 R7 of the currently selected register bank Ri Data RAM location addressed indirectly through R0 or R1 rel 8 bit signed twos complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address Thi...

Page 90: ... Bit Name Reset Access Description 7 0 DPH 0x00 RW Data Pointer High The DPH register is the high byte of the 16 bit DPTR DPTR is used to access indirectly addressed flash memory or XRAM 10 4 3 SP Stack Pointer Bit 7 6 5 4 3 2 1 0 Name SP Access RW Reset 0x07 SFR Page ALL SFR Address 0x81 Bit Name Reset Access Description 7 0 SP 0x07 RW Stack Pointer The Stack Pointer holds the location of the top...

Page 91: ...the accumulator for arithmetic operations 10 4 5 B B Register Bit 7 6 5 4 3 2 1 0 Name B Access RW Reset 0x00 SFR Page ALL SFR Address 0xF0 bit addressable Bit Name Reset Access Description 7 0 B 0x00 RW B Register This register serves as a second accumulator for certain arithmetic operations EFM8UB3 Reference Manual CIP 51 Microcontroller Core silabs com Building a more connected world Rev 0 2 91...

Page 92: ...Select These bits select which register bank is used during register accesses Value Name Description 0x0 BANK0 Bank 0 Addresses 0x00 0x07 0x1 BANK1 Bank 1 Addresses 0x08 0x0F 0x2 BANK2 Bank 2 Addresses 0x10 0x17 0x3 BANK3 Bank 3 Addresses 0x18 0x1F 2 OV 0 RW Overflow Flag This bit is set to 1 under the following circumstances 1 An ADD ADDC or SUBB instruction causes a sign change overflow 2 A MUL ...

Page 93: ...ogrammed to the smallest allowed value according to the system clock speed When transitioning to a faster clock speed program FLRT before changing the clock When changing to a slower clock speed change the clock before changing FLRT Value Name Description 0 SYSCLK_BE LOW_25_MHZ SYSCLK 25 MHz 1 SYSCLK_BE LOW_50_MHZ SYSCLK 50 MHz 3 0 Reserved Must write reset value EFM8UB3 Reference Manual CIP 51 Mi...

Page 94: ... 5 2 4 2 2 2 1 3 PCA ECI 1 1 1 1 CMP0 In CMP1 In INT0 INT1 Port Match P0 0 VREF P0 1 AGND P0 2 P0 3 EXTCLK P0 4 P0 6 CNVSTR P0 7 P0 5 Port Control and Config UART1 4 P0 P1 P0 ADC0 In P0 P1 P2 P1 P2 P0 P1 P0 Configurable Logic P2 1 P2 0 Figure 11 1 Port I O Block Diagram 11 2 Features The port control block offers the following features Up to 17 multi functions I O pins supporting digital and analo...

Page 95: ...r open drain WEAKPUD Weak Pull Up Disable Figure 11 2 Port I O Cell Block Diagram Configuring Port Pins For Analog Modes Any pins to be used for analog functions should be configured for analog mode When a pin is configured for analog I O its weak pull up digital driver and digital receiver are disabled This saves power by eliminating crowbar current and reduces noise on the analog input Pins conf...

Page 96: ...t Open drain outputs are configured exactly as digital inputs The pin may be driven low by an assigned peripheral or by writing 0 to the associated bit in the Pn register if the signal is a GPIO To configure a pin as a digital push pull output 1 Set the bit associated with the pin in the PnMDIN register to 1 This selects digital mode for the pin 2 Set the bit associated with the pin in the PnMDOUT...

Page 97: ...in XBR0 is set to 1 XBR0 XBR1 XBR2 External Interrupt 0 External Interrupt 1 P0 0 P0 7 IT01CF Conversion Start CNVSTR P0 6 ADC0CN0 External Clock Input EXTCLK P0 3 CLKSEL Port Match P0 0 P1 6 P2 1 P0MASK P0MAT P1MASK P1MAT P2MASK P2MAT VBUS P2 1 USB0CF Configurable Logic Inputs A and B Assignable pins vary across CLUs P0 0 P1 6 CLUnMX Configurable Logic Unit 0 Output CLU0OUT P0 2 CLU0CF Configurab...

Page 98: ...ic state of any digital I O pin as signed to a crossbar peripheral but the output state cannot be directly modified Figure 11 3 Crossbar Priority Decoder Example Assignments on page 98 shows an example of the resulting pin assignments of the device with UART1 and SPI0 enabled and P0 3 skipped P0SKIP 0x08 UART1 is the highest priority when URT1EL in XBR0 is set to 1 and it will be assigned first Wh...

Page 99: ... crossbar When these signals are enabled the Crossbar should be manually configured to skip the corresponding port pins Pins can be skipped by setting the corresponding bit in PnSKIP to 1 Notes 1 UART1 pins are available in these locations to be backwards compatible with UART0 on other devices UART1 is available either in the fixed P0 4 and P0 5 locations or the standard UART1 crossbar locations T...

Page 100: ...ecognized It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated 11 3 5 Port Match Port match functionality allows system events to be triggered by a logic value change on one or more port I O pins A software control led value stored in the PnMATCH registers specifies the expected or normal logic values of the associated p...

Page 101: ...outed to Port pin 5 CP1E 0 RW Comparator1 Output Enable Value Name Description 0 DISABLED CP1 unavailable at Port pin 1 ENABLED CP1 routed to Port pin 4 CP0AE 0 RW Comparator0 Asynchronous Output Enable Value Name Description 0 DISABLED Asynchronous CP0 unavailable at Port pin 1 ENABLED Asynchronous CP0 routed to Port pin 3 CP0E 0 RW Comparator0 Output Enable Value Name Description 0 DISABLED CP0 ...

Page 102: ... bit or URT1E in XBR2 can be used to enable UART1 Using this bit will place UART1 on P0 4 and P0 5 Using the URT1E bit in XBR2 will enable UART1 on any next available crossbar pin Value Name Description 0 DISABLED UART1 I O unavailable at Port pin 1 ENABLED UART1 TX0 RX0 routed to Port pins P0 4 and P0 5 EFM8UB3 Reference Manual Port I O Crossbar External Interrupts and Port Match silabs com Build...

Page 103: ...routed to Port pin 3 T0E 0 RW T0 Enable Value Name Description 0 DISABLED T0 unavailable at Port pin 1 ENABLED T0 routed to Port pin 2 ECIE 0 RW PCA0 External Counter Input Enable Value Name Description 0 DISABLED ECI unavailable at Port pin 1 ENABLED ECI routed to Port pin 1 0 PCA0ME 0x0 RW PCA Module I O Enable Value Name Description 0x0 DISABLED All PCA I O unavailable at Port pins 0x1 CEX0 CEX...

Page 104: ...ue 2 URT1CTSE 0 RW UART1 CTS Input Enable Value Name Description 0 DISABLED UART1 CTS1 unavailable at Port pin 1 ENABLED UART1 CTS1 routed to Port pin 1 URT1RTSE 0 RW UART1 RTS Output Enable Value Name Description 0 DISABLED UART1 RTS1 unavailable at Port pin 1 ENABLED UART1 RTS1 routed to Port pin 0 URT1E 0 RW UART1 I O Enable Either this bit or URT1EL in XBR0 can be used to enable UART1 Using th...

Page 105: ... drive strength 1 HIGH_DRIVE All pins on P2 use high drive strength 1 P1DRV 1 RW Port 1 Drive Strength Value Name Description 0 LOW_DRIVE All pins on P1 use low drive strength 1 HIGH_DRIVE All pins on P1 use high drive strength 0 P0DRV 1 RW Port 0 Drive Strength Value Name Description 0 LOW_DRIVE All pins on P0 use low drive strength 1 HIGH_DRIVE All pins on P0 use high drive strength EFM8UB3 Refe...

Page 106: ...logic value is compared to P0MAT 7 6 B6 0 RW Port 0 Bit 6 Mask Value See bit 7 description 5 B5 0 RW Port 0 Bit 5 Mask Value See bit 7 description 4 B4 0 RW Port 0 Bit 4 Mask Value See bit 7 description 3 B3 0 RW Port 0 Bit 3 Mask Value See bit 7 description 2 B2 0 RW Port 0 Bit 2 Mask Value See bit 7 description 1 B1 0 RW Port 0 Bit 1 Mask Value See bit 7 description 0 B0 0 RW Port 0 Bit 0 Mask V...

Page 107: ...d with logic HIGH 6 B6 1 RW Port 0 Bit 6 Match Value See bit 7 description 5 B5 1 RW Port 0 Bit 5 Match Value See bit 7 description 4 B4 1 RW Port 0 Bit 4 Match Value See bit 7 description 3 B3 1 RW Port 0 Bit 3 Match Value See bit 7 description 2 B2 1 RW Port 0 Bit 2 Match Value See bit 7 description 1 B1 1 RW Port 0 Bit 1 Match Value See bit 7 description 0 B0 1 RW Port 0 Bit 0 Match Value See b...

Page 108: ...atch See bit 7 description 4 B4 1 RW Port 0 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 0 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 0 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 0 Bit 1 Latch See bit 7 description 0 B0 1 RW Port 0 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading th...

Page 109: ...ee bit 7 description 5 B5 1 RW Port 0 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 0 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 0 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 0 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 0 Bit 1 Input Mode See bit 7 description 0 B0 1 RW Port 0 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have t...

Page 110: ...pull 6 B6 0 RW Port 0 Bit 6 Output Mode See bit 7 description 5 B5 0 RW Port 0 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 0 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 0 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 0 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 0 Bit 1 Output Mode See bit 7 description 0 B0 0 RW Port 0 Bit 0 Output Mode See bit 7 descript...

Page 111: ... 7 pin is skipped by the crossbar 6 B6 0 RW Port 0 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 0 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 0 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 0 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 0 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 0 Bit 1 Skip See bit 7 description 0 B0 0 RW Port 0 Bit 0 Skip See bit 7 description EFM8UB3 Referenc...

Page 112: ...logic value is compared to P1MAT 7 6 B6 0 RW Port 1 Bit 6 Mask Value See bit 7 description 5 B5 0 RW Port 1 Bit 5 Mask Value See bit 7 description 4 B4 0 RW Port 1 Bit 4 Mask Value See bit 7 description 3 B3 0 RW Port 1 Bit 3 Mask Value See bit 7 description 2 B2 0 RW Port 1 Bit 2 Mask Value See bit 7 description 1 B1 0 RW Port 1 Bit 1 Mask Value See bit 7 description 0 B0 0 RW Port 1 Bit 0 Mask V...

Page 113: ...d with logic HIGH 6 B6 1 RW Port 1 Bit 6 Match Value See bit 7 description 5 B5 1 RW Port 1 Bit 5 Match Value See bit 7 description 4 B4 1 RW Port 1 Bit 4 Match Value See bit 7 description 3 B3 1 RW Port 1 Bit 3 Match Value See bit 7 description 2 B2 1 RW Port 1 Bit 2 Match Value See bit 7 description 1 B1 1 RW Port 1 Bit 1 Match Value See bit 7 description 0 B0 1 RW Port 1 Bit 0 Match Value See b...

Page 114: ...Latch See bit 7 description 4 B4 1 RW Port 1 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 1 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 1 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 1 Bit 1 Latch See bit 7 description 0 B0 1 RW Port 1 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading t...

Page 115: ...See bit 7 description 5 B5 1 RW Port 1 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 1 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 1 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 1 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 1 Bit 1 Input Mode See bit 7 description 0 B0 1 RW Port 1 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have ...

Page 116: ...pull 6 B6 0 RW Port 1 Bit 6 Output Mode See bit 7 description 5 B5 0 RW Port 1 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 1 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 1 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 1 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 1 Bit 1 Output Mode See bit 7 description 0 B0 0 RW Port 1 Bit 0 Output Mode See bit 7 descript...

Page 117: ... 7 pin is skipped by the crossbar 6 B6 0 RW Port 1 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 1 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 1 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 1 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 1 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 1 Bit 1 Skip See bit 7 description 0 B0 0 RW Port 1 Bit 0 Skip See bit 7 description EFM8UB3 Referenc...

Page 118: ...W Port 2 Bit 0 Mask Value See bit 1 description 11 4 18 P2MAT Port 2 Match Bit 7 6 5 4 3 2 1 0 Name Reserved B1 B0 Access R RW RW Reset 0x00 0 0 SFR Page 0x20 SFR Address 0xFB Bit Name Reset Access Description 7 2 Reserved Must write reset value 1 B1 0 RW Port 2 Bit 1 Match Value Value Name Description 0 LOW P2 1 pin logic value is compared with logic LOW 1 HIGH P2 1 pin logic value is compared wi...

Page 119: ...r returns the logic value at the pin regardless if it is configured as output or input 11 4 20 P2MDIN Port 2 Input Mode Bit 7 6 5 4 3 2 1 0 Name Reserved B1 B0 Access R RW RW Reset 0x00 0 0 SFR Page 0x20 SFR Address 0xF3 Bit Name Reset Access Description 7 2 Reserved Must write reset value 1 B1 0 RW Port 2 Bit 1 Input Mode Value Name Description 0 ANALOG P2 1 pin is configured for analog mode 1 DI...

Page 120: ...ription 7 2 Reserved Must write reset value 1 B1 0 RW Port 2 Bit 1 Output Mode Value Name Description 0 OPEN_DRAIN P2 1 output is open drain 1 PUSH_PULL P2 1 output is push pull 0 B0 0 RW Port 2 Bit 0 Output Mode See bit 1 description EFM8UB3 Reference Manual Port I O Crossbar External Interrupts and Port Match silabs com Building a more connected world Rev 0 2 120 ...

Page 121: ...lected pin Value Name Description 0x0 P0_0 Select P0 0 0x1 P0_1 Select P0 1 0x2 P0_2 Select P0 2 0x3 P0_3 Select P0 3 0x4 P0_4 Select P0 4 0x5 P0_5 Select P0 5 0x6 P0_6 Select P0 6 0x7 P0_7 Select P0 7 3 IN0PL 0 RW INT0 Polarity Value Name Description 0 ACTIVE_LOW INT0 input is active low 1 ACTIVE_HIGH INT0 input is active high 2 0 IN0SL 0x1 RW INT0 Port Pin Selection These bits select which port ...

Page 122: ...x3 P0_3 Select P0 3 0x4 P0_4 Select P0 4 0x5 P0_5 Select P0 5 0x6 P0_6 Select P0 6 0x7 P0_7 Select P0 7 EFM8UB3 Reference Manual Port I O Crossbar External Interrupts and Port Match silabs com Building a more connected world Rev 0 2 122 ...

Page 123: ...0 External Pins SAR Analog to Digital Converter Accumulator Window Compare SYSCLK Clock Divider Less Than Greater Than Device Ground AGND 0 5x 1x gain Control Configuration ADC0 VDD VREF Internal LDO 1 65 V 2 4 V Reference ADWINT Window Interrupt SAR clock Temp Sensor VDD GND Internal LDO Input Multiplexer Selection ADINT Interrupt Flag Reference Selection Conversion Trigger Selection ADBUSY On De...

Page 124: ...ed between the ground pin GND or a port pin dedicated to analog ground AGND The voltage and ground reference options are configured using the REF0CN register The REFSL field selects be tween the different reference options while GNDSL configures the ground connection 12 3 2 1 Internal Voltage Reference The high speed internal reference offers two programmable voltage levels and is self contained a...

Page 125: ...r which allows selection of external pins the on chip temperature sensor the internal regulated sup ply the VDD supply or GND ADC input channels are selected using the ADC0MX register Note Any port pins selected as ADC inputs should be configured as analog inputs in their associated port configuration register and configured to be skipped by the crossbar 12 3 3 1 Multiplexer Channel Selection Tabl...

Page 126: ...ates the conversion 2 Hardware triggered An automatic internal event such as a timer overflow initiates the conversion 3 External pin triggered A rising edge on the CNVSTR input signal initiates the conversion Writing a 1 to ADBUSY provides software control of ADC0 whereby conversions are performed on demand All other trigger sources occur autonomous to code execution When the conversion is comple...

Page 127: ...PLE depends on the PGA gain See the electrical specifications for details Figure 12 2 ADC Equivalent Input Circuit The required ADC0 settling time for a given settling accuracy SA may be approximated as follows t ln 2n SA x RTOTAL x CSAMPLE Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle within 1 4 LSB t is the required settling time in seconds RTOTAL is ...

Page 128: ...rigger Source SAR Clocks Track or Convert Convert Track ADTM 0 Track Convert Low Power Mode Low Power or Convert 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 12 3 Track and Conversion Example Timing Normal Non Burst Operation When burst mode is enabled additional tracking times may need to be specified Because burst mode may power the ADC on f...

Page 129: ...the state the ADC enters when not tracking or performing conversions If ADEN is set to logic 0 the ADC is powered down after each burst If AD EN is set to logic 1 the ADC remains enabled after each burst On each convert start signal the ADC is awakened from its idle power state If the ADC is powered down it will automatically power up and wait for the amount of time programmed to the ADPWR bits be...

Page 130: ...the maximum output value is 4 x 1023 4092 rather than the max value of 2 12 1 4095 that is produced by a traditional 12 bit converter To further increase resolution the burst mode repeat value may be configured to any multiple of four conversions For example if a repeat value of 16 is selected the ADC0 output will be a 14 bit number sum of four 12 bit numbers with 13 effective bits of resolution T...

Page 131: ...L registers are set to 0 The exam ple below shows the right justified result for various input voltages and repeat counts Notice that accumulating 2n samples is equiva lent to left shifting by n bit positions when all samples returned from the ADC have the same value Table 12 3 Effects of ADRPT on Output Code Input Voltage Repeat Count 4 Repeat Count 16 Repeat Count 64 VREF x 1023 1024 0x0FFC 0x3F...

Page 132: ...hput Reference Source Mode Configuration SAR Clock Speed Other Register Field Set tings 325 800 ksps Any Always On ADEN 1 ADBMEN 0 12 25 MHz1 ADSC 1 ADC0PWR 0x40 ADC0TK N A ADRPT 0 0 325 ksps External Burst Mode ADEN 0 ADBMEN 1 12 25 MHz1 ADSC 1 ADC0PWR 0x44 ADC0TK 0x3A ADRPT 0 250 325 ksps Internal Burst Mode ADEN 0 ADBMEN 1 12 25 MHz1 ADSC 1 ADC0PWR 0x44 ADC0TK 0x3A ADRPT 0 200 250 ksps Internal...

Page 133: ... current savings can be realiz ed The length of time the ADC is active during each burst contains power up time at the beginning of the burst as well as the conver sion time required for each conversion in the burst The power on time is only required at the beginning of each burst When compared with single sample bursts to collect the same number of conversions multi sample bursts will consume sig...

Page 134: ...how how the ADC0GT and ADC0LT registers may be configured to set the ADWINT flag when the ADC output code is above below beween or outside of specific values Table 12 7 ADC Window Comparator Example Above 0x0080 Comparison Register Settings Output Code ADC0H L ADWINT Effects 0x03FF ADWINT 1 0x0081 ADC0GTH L 0x0080 0x0080 ADWINT Not Affected 0x007F 0x0001 ADC0LTH L 0x0000 0x0000 Table 12 8 ADC Wind...

Page 135: ...ator Example Outside the 0x0040 to 0x0080 range Comparison Register Settings Output Code ADC0H L ADWINT Effects 0x03FF ADWINT 1 0x0081 ADC0GTH L 0x0080 0x0080 ADWINT Not Affected 0x007F 0x0041 ADC0LTH L 0x0040 0x0040 0x003F ADWINT 1 0x0000 EFM8UB3 Reference Manual Analog to Digital Converter ADC0 silabs com Building a more connected world Rev 0 2 135 ...

Page 136: ...r Temperature Slope x Offset Offset Slope Offset Slope Voltage V at 0 deg Celsius V deg C Temp C V TEMP V TEMP Temp C Figure 12 6 Temperature Sensor Transfer Function 12 3 13 1 Temperature Sensor Calibration The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements For absolute tem perature measurements offset and or gain calibration is recom...

Page 137: ...e Interrupt Flag Set by hardware upon completion of a data conversion ADBMEN 0 or a burst of conversions ADBMEN 1 Can trigger an interrupt Must be cleared by firmware 4 ADBUSY 0 RW ADC Busy Writing 1 to this bit initiates an ADC conversion when ADCM 000 This bit should not be polled to indicate when a conver sion is complete Instead the ADINT bit should be used when polling for conversion completi...

Page 138: ...flow of Timer 2 when CEX2 is logic high 0x7 TIMER4 ADC0 conversion initiated on overflow of Timer 4 0x8 TIMER5 ADC0 conversion initiated on overflow of Timer 5 0x9 CLU0 ADC0 conversion initiated on CLU0 Output 0xA CLU1 ADC0 conversion initiated on CLU1 Output 0xB CLU2 ADC0 conversion initiated on CLU2 Output 0xC CLU3 ADC0 conversion initiated on CLU3 Output 3 1 Reserved Must write reset value 0 AD...

Page 139: ... Mode Enable Value Name Description 0 NORMAL ADC0 operates in 10 bit or 12 bit mode normal operation 1 8_BIT ADC0 operates in 8 bit mode 1 ADTM 0 RW Track Mode Selects between Normal or Delayed Tracking Modes Value Name Description 0 TRACK_NORMAL Normal Track Mode When ADC0 is enabled conversion begins imme diately following the start of conversion signal 1 TRACK_DELAYED Delayed Track Mode When AD...

Page 140: ...W Accumulator Shift and Justify Specifies the format of data read from ADC0H ADC0L All remaining bit combinations are reserved Value Name Description 0x0 RIGHT_NO_SHIFT Right justified No shifting applied 0x1 RIGHT_SHIFT_1 Right justified Shifted right by 1 bit 0x2 RIGHT_SHIFT_2 Right justified Shifted right by 2 bits 0x3 RIGHT_SHIFT_3 Right justified Shifted right by 3 bits 0x4 LEFT_NO_SHIFT Left...

Page 141: ...m and Accumulate 32 conversions 8 conversions in 12 bit mode 0x5 ACC_64 Perform and Accumulate 64 conversions 16 conversions in 12 bit mode EFM8UB3 Reference Manual Analog to Digital Converter ADC0 silabs com Building a more connected world Rev 0 2 141 ...

Page 142: ... operation for the multiplexer and voltage reference buffers Value Name Description 0 LP_MUX_VREF_DISA BLED Low power mode disabled 1 LP_MUX_VREF_ENA BLED Low power mode enabled SAR clock 4 MHz 4 ADLPM 0 RW Low Power Mode Enable This bit can be used to reduce power to the ADC s internal common mode buffer It can be set to 1 to reduce power when tracking times in the application are longer slower s...

Page 143: ... field sets the time delay between consecutive conversions performed in Burst Mode When ADTM is set an additional 4 SARCLKs are added to this time Tbmtk 64 ADTK Fhfosc The Burst Mode track delay is not inserted prior to the first conversion The required tracking time for the first conversion should be defined with the ADPWR field 12 4 7 ADC0H ADC0 Data Word High Byte Bit 7 6 5 4 3 2 1 0 Name ADC0H...

Page 144: ...ADC0GTH ADC0 Greater Than High Byte Bit 7 6 5 4 3 2 1 0 Name ADC0GTH Access RW Reset 0xFF SFR Page 0x0 0x10 SFR Address 0xC4 Bit Name Reset Access Description 7 0 ADC0GTH 0xFF RW Greater Than High Byte Most significant byte of the 16 bit greater than window compare register 12 4 10 ADC0GTL ADC0 Greater Than Low Byte Bit 7 6 5 4 3 2 1 0 Name ADC0GTL Access RW Reset 0xFF SFR Page 0x0 0x10 SFR Addres...

Page 145: ...icant byte of the 16 bit less than window compare register In 8 bit mode this register should be set to 0x00 12 4 13 ADC0MX ADC0 Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Name Reserved ADC0MX Access R RW Reset 0x0 0x1F SFR Page 0x0 0x10 SFR Address 0xBB Bit Name Reset Access Description 7 5 Reserved Must write reset value 4 0 ADC0MX 0x1F RW AMUX0 Positive Input Selection Selects the positive input...

Page 146: ... reference is the GND pin 1 AGND_PIN The ADC0 ground reference is the P0 1 AGND pin 4 3 REFSL 0x3 RW Voltage Reference Select Selects the ADC0 voltage reference Value Name Description 0x0 VREF_PIN The ADC0 voltage reference is the P0 0 VREF pin 0x1 VDD_PIN The ADC0 voltage reference is the VDD pin 0x2 INTERNAL_LDO The ADC0 voltage reference is the internal 1 8 V digital supply voltage 0x3 INTERNAL...

Page 147: ...e DAC Inversion Positive Input Selection Negative Input Selection Internal LDO VDD Port Pins VDD Port Pins GND Figure 13 1 Comparator Block Diagram 13 2 Features The comparator includes the following features Up to 8 CMP0 or 8 CMP1 external positive inputs Up to 8 CMP0 or 8 CMP1 external negative inputs Additional input options Internal connection to LDO output Direct connection to GND Direct conn...

Page 148: ... is determined by the settings of the CPHYN bits Settings of 20 10 or 5 mV nominal of nega tive hysteresis can be programmed or negative hysteresis can be disabled In a similar way the amount of positive hysteresis is deter mined by the setting the CPHYP bits CPn Positive programmable hysteresis CPHYP CPn Negative programmable hysteresis CPHYN CP0 out Figure 13 2 Comparator Hysteresis Plot 13 3 3 ...

Page 149: ...er Channels CMXN Setting in Register CMP0MX Signal Name Enumeration Name QFN24 Pin Name QSOP24 Pin Name QFN20 Pin Name 0000 CMP0N 0 CMP0N0 P0 0 P0 0 P0 0 0001 CMP0N 1 CMP0N1 P0 1 P0 1 P0 1 0010 CMP0N 2 CMP0N2 P0 2 P0 2 P0 2 0011 CMP0N 3 CMP0N3 P0 3 P0 3 P0 3 0100 CMP0N 4 CMP0N4 P0 4 P0 4 P0 4 0101 CMP0N 5 CMP0N5 P0 5 P0 5 P0 5 0110 CMP0N 6 CMP0N6 P0 6 P0 6 P0 6 0111 CMP0N 7 CMP0N7 P0 7 P0 7 P0 7 1...

Page 150: ...13 4 CMP1 Negative Input Multiplexer Channels CMXN Setting in Register CMP1MX Signal Name Enumeration Name QFN24 Pin Name QSOP24 Pin Name QFN20 Pin Name 0000 CMP1N 0 CMP1N0 P1 0 P1 0 P1 0 0001 CMP1N 1 CMP1N1 P1 1 P1 1 P1 1 0010 CMP1N 2 CMP1N2 P1 2 P1 2 P1 2 0011 CMP1N 3 CMP1N3 P1 3 P1 3 Reserved 0100 CMP1N 4 CMP1N4 P1 4 P1 4 Reserved 0101 CMP1N 5 CMP1N5 P1 5 P1 5 Reserved 0110 CMP1N 6 CMP1N6 P1 6 ...

Page 151: ...tion the comparator mux channels are directly connected to the comparator inputs The reference DAC is not used in this configuration CMPnP 0 CMPnP 1 CMPnP 2 CMPnP 3 CMPnP x CMPnN 0 CMPnN 1 CMPnN 2 CMPnN 3 CMPnN x CMPn CMPn CMXP CMXN Figure 13 3 Direct Input Connection When INSL is configured to ground the negative input the positive comparator mux selection is directly connected to the positive co...

Page 152: ...arator input CMPnP 0 CMPnP 1 CMPnP 2 CMPnP 3 CMPnP x CMPnN 0 CMPnN 1 CMPnN 2 CMPnN 3 CMPnN x CMPn CMPn DACLVL CMXP CMXN DAC Full Scale Reference Figure 13 5 Negative Input DAC Connection When INSL is configured to use the reference DAC on the positive channel the negative comparator mux selection is directly connec ted to the negative comparator input The positive mux selection becomes the full sc...

Page 153: ...e and the CPRIF flag is set to logic 1 upon the comparator rising edge occurrence Once set these bits remain set until cleared by software The comparator rising edge interrupt mask is enabled by setting CPRIE to a logic 1 The com parator falling edge interrupt mask is enabled by setting CPFIE to a logic 1 False rising edges and falling edges may be detected when the comparator is first powered on ...

Page 154: ... prevent undersirable glitches during known noise events such as power FET switching The CPINH bit in register CMPnCN1 enables this option When CPINH is set to 1 the comparator output will hold its current state any time the CEX2 channel is logic low EFM8UB3 Reference Manual Comparators CMP0 and CMP1 silabs com Building a more connected world Rev 0 2 154 ...

Page 155: ...re Value Name Description 0 NOT_SET No comparator rising edge has occurred since this flag was last cleared 1 RISING_EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT_SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING_EDGE Comparator falling edge has occurred 3 2 CPHYP 0x0 ...

Page 156: ...on 0x0 DISABLED Negative Hysteresis disabled 0x1 ENABLED_MODE1 Negative Hysteresis Hysteresis 1 0x2 ENABLED_MODE2 Negative Hysteresis Hysteresis 2 0x3 ENABLED_MODE3 Negative Hysteresis Hysteresis 3 Maximum EFM8UB3 Reference Manual Comparators CMP0 and CMP1 silabs com Building a more connected world Rev 0 2 156 ...

Page 157: ...d 1 RISE_INT_ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL_INT_DISABLED Comparator falling edge interrupt disabled 1 FALL_INT_ENABLED Comparator falling edge interrupt enabled 3 2 INSL 0x0 RW Comparator Input Selection These bits control how the comparator input pins CMP and CMP are connected internally Value Na...

Page 158: ...0x1 MODE1 Mode 1 0x2 MODE2 Mode 2 0x3 MODE3 Mode 3 Slowest Response Time Lowest Power Consumption 13 4 3 CMP0MX Comparator 0 Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Name CMXN CMXP Access RW RW Reset 0xF 0xF SFR Page 0x0 0x10 SFR Address 0x9F Bit Name Reset Access Description 7 4 CMXN 0xF RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 0 CMXP ...

Page 159: ... output will always reflect the input conditions 1 ENABLED The comparator output will hold state any time the PCA CEX2 channel is low 6 Reserved Must write reset value 5 0 DACLVL 0x00 RW Internal Comparator DAC Reference Level These bits control the output of the comparator reference DAC The voltage is given by DAC Output CMPREF DACLVL 64 CMPREF is the selected input reference for the DAC accordin...

Page 160: ...re Value Name Description 0 NOT_SET No comparator rising edge has occurred since this flag was last cleared 1 RISING_EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT_SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING_EDGE Comparator falling edge has occurred 3 2 CPHYP 0x0 ...

Page 161: ...on 0x0 DISABLED Negative Hysteresis disabled 0x1 ENABLED_MODE1 Negative Hysteresis Hysteresis 1 0x2 ENABLED_MODE2 Negative Hysteresis Hysteresis 2 0x3 ENABLED_MODE3 Negative Hysteresis Hysteresis 3 Maximum EFM8UB3 Reference Manual Comparators CMP0 and CMP1 silabs com Building a more connected world Rev 0 2 161 ...

Page 162: ...d 1 RISE_INT_ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL_INT_DISABLED Comparator falling edge interrupt disabled 1 FALL_INT_ENABLED Comparator falling edge interrupt enabled 3 2 INSL 0x0 RW Comparator Input Selection These bits control how the comparator input pins CMP and CMP are connected internally Value Na...

Page 163: ...0x1 MODE1 Mode 1 0x2 MODE2 Mode 2 0x3 MODE3 Mode 3 Slowest Response Time Lowest Power Consumption 13 5 3 CMP1MX Comparator 1 Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Name CMXN CMXP Access RW RW Reset 0xF 0xF SFR Page 0x0 0x10 SFR Address 0xAA Bit Name Reset Access Description 7 4 CMXN 0xF RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 0 CMXP ...

Page 164: ... output will always reflect the input conditions 1 ENABLED The comparator output will hold state any time the PCA CEX2 channel is low 6 Reserved Must write reset value 5 0 DACLVL 0x00 RW Internal Comparator DAC Reference Level These bits control the output of the comparator reference DAC The voltage is given by DAC Output CMPREF DACLVL 64 CMPREF is the selected input reference for the DAC accordin...

Page 165: ...ay be used as inputs to each CLU and the outputs may be routed out to port I O pins or directly to select peripheral inputs CLU0 Configurable Logic CL Output Drive Logic CLU3OUT Interrupt Logic CLU2OUT CLU1OUT CLU0OUT CLU1 CLU2 CLU3 CL Interrupt Control Logic Timer 2 4 5 Overflow CEX2 UART1_TX CMP1_A Timer 3 4 5 Overflow CEX1 CMP0_A SPI MOSI Timer 2 3 4 CEX0 SPI MISO Timer 2 3 5 Overflow CMP0_A AD...

Page 166: ...s of the Configurable Logic block are as follows Four configurable logic units CLUs with direct pin and internal logic connections Each unit supports 256 different combinatorial logic functions AND OR XOR muxing etc and includes a clocked flip flop for syn chronous operations Units may be operated synchronously or asynchronously May be cascaded together to perform more complicated logic functions ...

Page 167: ...MXA and MXB fields in the CLUnMX register and may be one of many different internal and external signals When another CLU output is selected as an input the asynchronous output from that CLU is used enabling more complex boolean logic functions to be implemented Note When using timer overflow events as an input the timer overflow event is a pulse which will be logic high for one SYSCLK cycle and l...

Page 168: ...10 P0 1 P0 3 P0 5 P0 7 111 P1 6 P0 7 P1 0 P0 1 Table 14 2 CLUnB Input Selection CLUnMX MXB CLU0B CLU1B CLU2B CLU3B 000 C0OUTa C0OUTa C0OUTa C0OUTa 001 C1OUTa C1OUTa C1OUTa C1OUTa 010 C2OUTa C2OUTa C2OUTa C2OUTa 011 C3OUTa C3OUTa C3OUTa C3OUTa 100 ADBUSY Reserved CMP0 Asynchronous Output CMP1 Asynchronous Output 101 Reserved SPI MISO Slave output SPI MOSI Master out put UART TX 110 P1 0 P0 6 P0 4 P...

Page 169: ...U input are SYSCLK synchronized CLU output signals to any CLU input are not SYSCLK synchronized 14 3 4 LUT Configuration The boolean logic function in each CLU is determined by the LUT and may be changed by programming the FNSEL field in register CLUnFN The LUT is implemented as an 8 input multiplexer The bits of FNSEL map to the 8 multiplexer inputs and the output of the LUT is selected by the co...

Page 170: ... logic low 1 ENABLE CLU3 is enabled 2 C2EN 0 RW CLU2 Enable Value Name Description 0 DISABLE CLU2 is disabled The output of the block will be logic low 1 ENABLE CLU2 is enabled 1 C1EN 0 RW CLU1 Enable Value Name Description 0 DISABLE CLU1 is disabled The output of the block will be logic low 1 ENABLE CLU1 is enabled 0 C0EN 0 RW CLU0 Enable Value Name Description 0 DISABLE CLU0 is disabled The outp...

Page 171: ...bles interrupts generated by CLU3 falling edges synchronized with SYSCLK Value Name Description 0 DISABLE Interrupts will not be generated for CLU3 falling edge events 1 ENABLE Interrupts will be generated for CLU3 falling edge events 5 C2RIE 0 RW CLU2 Rising Edge Interrupt Enable See bit 7 description 4 C2FIE 0 RW CLU2 Falling Edge Interrupt Enable See bit 6 description 3 C1RIE 0 RW CLU1 Rising E...

Page 172: ... 0 RW CLU3 Falling Edge Flag Value Name Description 0 NOT_SET A CLU3 falling edge has not been detected since this flag was last cleared 1 SET A CLU3 falling edge synchronized with SYSCLK has occurred This bit must be cleared by firmware 5 C2RIF 0 RW CLU2 Rising Edge Flag See bit 7 description 4 C2FIF 0 RW CLU2 Falling Edge Flag See bit 6 description 3 C1RIF 0 RW CLU1 Rising Edge Flag See bit 7 de...

Page 173: ...R CLU1 Output State This bit represents the logic level of the CLU1 output synchronized with SYSCLK 0 C0OUT 0 R CLU0 Output State This bit represents the logic level of the CLU0 output synchronized with SYSCLK 14 4 5 CLU0MX Configurable Logic Unit 0 Multiplexer Bit 7 6 5 4 3 2 1 0 Name MXA MXB Access RW RW Reset 0x0 0x0 SFR Page 0x20 SFR Address 0x84 Bit Name Reset Access Description 7 4 MXA 0x0 R...

Page 174: ...or the CLU0 LUT The LUT is an 8 input multiplexer where the inputs are the bits of FNSEL The multiplex er selection signals are MS bit first MXA MXB Carry in Examples FNSEL 0xC0 implements MXA MXB FNSEL 0xE4 implements Carry MXA not Carry MXB The second example is a multiplexer where Carry is used to select MXA or MXB EFM8UB3 Reference Manual Configurable Logic Units CLU0 CLU1 CLU2 CLU3 silabs com...

Page 175: ...ronous output to the selected GPIO pin 5 4 Reserved Must write reset value 3 RST 0 RW CLU D flip flop Reset Writing this bit to 1 resets the D flip flop for CLU0 The bit will immediately return to 0 Value Name Description 1 RESET Reset the flip flop 2 CLKINV 0 RW CLU D flip flop Clock Invert Value Name Description 0 NORMAL Clock signal is not inverted 1 INVERT Clock signal will be inverted 1 0 CLK...

Page 176: ...Name FNSEL Access RW Reset 0x00 SFR Page 0x20 SFR Address 0xB9 Bit Name Reset Access Description 7 0 FNSEL 0x00 RW CLU Look Up Table function select Function select for the CLU1 LUT The LUT is an 8 input multiplexer where the inputs are the bits of FNSEL The multiplex er selection signals are MS bit first MXA MXB Carry in Examples FNSEL 0xC0 implements MXA MXB FNSEL 0xE4 implements Carry MXA not C...

Page 177: ...ronous output to the selected GPIO pin 5 4 Reserved Must write reset value 3 RST 0 RW CLU D flip flop Reset Writing this bit to 1 resets the D flip flop for CLU1 The bit will immediately return to 0 Value Name Description 1 RESET Reset the flip flop 2 CLKINV 0 RW CLU D flip flop Clock Invert Value Name Description 0 NORMAL Clock signal is not inverted 1 INVERT Clock signal will be inverted 1 0 CLK...

Page 178: ... Name FNSEL Access RW Reset 0x00 SFR Page 0x20 SFR Address 0xBC Bit Name Reset Access Description 7 0 FNSEL 0x00 RW CLU Look Up Table function select Function select for the CLU2 LUT The LUT is an 8 input multiplexer where the inputs are the bits of FNSEL The multiplex er selection signals are MS bit first MXA MXB Carry in Examples FNSEL 0xC0 implements MXA MXB FNSEL 0xE4 implements Carry MXA not ...

Page 179: ...ronous output to the selected GPIO pin 5 4 Reserved Must write reset value 3 RST 0 RW CLU D flip flop Reset Writing this bit to 1 resets the D flip flop for CLU2 The bit will immediately return to 0 Value Name Description 1 RESET Reset the flip flop 2 CLKINV 0 RW CLU D flip flop Clock Invert Value Name Description 0 NORMAL Clock signal is not inverted 1 INVERT Clock signal will be inverted 1 0 CLK...

Page 180: ... Name FNSEL Access RW Reset 0x00 SFR Page 0x20 SFR Address 0xC7 Bit Name Reset Access Description 7 0 FNSEL 0x00 RW CLU Look Up Table function select Function select for the CLU3 LUT The LUT is an 8 input multiplexer where the inputs are the bits of FNSEL The multiplex er selection signals are MS bit first MXA MXB Carry in Examples FNSEL 0xC0 implements MXA MXB FNSEL 0xE4 implements Carry MXA not ...

Page 181: ...ronous output to the selected GPIO pin 5 4 Reserved Must write reset value 3 RST 0 RW CLU D flip flop Reset Writing this bit to 1 resets the D flip flop for CLU3 The bit will immediately return to 0 Value Name Description 1 RESET Reset the flip flop 2 CLKINV 0 RW CLU D flip flop Clock Invert Value Name Description 0 NORMAL Clock signal is not inverted 1 INVERT Clock signal will be inverted 1 0 CLK...

Page 182: ... or 0xFFFF Automatic flash read control 8 8 8 8 8 Flash Memory CRC0FLIP 8 Figure 15 1 CRC Functional Block Diagram 15 2 Features The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols The CRC module supports the standard CCITT 16 16 bit polynomial 0x1021 and includes the following features Support for CCITT 16 polynomial Byte level bi...

Page 183: ...vidend for polynomial arithmetic binary arithmetic with no carries CRC_acc CRC_acc CRC_input 8 Divide the poly into the dividend using CRC XOR subtraction CRC_acc holds the remainder of each divide Only complete this division for 8 bits since input is 1 byte for i 0 i 8 i Check if the MSB is set if MSB is 1 then the POLY can divide into the dividend if CRC_acc 0x8000 0x8000 if so shift the CRC val...

Page 184: ... CRC calculation The CPU will not execute code any additional code until the CRC operation completes Note Upon initiation of an automatic CRC calculation the three cycles following a write to CRC0CN0 that initiate a CRC operation must only contain instructions which execute in the same number of cycles as the number of bytes in the instruction An example of such an instruction is a 3 byte MOV that...

Page 185: ...ame Description 0 ACCESS_LOWER CRC0DAT accesses bits 7 0 of the 16 bit CRC result 1 ACCESS_UPPER CRC0DAT accesses bits 15 8 of the 16 bit CRC result Upon initiation of an automatic CRC calculation the three cycles following a write to CRC0CN0 that initiate a CRC operation must only contain instructions which execute in the same number of cycles as the number of bytes in the instruction An example ...

Page 186: ...Name Reset Access Description 7 0 CRCST 0x00 RW Automatic CRC Calculation Starting Block These bits specify the flash block to start the automatic CRC calculation The starting address of the first flash block inclu ded in the automatic CRC calculation is CRCST x block_size where block_size is 256 bytes 15 4 5 CRC0CNT CRC0 Automatic Flash Sector Count Bit 7 6 5 4 3 2 1 0 Name CRCCNT Access RW Reset...

Page 187: ... 5 4 3 2 1 0 Name AUTOEN CRCDN Reserved Access RW R R Reset 0 1 0x00 SFR Page 0x0 0x20 SFR Address 0x86 Bit Name Reset Access Description 7 AUTOEN 0 RW Automatic CRC Calculation Enable When AUTOEN is set to 1 any write to CRC0CN0 will initiate an automatic CRC starting at flash sector CRCST and con tinuing for CRCCNT sectors 6 CRCDN 1 R Automatic CRC Calculation Complete Set to 0 when a CRC calcul...

Page 188: ...dge Triggered Capture Software Timer High Speed Output Frequency Output or Pulse Width Modulated PWM Output Each capture compare module has its own associated I O line CEXn which is routed through the crossbar to port I O when enabled Channel 2 Mode Control Capture Compare Channel 1 Mode Control Capture Compare PCA0 ECI CEX0 EXTCLK 8 L F Oscillator 8 Timer 0 Overflow SYSCLK SYSCLK 4 SYSCLK 12 Pola...

Page 189: ...he counter operation The CPS2 CPS0 bits in the PCA0MD register select the timebase for the counter timer When the counter timer overflows from 0xFFFF to 0x0000 the Counter Overflow Flag CF in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not auto...

Page 190: ...he ECCFn bit in a PCA0CPMn register enables the module s CCFn interrupt Table 16 2 PCA0CPM and PCA0PWM Bit Settings for PCA Capture Compare Modules Operational Mode PCA0CPMn PCA0PWM Bit Name PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF ARSEL ECOV COVF Reserved CLSEL Capture triggered by positive edge on CEXn X X 1 0 0 0 0 A 0 X B X X Capture triggered by negative edge on CEXn X X 0 1 0 0 0 A 0 X B X X Ca...

Page 191: ...used to select the type of transition that triggers the capture low to high transition positive edge high to low transition negative edge or either transition positive or negative edge When a capture occurs the Capture Compare Flag CCFn in PCA0CN0 is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardw...

Page 192: ...rrupt service routine and it must be cleared by software Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode Note When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 PCA0L PCA0CPLn PCA0H PCA0CPHn ECOMn Compare Enable PCA Clock ...

Page 193: ... software Setting the TOGn MATn and ECOMn bits in the PCA0CPMn register enables the High Speed Output mode If ECOMn is cleared the associated pin retains its state and not toggle on the next match event Note When writing a 16 bit value to the PCA0 Capture Compare registers the low byte should always be written first Writing to PCA0CPLn clears the ECOMn bit to 0 writing to PCA0CPHn sets ECOMn to 1 ...

Page 194: ...for the channel will be set when the 16 bit PCA0 counter and the 16 bit capture compare register for the channel are equal PCA0L ECOMn Compare Enable PCA Clock 8 bit Comparator match Toggle TOGn Toggle Enable CEXn 8 bit Adder Adder Enable PCA0CPLn PCA0CPHn Figure 16 5 PCA Frequency Output Mode 16 3 8 PWM Waveform Generation The PCA can generate edge or center aligned PWM waveforms with resolutions...

Page 195: ... and CEX1POL bits are cleared to 0 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 Counter PCA0 0x0002 Capture Compare PCA0CP0 Output CEX0 PCA Clock match edge overflow edge 0x0005 Capture Compare PCA0CP1 Output CEX1 match edge Figure 16 6 Edge Aligned PWM Timing For a given PCA resolution the unused high bits in the PCA0 counter and the PCA0CPn compare registers are ignored and only the used bit...

Page 196: ...Cycle PCA0CPn 2N Figure 16 8 N bit Edge Aligned PWM Duty Cycle With CEXnPOL 1 N PWM resolution EFM8UB3 Reference Manual Programmable Counter Array PCA0 silabs com Building a more connected world Rev 0 2 196 ...

Page 197: ... occurs when bits 9 0 of the PCA0CPn register are one less than bits 9 0 of the PCA0 counter and bit 10 of the PCA0 counter is 0 An example of the PWM timing in center aligned mode for two channels is shown here In this example the CEX0POL and CEX1POL bits are cleared to 0 0xFB 0xFC 0xFD 0xFE 0xFF 0x00 0x01 0x02 0x03 0x04 Counter PCA0L 0x01 Capture Compare PCA0CPL0 Output CEX0 PCA Clock down edge ...

Page 198: ...h time a match edge or up edge occurs The COVF flag in PCA0PWM can be used to detect the overflow falling edge which occurs every 256 PCA clock cycles 9 to 11 bit Pulse Width Modulator Mode In 9 to 11 bit PWM mode the duty cycle is determined by the value of the least significant N bits of the PCA0CPn register where N is the selected PWM resolution To adjust the duty cycle PCA0CPn should not norma...

Page 199: ...r For a varying duty cycle the match interrupt flag should be enabled ECCFn 1 AND MATn 1 to help synchronize the capture compare register writes If the MATn bit is set to 1 the CCFn flag for the module is set each time a match edge or up edge occurs The CF flag in PCA0CN0 can be used to detect the overflow or down edge Important When writing a 16 bit value to the PCA0 Capture Compare registers the...

Page 200: ... Comparator 0 output is used to clear CEXn as follows when CPCPOL 0 CEXn is cleared on the falling edge of the Comparator0 output CEXn CPCEn 0 CEXn CPCEn 1 Comparator0 Output CPCPOL 0 Figure 16 12 CEXn with CPCEn 1 CPCPOL 0 When CPCPOL 1 CEXn is cleared on the rising edge of the Comparator0 output CEXn CPCEn 0 CEXn CPCEn 1 Comparator0 Output CPCPOL 1 Figure 16 13 CEXn with CPCEn 1 CPCPOL 1 In the ...

Page 201: ...ng 5 3 Reserved Must write reset value 2 CCF2 0 RW PCA Module 2 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF2 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 1 CCF1 0 RW PCA Module 1 Capture Compare Flag This bit is se...

Page 202: ...he PCA counter Value Name Description 0x0 SYSCLK_DIV_12 System clock divided by 12 0x1 SYSCLK_DIV_4 System clock divided by 4 0x2 T0_OVERFLOW Timer 0 overflow 0x3 ECI High to low transitions on ECI max rate system clock divided by 4 0x4 SYSCLK System clock 0x5 EXTOSC_DIV_8 External clock divided by 8 synchronized with the system clock 0x6 LFOSC_DIV_8 Low frequency oscillator divided by 8 0 ECF 0 R...

Page 203: ...erate PCA interrupts 1 COVF_MASK_ENA BLED A PCA interrupt will be generated when COVF is set 5 COVF 0 RW Cycle Overflow Flag This bit indicates an overflow of the 8th to 11th bit of the main PCA counter PCA0 The specific bit used for this flag de pends on the setting of the Cycle Length Select bits The bit can be set by hardware or firmware but must be cleared by firmware Value Name Description 0 ...

Page 204: ...MP0 Use Comparator 0 for the comparator clear function 1 CMP1 Use Comparator 1 for the comparator clear function 5 3 Reserved Must write reset value 2 CPCE2 0 RW Comparator Clear Enable for CEX2 Enables the comparator clear function on PCA channel 2 1 CPCE1 0 RW Comparator Clear Enable for CEX1 Enables the comparator clear function on PCA channel 1 0 CPCE0 0 RW Comparator Clear Enable for CEX0 Ena...

Page 205: ...write reset value 2 CEX2POL 0 RW CEX2 Output Polarity Selects the polarity of the CEX2 output channel When this bit is modified the change takes effect at the pin immediately Value Name Description 0 DEFAULT Use default polarity 1 INVERT Invert polarity 1 CEX1POL 0 RW CEX1 Output Polarity Selects the polarity of the CEX1 output channel When this bit is modified the change takes effect at the pin i...

Page 206: ...e aligned 1 CENTER Center aligned 1 CEX1CEN 0 RW CEX1 Center Alignment Enable Selects the alignment properties of the CEX1 output channel when operated in any of the PWM modes This bit does not affect the operation of non PWM modes Value Name Description 0 EDGE Edge aligned 1 CENTER Center aligned 0 CEX0CEN 0 RW CEX0 Center Alignment Enable Selects the alignment properties of the CEX0 output chann...

Page 207: ...ith a module s capture compare register cause the CCF0 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 0 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX0 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW ...

Page 208: ...ter will clear the module s ECOM bit to a 0 16 4 11 PCA0CPH0 PCA Channel 0 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH0 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xFC Bit Name Reset Access Description 7 0 PCA0CPH0 0x00 RW PCA Channel 0 Capture Module High Byte The PCA0CPH0 register holds the high byte MSB of the 16 bit capture module This register address also allows access ...

Page 209: ...ith a module s capture compare register cause the CCF1 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 1 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX1 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW ...

Page 210: ...ter will clear the module s ECOM bit to a 0 16 4 14 PCA0CPH1 PCA Channel 1 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH1 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xEA Bit Name Reset Access Description 7 0 PCA0CPH1 0x00 RW PCA Channel 1 Capture Module High Byte The PCA0CPH1 register holds the high byte MSB of the 16 bit capture module This register address also allows access ...

Page 211: ...ith a module s capture compare register cause the CCF2 bit in the PCA0MD register to be set to logic 1 2 TOG 0 RW Channel 2 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX2 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW ...

Page 212: ...ter will clear the module s ECOM bit to a 0 16 4 17 PCA0CPH2 PCA Channel 2 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCA0CPH2 Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xEC Bit Name Reset Access Description 7 0 PCA0CPH2 0x00 RW PCA Channel 2 Capture Module High Byte The PCA0CPH2 register holds the high byte MSB of the 16 bit capture module This register address also allows access ...

Page 213: ...ins required Additional general purpose port I O pins can be used to select multiple slave devices in master mode SPI0 Shift Register MISO MOSI Clock Rate Generator SYSCLK Bus Control Master or Slave SCK Polarity SCK Phase NSS Control SCK NSS SPI0DAT TX Buffer 2 bytes RX Buffer 2 bytes FIFO Control Interrupt Selection Figure 17 1 SPI Block Diagram 17 2 Features Supports 3 or 4 wire master or slave...

Page 214: ...nction of the slave select NSS signal is dependent on the setting of the NSSMD bitfield There are three possible modes that can be selected with these bits NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode The SPI operates in 3 wire mode and NSS is disabled When operating as a slave device the SPI is always selected in 3 wire mode Since no select signal is present the SPI must be the only slave on t...

Page 215: ...er mode the MSTEN bit should be set to 1 Writing a byte of data to the SPInDAT register writes to the trans mit buffer If the SPI shift register is empty a byte is moved from the transmit buffer into the shift register and a bi directional data transfer begins The SPI module provides the serial clock on SCK while simultaneously shifting data out of the shift register MSB first on MOSI and into the...

Page 216: ...gured as a slave SPI0 can be configured for 4 wire or 3 wire operation In the default 4 wire slave mode the NSS signal is routed to a port pin and configured as a digital input The SPI interface is enabled when NSS is logic 0 and disabled when NSS is logic 1 The internal shift register bit counter is reset on a falling edge of NSS When operated in 3 wire slave mode NSS is not mapped to an external...

Page 217: ...anging the clock phase or polarity Note that CKPHA should be set to 0 on both the master and slave SPI when communicating between two Silicon Labs devices SCK CKPOL 0 CKPHA 0 SCK CKPOL 0 CKPHA 1 SCK CKPOL 1 CKPHA 0 SCK CKPOL 1 CKPHA 1 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MOSI Figure 17 5 Master Mode Data Clock Timing MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO NSS 4 Wire Mode ...

Page 218: ...ag to generate an interrupt or poll SPIF until it is set to 1 3 Read the received data from SPInDAT 4 Clear the SPIF flag to 0 5 Repeat the sequence for any additional transfers Slave Transfers As a SPI slave the transfers are initiated by an external master device driving the bus Slave firmware may anticipate any output data needs by pre loading the SPInDAT register before the master begins the t...

Page 219: ...e will set the TFRQ flag to 1 The receive threshold RXTH is continually compared with RXCNT If RXCNT is greater than RXTH hardware will set the RFRQ flag to 1 The thresholds can be used in interrupt based systems to specify when the associated interrupt occurs Both the RFRQ and TFRQ flags may be individually enabled to generate an SPI interrupt using the RFRQE and TFRQE bits respecitvely In most a...

Page 220: ...ster and is equivalent to SPInCKR x 32 system clock cycles SYSCLKs The internal timeout counter will run when at least one byte has been received in the receive FIFO but the RFRQ flag is not set the RXTH threshold has not been crossed The counter is reloaded from the SPInCKR register under any of the following conditions The receive buffer is read by firmware The RFRQ flag is set A valid SCK occur...

Page 221: ...y for CKPOL 1 T MIH Figure 17 8 SPI Master Timing CKPHA 0 SCK T MCKH T MCKL MISO T MIH MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T MIS Figure 17 9 SPI Master Timing CKPHA 1 EFM8UB3 Reference Manual Serial Peripheral Interface SPI0 silabs com Building a more connected world Rev 0 2 221 ...

Page 222: ... T SDZ Figure 17 10 SPI Slave Timing CKPHA 0 SCK T SE NSS T CKH T CKL MOSI T SIS T SIH MISO T SD T SOH SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 T SEZ T SDZ Figure 17 11 SPI Slave Timing CKPHA 1 EFM8UB3 Reference Manual Serial Peripheral Interface SPI0 silabs com Building a more connected world Rev 0 2 222 ...

Page 223: ... SCK Edge 5 ns TSD Last SCK Edge to NSS Rising 5 ns TSEZ NSS Falling to MISO Valid 20 ns TSDZ NSS Rising to MISO High Z 20 ns TCKH SCK High Time 40 ns TCKL SCK Low Time 40 ns TSIS MOSI Valid to SCK Sample Edge 20 ns TSIH SCK Sample Edge to MOSI Change 5 ns TSOH SCK Shift Edge to MISO Change 20 ns Note 1 TSYSCLK is equal to one period of the device system clock SYSCLK EFM8UB3 Reference Manual Seria...

Page 224: ...d Flag This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched ver sion of the pin input 2 NSSIN 1 R NSS Instantaneous Pin Input This bit mimics the instantaneous value that is present on the NSS port pin at the...

Page 225: ...cess Description Value Name Description 0 NOT_EMPTY The RX FIFO contains data 1 EMPTY The RX FIFO is empty EFM8UB3 Reference Manual Serial Peripheral Interface SPI0 silabs com Building a more connected world Rev 0 2 225 ...

Page 226: ...leared by firmware 4 RXOVRN 0 RW Receive Overrun Flag This bit is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 3 2 NSSMD ...

Page 227: ...YSCLK is the system clock frequency and SPI0CKR is the 8 bit value held in the SPI0CKR register fsck SYSCLK 2 SPI0CKR 1 for 0 SPI0CKR 255 17 4 4 SPI0DAT SPI0 Data Bit 7 6 5 4 3 2 1 0 Name SPI0DAT Access RW Reset 0x00 SFR Page 0x0 0x20 SFR Address 0xA3 Bit Name Reset Access Description 7 0 SPI0DAT 0x00 RW SPI0 Transmit and Receive Data The SPI0DAT register is used to transmit and receive SPI0 data ...

Page 228: ...Name Description 0x0 ZERO TFRQ will be set when the TX FIFO is empty 0x1 ONE TFRQ will be set when the TX FIFO contains one or fewer bytes 3 RFRQE 0 RW Read Request Interrupt Enable When set to 1 a SPI0 interrupt will be generated any time RFRQ is logic 1 Value Name Description 0 DISABLED SPI0 interrupts will not be generated when RFRQ is set 1 ENABLED SPI0 interrupts will be generated if RFRQ is ...

Page 229: ...leared When set the SPI will complete any byte transmission in progress but any new transfers will be 0xFF and not pull data from the TX FIFO Bytes will continue to be pulled from the TX FIFO when the TXHOLD bit is cleared Value Name Description 0 CONTINUE The UART will continue to transmit any available data in the TX FIFO 1 HOLD The UART will not transmit any new data from the TX FIFO 4 SPIFEN 1...

Page 230: ...hen enabled any received bytes will be placed into the RX FIFO Value Name Description 0 DISABLED Received bytes will be discarded 1 ENABLED Received bytes will be placed in the RX FIFO 17 4 7 SPI0FCT SPI0 FIFO Count Bit 7 6 5 4 3 2 1 0 Name Reserved TXCNT Reserved RXCNT Access R R R R Reset 0x0 0x0 0x0 0x0 SFR Page 0x20 SFR Address 0xF7 Bit Name Reset Access Description 7 6 Reserved Must write res...

Page 231: ...Master MISO Input Select Value Name Description 0x0 CROSSBAR The crossbar input is the MISO input master mode 0x1 CLU0 The CLU0 synchronous output is the MISO input master mode 0x2 CLU2 The CLU2 synchronous output is the MISO input master mode 0x3 CLU3 The CLU3 synchronous output is the MISO input master mode 2 Reserved Must write reset value 1 0 SISEL 0x0 RW Slave MOSI Input Select This field sel...

Page 232: ...chronization and arbitration for multi master mode Clock low extending clock stretching to interface with faster masters Hardware support for 7 bit slave and general call address recognition Firmware support for 10 bit slave address decoding Ability to inhibit all slave states Programmable data setup hold times Transmit and receive FIFOs two byte to help increase throughput in faster applications ...

Page 233: ...winning the arbitration It is not necessary to specify one device as the Master in a system any device who transmits a START and a slave address becomes the master for the duration of that transfer A typical SMBus transaction consists of a START condition followed by an address byte Bits7 1 7 bit slave address Bit0 R W direc tion bit one or more bytes of data and a STOP condition Bytes that are re...

Page 234: ...ow extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency SCL Low Timeout If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master cannot force the SCL line...

Page 235: ...is transferred When hardware acknowledgement is disabled the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver When a trans mitter i e sending address data receiving an ACK this interrupt is generated after the ACK cycle so that software may read the re ceived ACK value when receiving data i e receiving address data sending an ACK...

Page 236: ...um setup and hold times for the SDA line The minimum SDA setup time defines the abso lute minimum time that SDA is stable before SCL transitions from low to high The minimum SDA hold time defines the absolute mini mum time that the current SDA value remains stable after SCL transitions from high to low EXTHOLD should be set so that the mini mum setup and hold times meet the SMBus Specification req...

Page 237: ...TXMODE indicates whether the device is transmitting or receiving data for the current byte STA and STO indicate that a START and or STOP has been detected or generated since the last SMBus interrupt STA and STO are also used to generate START and STOP conditions when operating as a master Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becom...

Page 238: ... not written before the start of an SMBus frame STA A START followed by an address byte is re ceived Must be cleared by software STO A STOP is detected while addressed as a slave Arbitration is lost due to a detected STOP A pending STOP is generated ACKRQ A byte has been received and an ACK re sponse value is needed only when hard ware ACK is not enabled After each ACK cycle ARBLOST A repeated STA...

Page 239: ...recommended for applications to use hardware ACK and address recognition In some cases it may be desirable to drive ACK generation and address recognition from firmware When the EHACK bit in register SMB0ADM is cleared to 0 the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes As a receiver writing the ACK bit defines the outgoing...

Page 240: ...erates a STOP An SMBus inter rupt is generated at the end of all SMBus byte frames The position of the ACK interrupt when operating as a receiver depends on whether hardware ACK generation is enabled As a receiver the interrupt for an ACK occurs before the ACK with hardware ACK gener ation disabled and after the ACK when hardware ACK generation is enabled As a transmitter interrupts occur after th...

Page 241: ...wing a Master Transmitter interrupt Figure 18 5 Typical Master Write Sequence on page 241 shows a typical master write sequence as it appears on the bus and Figure 18 6 Master Write Sequence State Diagram EHACK 1 on page 242 shows the corresponding firmware state machine Two transmit data bytes are shown though any number of bytes may be transmitted Notice that all of the data byte transferred int...

Page 242: ... Yes No ACK received 1 Write next data to SMB0DAT 2 Clear the interrupt flag SI Interrupt Send Repeated Start Yes 1 Set the STO flag 2 Clear the interrupt flag SI No 1 Set the STA flag 2 Clear the interrupt flag SI Idle Interrupt b c d Figure 18 6 Master Write Sequence State Diagram EHACK 1 EFM8UB3 Reference Manual System Management Bus I2C SMB0 silabs com Building a more connected world Rev 0 2 2...

Page 243: ...generates a NACK Software should write a 0 to the ACK bit for the last data transfer to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver Figure 18 7 Typical Master Read Se quence on page 243 shows a typical master read sequence as it ap...

Page 244: ...ag SI Send Repeated Start Yes 1 Set the STO flag 2 Clear the interrupt flag SI No 1 Set the STA flag 2 Clear the interrupt flag SI Idle Interrupt 1 Clear ACK 2 Clear SI Next Byte Final 1 Set ACK 2 Clear SI Yes No Interrupt No Yes Set the STA bit Idle b c d Figure 18 8 Master Read Sequence State Diagram EHACK 1 EFM8UB3 Reference Manual System Management Bus I2C SMB0 silabs com Building a more conne...

Page 245: ...bled the SMBus hardware will automatically generate the ACK NACK and then post the interrupt It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled The interface exits Slave Receiver Mode after receiving a STOP The interface will switch to Slave Transmitter Mode if SMB0DAT is written while ...

Page 246: ... Yes No Clear SI Interrupt Clear STO Repeated Start Yes Idle No 1 Set ACK 2 Clear SI Clear SI 1 Read Data From SMB0DAT 2 Clear SI Interrupt STOP No Interrupt Yes a e b d f g c h e d h Figure 18 10 Slave State Diagram EHACK 1 EFM8UB3 Reference Manual System Management Bus I2C SMB0 silabs com Building a more connected world Rev 0 2 246 ...

Page 247: ...a After each byte is transmitted the master sends an acknowledge bit if the acknowledge bit is an ACK SMB0DAT should be writ ten with the next data byte If the acknowledge bit is a NACK SMB0DAT should not be written to before SI is cleared an error condition may be generated if SMB0DAT is written following a received NACK while in slave transmitter mode The interface exits slave trans mitter mode ...

Page 248: ...the number of SYSCLKs to extend the setup and hold times 3 SMBTOE 0 RW SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is configured to Split Mode only the High Byte of the timer is held in reload while SCL is high Timer 3 should be programme...

Page 249: ... SYSCLKs 3 2 Reserved Must write reset value 1 0 SDD 0x0 RW SMBus Start Detection Window This field is used to delay the recognition of the falling edge of the SDA signal This feature should be applied in cases where a data bit transition occurs close to the SCL falling edge that may cause a false START detection when there is a significant mismatch between the impedance or capacitance on the SDA ...

Page 250: ...Transmitter Mode 5 STA 0 RW SMBus Start Flag When reading STA a 1 indicates that a start or repeated start condition was detected on the bus Writing a 1 to the STA bit initiates a start or repeated start on the bus 4 STO 0 RW SMBus Stop Flag When reading STO a 1 indicates that a stop condition was detected on the bus in slave mode or is pending in master mode When acting as a master writing a 1 to...

Page 251: ...ring SI initiates the next SMBus state machine operation 18 4 4 SMB0ADR SMBus 0 Slave Address Bit 7 6 5 4 3 2 1 0 Name SLV GC Access RW RW Reset 0x00 0 SFR Page 0x0 0x20 SFR Address 0xD7 Bit Name Reset Access Description 7 1 SLV 0x00 RW SMBus Hardware Slave Address Defines the SMBus Slave Address es for automatic hardware acknowledgement Only address bits which have a 1 in the corresponding bit po...

Page 252: ... 0 ADR_ACK_MANUAL Firmware must manually acknowledge all incoming address and data bytes 1 ADR_ACK_AUTOMAT IC Automatic slave address recognition and hardware acknowledge is en abled 18 4 6 SMB0DAT SMBus 0 Data Bit 7 6 5 4 3 2 1 0 Name SMB0DAT Access RW Reset Varies SFR Page 0x0 0x20 SFR Address 0xC2 Bit Name Reset Access Description 7 0 SMB0DAT Varies RW SMBus 0 Data The SMB0DAT register is used ...

Page 253: ... bytes in the TX FIFO is equal to or less than the value in TXTH Value Name Description 0x0 ZERO TFRQ will be set when the TX FIFO is empty 3 RFRQE 0 RW Read Request Interrupt Enable When set to 1 an SMBus 0 interrupt will be generated any time RFRQ is logic 1 Value Name Description 0 DISABLED SMBus 0 interrupts will not be generated when RFRQ is set 1 ENABLED SMBus 0 interrupts will be generated ...

Page 254: ...0 it will replace the most recent byte in the FIFO Value Name Description 0 FULL The TX FIFO is full 1 NOT_FULL The TX FIFO has room for more data 5 4 Reserved Must write reset value 3 RFRQ 0 R Receive FIFO Request Set to 1 by hardware when the number of bytes in the RX FIFO is larger than specified by the RX FIFO threshold RXTH Value Name Description 0 NOT_SET The number of bytes in the RX FIFO i...

Page 255: ... 0 Slave Receiver When RXLN is cleared to 0 the bus will stall and generate an interrupt after every received byte regard less of the FIFO status Any other value programmed here will allow the FIFO to operate RXLN is not decremented as new bytes arrive in slave receiver mode This register should not be modified by firmware in the middle of a transfer except when SI 1 and the bus is stalled 18 4 10...

Page 256: ...incremented on each high to low transition at the selected input pin T0 or T1 Events with a frequency of up to one fourth the system clock frequency can be counted The input signal need not be periodic but it must be held at a given level for at least two full system clock cycles to ensure the level is properly sampled Table 19 1 Timer Modes Timer 0 and Timer 1 Modes Timer 2 and 5 Modes Timer 3 an...

Page 257: ...Capture SMBus 0 Clock Rate Master Yes Yes Yes Yes SMBus 0 SCL Low Timeout Yes PCA0 Clock Yes ADC0 Conver sion Start Yes Yes1 Yes1 Yes1 Yes1 Yes1 Yes1 Yes1 Yes1 T2 Input Cap ture Pin Yes Yes Yes Yes LFOSC0 Cap ture Yes Yes Yes Yes Comparator 0 Output Capture Yes Yes Yes Yes USB Start of Frame Capture Yes Yes Yes Yes CLU Input CLU Clock CLU0A CLU1ALTCLK0 CLU3ALTCLK1 CLU1A CLU2ALTCLK0 CLU0ALTCLK1 CLU...

Page 258: ...s can be enabled by setting the ET0 bit in the IE register Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register Both counter timers operate in one of four primary modes selected by setting the Mode Select bits T1M1 T0M0 in the Counter Timer Mode register TMOD Each timer can be configured independently for the supported operating modes EFM8UB3 Reference Manual Timers Timer0 T...

Page 259: ...cycles to ensure the level is properly sampled Clearing CT selects the clock defined by the T0M bit in register CKCON0 When T0M is set Timer 0 is clocked by the system clock When T0M is cleared Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON0 Setting the TR0 bit enables the timer when either GATE0 in the TMOD register is logic 0 or based on the input signal INT0 The IN0P...

Page 260: ...e same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and configured in Mode 1 in the same manner as for Mode 0 The overflow rate for Timer 0 in 16 bit mode is FTIMER0 FInput Clock 216 TH0 TL0 FInput Clock 65536 TH0 TL0 EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 Timer4 and Timer5 silabs com Building a more connected world Rev 0 2 2...

Page 261: ...e timer for the first count to be correct When in Mode 2 Timer 1 operates identically to Timer 0 The overflow rate for Timer 0 in 8 bit auto reload mode is FTIMER0 FInput Clock 28 TH0 FInput Clock 256 TH0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TR0 bit enables the timer when either GATE0 in the TMOD register is logic 0 or when the input sig...

Page 262: ... clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode settings To run Timer 1 while Timer 0 is in Mode 3 set the Timer 1 Mode as 0 1 or 2 To disable Timer 1 configure it f...

Page 263: ... both the Suspend and Snooze power modes Timer 4 includes Timer 3 overflows as a clock source allowing the two to be chained together for longer sleep intervals When operating in one of the 16 bit modes the low side timer clock is used to clock the entire 16 bit timer To Timer Low Clock Input Timer Clock Selection SYSCLK TnXCLK TnML TnMH To Timer High Clock Input for split mode SYSCLK 12 External ...

Page 264: ...the low frequency oscillator clock comparator 0 USB start of frame SOF events or CLUn outputs The capture input signal for the timer is selected using the TnCSEL field in the TMRnCN1 register Capture Source Selection USB Start of Frame Comparator 0 Output TnCSEL T2 Pin via Crossbar LFOSC0 To Timer n Capture Input CLU0 1 2 or 3 Output Figure 19 5 Timer 2 3 4 and 5 Capture Source Selection EFM8UB3 R...

Page 265: ...rupts are enabled an interrupt is generated on each timer overflow Additionally if the timer interrupts are enabled and the TFnLEN bit is set an interrupt is generated each time the lower 8 bits TMRnL overflow from 0xFF to 0x00 The overflow rate of the timer in split 16 bit auto reload mode is FTIMERn FInput Clock 216 TMRnRLH TMRnRLL FInput Clock 65536 TMRnRLH TMRnRLL TMRnL TMRnH Reload Interrupt ...

Page 266: ... mode is FTIMERn High FInput Clock 28 TMRnRLH FInput Clock 256 TMRnRLH The TFnH bit is set when TMRnH overflows from 0xFF to 0x00 the TFnL bit is set when TMRnL overflows from 0xFF to 0x00 When timer interrupts are enabled an interrupt is generated each time TMRnH overflows If timer interrupts are enabled and TFnLEN is set an interrupt is generated each time either TMRnL or TMRnH overflows When TF...

Page 267: ... counter option This is accomplished by configuring Timer 4 s T4XCLK field to clock from Timer 3 overflows The primary use of this mode is to wake the device from long term Suspend or Snooze operations but it may also be used effectively as a 32 bit capture source It is important to note the relationship between the two timers when they are chained together in this manner The timer 3 overflow rate...

Page 268: ...uses the system clock 5 T2MH 0 RW Timer 2 High Byte Clock Select Selects the clock supplied to the Timer 2 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 2 high byte uses the clock defined by T2XCLK in TMR2CN0 1 SYSCLK Timer 2 high byte uses the system clock 4 T2ML 0 RW Timer 2 Low Byte Clock Select Selects the clock supplied to Timer 2 If Timer 2 is configured...

Page 269: ...he system clock 1 0 SCA 0x0 RW Timer 0 1 Prescale These bits control the Timer 0 1 Clock Prescaler Value Name Description 0x0 SYSCLK_DIV_12 System clock divided by 12 0x1 SYSCLK_DIV_4 System clock divided by 4 0x2 SYSCLK_DIV_48 System clock divided by 48 0x3 EXTOSC_DIV_8 External oscillator divided by 8 synchronized with the system clock EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 ...

Page 270: ...lue Name Description 0 EXTERNAL_CLOCK Timer 5 low byte uses the clock defined by T5XCLK in TMR5CN0 1 SYSCLK Timer 5 low byte uses the system clock 1 T4MH 0 RW Timer 4 High Byte Clock Select Selects the clock supplied to the Timer 4 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 4 high byte uses the clock defined by T4XCLK in TMR4CN0 1 SYSCLK Timer 4 high byte u...

Page 271: ...can be cleared by firmware but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge triggered mode 2 IT1 0 RW Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in register IT01CF Value Name Description 0 LEVEL INT1 is level triggered 1 EDG...

Page 272: ... T1M 0x0 RW Timer 1 Mode Select These bits select the Timer 1 operation mode Value Name Description 0x0 MODE0 Mode 0 13 bit Counter Timer 0x1 MODE1 Mode 1 16 bit Counter Timer 0x2 MODE2 Mode 2 8 bit Counter Timer with Auto Reload 0x3 MODE3 Mode 3 Timer 1 Inactive 3 GATE0 0 RW Timer 0 Gate Control Value Name Description 0 DISABLED Timer 0 enabled when TR0 1 irrespective of INT0 logic level 1 ENABLE...

Page 273: ... 2 1 0 Name TL0 Access RW Reset 0x00 SFR Page ALL SFR Address 0x8A Bit Name Reset Access Description 7 0 TL0 0x00 RW Timer 0 Low Byte The TL0 register is the low byte of the 16 bit Timer 0 19 4 6 TL1 Timer 1 Low Byte Bit 7 6 5 4 3 2 1 0 Name TL1 Access RW Reset 0x00 SFR Page ALL SFR Address 0x8B Bit Name Reset Access Description 7 0 TL1 0x00 RW Timer 1 Low Byte The TL1 register is the low byte of ...

Page 274: ...he high byte of the 16 bit Timer 0 19 4 8 TH1 Timer 1 High Byte Bit 7 6 5 4 3 2 1 0 Name TH1 Access RW Reset 0x00 SFR Page ALL SFR Address 0x8D Bit Name Reset Access Description 7 0 TH1 0x00 RW Timer 1 High Byte The TH1 register is the high byte of the 16 bit Timer 1 EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 Timer4 and Timer5 silabs com Building a more connected world Rev 0 2 274...

Page 275: ...If TF2CEN is set and Timer 2 interrupts are enabled an interrupt will be generated according to the capture source selected by the T2CSEL bits and the current 16 bit timer value in TMR2H TMR2L will be copied to TMR2RLH TMR2RLL 3 T2SPLIT 0 RW Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with auto reload Value Name Description 0 16_BIT_RELOAD Timer 2 operates i...

Page 276: ... Bit Name Reset Access Description 7 0 TMR2RLH 0x00 RW Timer 2 Reload High Byte When operating in one of the auto reload modes TMR2RLH holds the reload value for the high byte of Timer 2 TMR2H When operating in capture mode TMR2RLH is the captured value of TMR2H 19 4 12 TMR2L Timer 2 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR2L Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0xCC Bit Name Reset Acce...

Page 277: ...set Access Description 7 0 TMR2H 0x00 RW Timer 2 High Byte In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the 8 bit high byte timer value EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 Timer4 and Timer5 silabs com Building a more connected world Rev 0 2 277 ...

Page 278: ... 3 Reserved Must write reset value 2 0 T2CSEL 0x0 RW Timer 2 Capture Select When used in capture mode the T2CSEL field selects the input capture signal Value Name Description 0x0 PIN Capture high to low transitions on the T2 input pin 0x1 LFOSC Capture high to low transitions of the LFO oscillator 0x2 COMPARATOR0 Capture high to low transitions of the Comparator 0 output 0x3 USB_SOF Capture USB st...

Page 279: ...terrupt will be generated according to the capture source selected by the T3CSEL bits and the current 16 bit timer value in TMR3H TMR3L will be copied to TMR3RLH TMR3RLL 3 T3SPLIT 0 RW Timer 3 Split Mode Enable When this bit is set Timer 3 operates as two 8 bit timers with auto reload Value Name Description 0 16_BIT_RELOAD Timer 3 operates in 16 bit auto reload mode 1 8_BIT_RELOAD Timer 3 operates...

Page 280: ... Bit Name Reset Access Description 7 0 TMR3RLH 0x00 RW Timer 3 Reload High Byte When operating in one of the auto reload modes TMR3RLH holds the reload value for the high byte of Timer 3 TMR3H When operating in capture mode TMR3RLH is the captured value of TMR3H 19 4 18 TMR3L Timer 3 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR3L Access RW Reset 0x00 SFR Page 0x0 0x10 SFR Address 0x94 Bit Name Reset Acce...

Page 281: ...set Access Description 7 0 TMR3H 0x00 RW Timer 3 High Byte In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer 3 In 8 bit mode TMR3H contains the 8 bit high byte timer value EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 Timer4 and Timer5 silabs com Building a more connected world Rev 0 2 281 ...

Page 282: ...o indicate when it is safe to read and write the registers associated with the suspend wake up timer If a suspend wake up source other than the timer has brought the oscillator out of suspend mode it may take up to three timer clocks before the timer can be read or written Value Name Description 0 NOT_SET It is safe to read and write the timer registers 1 SET Reads and writes of the timer register...

Page 283: ...n the configurable logic unit 2 synchro nous output 0x7 CLU3_OUT Capture high to low transitions on the configurable logic unit 3 synchro nous output EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 Timer4 and Timer5 silabs com Building a more connected world Rev 0 2 283 ...

Page 284: ...rated according to the capture source selected by the T4CSEL bits and the current 16 bit timer value in TMR4H TMR4L will be copied to TMR4RLH TMR4RLL 3 T4SPLIT 0 RW Timer 4 Split Mode Enable When this bit is set Timer 4 operates as two 8 bit timers with auto reload Value Name Description 0 16_BIT_RELOAD Timer 4 operates in 16 bit auto reload mode 1 8_BIT_RELOAD Timer 4 operates as two 8 bit auto r...

Page 285: ...it Name Reset Access Description 7 0 TMR4RLH 0x00 RW Timer 4 Reload High Byte When operating in one of the auto reload modes TMR4RLH holds the reload value for the high byte of Timer 4 TMR4H When operating in capture mode TMR4RLH is the captured value of TMR4H 19 4 24 TMR4L Timer 4 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR4L Access RW Reset 0x00 SFR Page 0x10 SFR Address 0xA4 Bit Name Reset Access Des...

Page 286: ...t Access Description 7 0 TMR4H 0x00 RW Timer 4 High Byte In 16 bit mode the TMR4H register contains the high byte of the 16 bit Timer 4 In 8 bit mode TMR4H contains the 8 bit high byte timer value EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 Timer4 and Timer5 silabs com Building a more connected world Rev 0 2 286 ...

Page 287: ...urce other than the timer has brought the oscillator out of suspend mode it may take up to three timer clocks before the timer can be read or written Value Name Description 0 NOT_SET It is safe to read and write the timer registers 1 SET Reads and writes of the timer register should not be performed 3 Reserved Must write reset value 2 0 T4CSEL 0x1 RW Timer 4 Capture Select When used in capture mod...

Page 288: ...Name TMR5RLH Access RW Reset 0x00 SFR Page 0x10 SFR Address 0xD3 Bit Name Reset Access Description 7 0 TMR5RLH 0x00 RW Timer 5 Reload High Byte When operating in one of the auto reload modes TMR5RLH holds the reload value for the high byte of Timer 5 TMR5H When operating in capture mode TMR5RLH is the captured value of TMR5H 19 4 29 TMR5L Timer 5 Low Byte Bit 7 6 5 4 3 2 1 0 Name TMR5L Access RW R...

Page 289: ...t Access Description 7 0 TMR5H 0x00 RW Timer 5 High Byte In 16 bit mode the TMR5H register contains the high byte of the 16 bit Timer 5 In 8 bit mode TMR5H contains the 8 bit high byte timer value EFM8UB3 Reference Manual Timers Timer0 Timer1 Timer2 Timer3 Timer4 and Timer5 silabs com Building a more connected world Rev 0 2 289 ...

Page 290: ...Timer 5 interrupts are enabled an interrupt will be generated according to the capture source selected by the T5CSEL bits and the current 16 bit timer value in TMR5H TMR5L will be copied to TMR5RLH TMR5RLL 3 T5SPLIT 0 RW Timer 5 Split Mode Enable When this bit is set Timer 5 operates as two 8 bit timers with auto reload Value Name Description 0 16_BIT_RELOAD Timer 5 operates in 16 bit auto reload ...

Page 291: ...set value 2 0 T5CSEL 0x0 RW Timer 5 Capture Select When used in capture mode the T5CSEL field selects the input capture signal Value Name Description 0x0 PIN Capture high to low transitions on the T2 input pin 0x1 LFOSC Capture high to low transitions of the LFO oscillator 0x2 COMPARATOR0 Capture high to low transitions of the Comparator 0 output 0x3 USB_SOF Capture USB start of frame SOF events 0...

Page 292: ...X extra bit RBX extra bit Control Configuration Interrupt Generation TX Clk RX Clk CTS LIN Break Detection Autobaud RTS Figure 20 1 UART 1 Block Diagram 20 2 Features UART1 provides the following features Asynchronous transmissions and receptions Dedicated baud rate generator supports baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 5 6 7 8 or 9 bit data Automatic start and stop generation A...

Page 293: ...logic low followed by the data bits sent LSB first a parity or extra bit if selected and end with one or two stop bits logic high The data length is variable between 5 and 8 bits A parity bit can be appended to the data and automatically generated and detected by hardware for even odd mark or space parity The stop bit length is selectable between short 1 bit time and long 1 5 or 2 bit times and a ...

Page 294: ...e transferred into the receive buffer under the following conditions There is room in the receive buffer for the data MCE is set to 1 and the stop bit is also 1 XBE 0 MCE is set to 1 and the extra bit is also 1 XBE 1 MCE is 0 stop or extra bit will be ignored In the event that there is not room in the receive buffer for the data the most recently received data will be lost The RI flag will be set ...

Page 295: ... when the transmit FIFO is not full indicating that more data may be written Any data written to SBUF1 when the transmit FIFO is full will over write the most recent data written to the buffer and a data byte will be lost In the course of normal operations the transmit FIFO may be maintained with an interrupt based system filling the FIFO as space al lows and servicing any write request interrupts...

Page 296: ...Data reception begins when a start condition is recognized on the RX pin Data will be received at the selected baud rate through the end of the data phase Data will be transferred into the receive buffer under the following conditions There is room in the receive buffer for the data MCE is set to 1 and the stop bit is also 1 XBE 0 MCE is set to 1 and the extra bit is also 1 XBE 1 MCE is 0 stop or ...

Page 297: ... for all incoming data The circuitry can detect a break sync sequence in the middle of an incoming data stream and react accordingly The UART will indicate that a break has been detected by setting the BREAKDN flag to 1 Likewise hardware will set the SYNCD bit if a valid sync is detected and the SYNCTO bit will indicate if a sync timeout has occured The break done and sync flags may be individ ual...

Page 298: ...crossbar by default It is also possible to route the RX input to the output of CLU0 CLU1 or CLU2 This function is selected by the RXSEL field in register UART1PCF EFM8UB3 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 silabs com Building a more connected world Rev 0 2 298 ...

Page 299: ... has occurred 5 Reserved Must write reset value 4 REN 0 RW Receive Enable This bit enables disables the UART receiver When disabled bytes can still be read from the receive FIFO but the receiver will not place new data into the FIFO Value Name Description 0 RECEIVE_DISABLED UART1 reception disabled 1 RECEIVE_ENABLED UART1 reception enabled 3 TBX 0 RW Extra Transmission Bit The logic level of this ...

Page 300: ...pling time RI remains set while the receive FIFO contains any data Hardware will clear this bit when the receive FIFO is empty If a read of SBUF1 is performed when RI is cleared the most recently received byte will be returned EFM8UB3 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 silabs com Building a more connected world Rev 0 2 300 ...

Page 301: ...ITY Odd 0x1 EVEN_PARITY Even 0x2 MARK_PARITY Mark 0x3 SPACE_PARITY Space 4 PE 0 RW Parity Enable This bit activates hardware parity generation and checking The parity type is selected by the SPT field when parity is ena bled Value Name Description 0 PARITY_DISABLED Disable hardware parity 1 PARITY_ENABLED Enable hardware parity 3 2 SDL 0x3 RW Data Length Value Name Description 0x0 5_BITS 5 bits 0x...

Page 302: ...ion 7 0 SBUF1 Varies RW Serial Port Data Buffer This SFR accesses the transmit and receive FIFOs When data is written to SBUF1 and TXNF is 1 the data is placed into the transmit FIFO and is held for serial transmission Any data in the TX FIFO will initiate a transmission Writing to SBUF1 while TXNF is 0 will over write the most recent byte in the TX FIFO A read of SBUF1 returns the oldest byte in ...

Page 303: ...r 4 0x2 DIV_BY_48 Prescaler 48 0x3 DIV_BY_1 Prescaler 1 0x4 DIV_BY_8 Prescaler 8 0x5 DIV_BY_16 Prescaler 16 0x6 DIV_BY_24 Prescaler 24 0x7 DIV_BY_32 Prescaler 32 20 4 5 SBRLH1 UART1 Baud Rate Generator High Byte Bit 7 6 5 4 3 2 1 0 Name BRH Access RW Reset 0x00 SFR Page 0x20 SFR Address 0x96 Bit Name Reset Access Description 7 0 BRH 0x00 RW UART1 Baud Rate Reload High This field is the high byte o...

Page 304: ... Reload Low This field is the low byte of the 16 bit UART1 baud rate generator The high byte of the baud rate generator should be writ ten first then the low byte The baud rate is determined by the following equation Baud Rate SYSCLK 65536 BRH1 BRL1 1 2 1 Prescaler EFM8UB3 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 silabs com Building a more connected world Rev 0 2 304 ...

Page 305: ... the TX FIFO is empty 0x1 ONE TFRQ will be set when the TX FIFO contains one or fewer bytes 0x2 TWO TFRQ will be set when the TX FIFO contains two or fewer bytes 0x3 THREE TFRQ will be set when the TX FIFO contains three or fewer bytes 3 RFRQE 0 RW Read Request Interrupt Enable When set to 1 a UART1 interrupt will be generated any time RFRQ is logic 1 Value Name Description 0 DISABLED UART1 interr...

Page 306: ... than one byte 0x2 TWO RFRQ will be set if the RX FIFO contains more than two bytes 0x3 THREE RFRQ will be set if the RX FIFO contains more than three bytes EFM8UB3 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 silabs com Building a more connected world Rev 0 2 306 ...

Page 307: ...omplete any byte transmission in pro gress but no further data will be sent Transmission will continue when the TXHOLD bit is cleared If CTS is used for hard ware flow control either TXHOLD or CTS assertion will cause transmission to stall Value Name Description 0 CONTINUE The UART will continue to transmit any available data in the TX FIFO 1 HOLD The UART will not transmit any new data from the T...

Page 308: ...e UART RX line 0x3 TIMEOUT_16 A receive timeout will occur after 16 idle periods on the UART RX line 0 RIE 1 RW Receive Interrupt Enable This bit enables the RI flag to generate UART1 interrupts when there is information available in the receive FIFO regard less of the RXTH settings Value Name Description 0 DISABLED The RI flag will not generate UART1 interrupts 1 ENABLED The RI flag will generate...

Page 309: ...meout Flag This bit is set by hardware if a sync measurement in process overflows the baud rate generator This is usually an indica tion that the prescaler must be increased When a sync timeout occurs the baud rate generator is not updated Firmware must clear this bit to 0 Value Name Description 0 NOT_SET A sync timeout has not occured 1 TIMEOUT A sync timeout occured 4 SYNCD 0 RW LIN Sync Detect ...

Page 310: ...et 0 SYNCDIE 0 RW LIN Sync Detect Interrupt Enable Enables the sync detection interrupt source Value Name Description 0 DISABLED The SYNCD flag will not generate UART1 interrupts 1 ENABLED The SYNCD flag will generate UART1 interrupts when it is set 20 4 11 UART1PCF UART1 Configuration Bit 7 6 5 4 3 2 1 0 Name Reserved RXSEL Access R RW Reset 0x00 0x0 SFR Page 0x20 SFR Address 0xDA Bit Name Reset ...

Page 311: ...nal USBn Oscillator Clock Recovery to SYSCLK mux Data Transfer Control Control Status Endpoint 0 IN OUT USB FIFO space in External RAM USBn_EP1 Endpoint IN OUT USBn_EP2 Endpoint IN OUT USBn_EP3 Endpoint IN OUT D D Transceiver VDD Figure 21 1 USB Block Diagram 21 2 Features The USB0 module includes the following features Full and Low Speed functionality Implements 4 bidirectional endpoints Low Ener...

Page 312: ...A typical full speed applica tion would configure the USB clock to run directly from the HFOSC1 oscillator while a typical low speed application would configure the clock for HFOSC1 8 The USB clock may also be derived from an external CMOS clock with various divider options By default the clock to the USB module is turned off to save power Clock Recovery circuitry uses the incoming USB data stream...

Page 313: ...us Registers Endpoint3 Control Status Registers Common Registers Interrupt Registers Special Function Registers USB0ADR USB0DAT Figure 21 2 USB Indirect Register Access Note The USB clock must be active when accessing indirect USB registers Table 21 2 USB Indirect Registers USB Register Name USB Register Address Description Interrupt Registers IN1INT 0x02 Endpoint0 and Endpoints1 3 IN Interrupt Fl...

Page 314: ...ntrol Status EINCSRL Endpoint IN Control Status Low Byte EINCSRH 0x12 Endpoint IN Control Status High Byte EOUTCSRL 0x14 Endpoint OUT Control Status Low Byte EOUTCSRH 0x15 Endpoint OUT Control Status High Byte E0CNT 0x16 Number of Received Bytes in Endpoint0 FIFO EOUTCNTL Endpoint OUT Packet Count Low Byte EOUTCNTH 0x17 Endpoint OUT Packet Count High Byte EFM8UB3 Reference Manual Universal Serial ...

Page 315: ...n System Clock Domain Figure 21 3 FIFO Memory Map FIFO Split Mode The FIFO space for Endpoints1 3 can be split such that the upper half of the FIFO space is used by the IN endpoint and the lower half is used by the OUT endpoint For example if the Endpoint3 FIFO is configured for Split Mode the upper 256 bytes are used by End point3 IN and the lower 256 bytes are used by Endpoint3 OUT If an endpoin...

Page 316: ...ter unloads one byte from the OUT endpoint FIFO a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO Accessing the Unused FIFO Memory Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary The FIFO block operates on the USB clock domain thus the USB clock must be active when accessing FIFO space Note that the number of SYSCLK cycles required ...

Page 317: ...P bit the isochronous update function is enabled With isochronous update enabled new packets written to an isochronous IN endpoint will not be transmitted until a new Start Of Frame SOF is received If the isochro nous IN endpoint receives an IN token before a SOF the USB interface will transmit a zero length packet When ISOUP 1 isochro nous update is enabled for all isochronous endpoints USB Enabl...

Page 318: ... a SETUP packet is loaded into the Endpoint0 FIFO Software should unload the command from the Endpoint0 FIFO decode the command perform any necessary tasks and set the SOPRDY bit to indicate that it has serviced the OUT packet Endpoint0 IN Transactions When a SETUP request is received that requires the USB interface to transmit data to the host one or more IN requests will be sent by the host For ...

Page 319: ...n an Endpoint is disabled it will not respond to bus traffic or stall the bus All Endpoints are enabled by default Endpoint 1 3 IN General Control Endpoints 1 3 IN are managed via USB registers EINCSRL and EINCSRH All IN endpoints can be used for Interrupt Bulk or Isochro nous transfers Isochronous ISO mode is enabled by writing 1 to the ISO bit in register EINCSRH Bulk and Interrupt transfers are...

Page 320: ...nt has been configured to operate in Bulk Interrupt OUT mode typically following an Endpoint0 SET_INTERFACE command hardware will set the OPRDY bit to 1 and generate an interrupt upon reception of an OUT token and data packet The number of bytes in the current OUT data packet the packet ready to be unloaded from the FIFO is given in the EOUTCNTH and EOUTCNTL registers In response to this interrupt...

Page 321: ...for detecting the presence of non standard charging hardware Firmware may optionally implement algorithms to detect ACA or non compliant charger hardware Note The USB charger detect function only distinguishes between the various types of USB ports outlined in the specification The device itself does not contain direct battery management or battery charging circuitry Firmware interfaces to the USB...

Page 322: ... enable data contact detection and the associated timeout circuit 4 Set PDEN to enable Primary Detection 5 Set CHDEN to begin the charge detect sequence 6 Wait for Primary Detection to complete PDI 1 or service the interrupt 7 The SDP bit will indicate if a Standard Downstream Port is detected 8 If the application requires further differentiation between DCP and CDP set SDEN to enable Secondary De...

Page 323: ... Timeout DCP Detected CDP Detected Charge and or Enable USB Not SDP PD Complete SD Complete Enable SD Yes Must Assume DCP Profile Firmware Action Hardware Action Optional Interrupt Figure 21 4 Basic USB Charger Detection Flow Diagram EFM8UB3 Reference Manual Universal Serial Bus USB0 silabs com Building a more connected world Rev 0 2 323 ...

Page 324: ...en different ACA options Applications need ing to determine ACA ports should check for ACA after primary detection is complete and optionally after data contact detection is complete Many dedicated charging units pre date the USB Battery Charging Specification or do not comply with this specification for other rea sons such as additional supply current capabilities Most of these cases implement re...

Page 325: ...CP Detected CDP Detected Charge and or Enable USB PD Complete SD Complete Enable SD Yes Must Assume DCP Profile Handle Non Compliant Charger Enable DCD and PD Non compliant charger detected Check for ACA Not SDP Optional Interrupt Optional Firmware Figure 21 5 USB Charger Detection Flow Diagram with ACA and Non Compliant Charger EFM8UB3 Reference Manual Universal Serial Bus USB0 silabs com Buildin...

Page 326: ...le the USB0 physical layer transceiver normal 5 SPEED 0 RW USB0 Speed Select This bit selects the USB0 speed Value Name Description 0 LOW_SPEED USB0 operates as a Low Speed device If enabled the internal pull up resistor appears on the D line 1 FULL_SPEED USB0 operates as a Full Speed device If enabled the internal pull up resistor appears on the D line 4 3 PHYTST 0x0 RW Physical Layer Test Value ...

Page 327: ...ess 0xAE Bit Name Reset Access Description 7 BUSY 0 RW USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses 6 AUTORD 0 RW USB0 Register Auto Read Flag This bit is used for block FIFO reads Value Name Description 0 DISABLED BUSY must be written manually for each USB0 indirect register read 1 ENABLED The next indirect register read will automatically be initiated when...

Page 328: ...R RW Reset 0x0 0x0 Indirect Address 0x0E Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 0 EPSEL 0x0 RW Endpoint Select Bits This field selects which endpoint is targeted when indexed USB0 registers are accessed Value Name Description 0x0 ENDPOINT_0 Endpoint 0 0x1 ENDPOINT_1 Endpoint 1 0x2 ENDPOINT_2 Endpoint 2 0x3 ENDPOINT_3 Endpoint 3 This register is accessed indirectly ...

Page 329: ... the oscillator calibration into single step mode during clock recovery Value Name Description 0 DISABLED Disable single step mode normal calibration mode 1 ENABLED Enable single step mode 5 CRLOW 0 RW Low Speed Clock Recovery Mode This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB device Value Name Description 0 FULL_SPEED Full Speed Mode 1 LOW_SPEED Low Speed M...

Page 330: ...ODATA 0x00 RW Endpoint 1 FIFO Access Writing to this FIFO address loads data into the IN FIFO for Endpoint 1 Reading from the FIFO address reads data from the Endpoint 1 OUT FIFO This register is accessed indirectly using the USB0ADR and USB0DAT registers 21 4 8 FIFO2 USB0 Endpoint 2 FIFO Access Bit 7 6 5 4 3 2 1 0 Name FIFODATA Access RW Reset 0x00 Indirect Address 0x22 Bit Name Reset Access Desc...

Page 331: ... Access Description 7 UPDATE 0 R Function Address Update Set to 1 when firmware writes the FADDR register USB0 clears this bit to 0 when the new address takes effect Value Name Description 0 NOT_SET The last address written to FADDR is in effect 1 SET The last address written to FADDR is not yet in effect 6 0 FADDR 0x00 RW Function Address This field is the 7 bit function address for USB0 This add...

Page 332: ...it is set to 1 by hardware when reset signalling is detected on the bus Upon this detection the following occur 1 The USB0 Address is reset FADDR 0x00 2 Endpoint FIFOs are flushed 3 Control status registers are reset to 0x00 E0CSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH 4 USB register INDEX is reset to 0x00 5 All USB interrupts excluding the suspend interrupt are enabled and their corresponding flags cl...

Page 333: ...ss 0x0C Bit Name Reset Access Description 7 0 FRMEL 0x00 R Frame Number Low This register contains bits 7 0 of the last received frame number This register is accessed indirectly using the USB0ADR and USB0DAT registers 21 4 13 FRAMEH USB0 Frame Number High Bit 7 6 5 4 3 2 1 0 Name Reserved FRMEH Access R R Reset 0x00 0x0 Indirect Address 0x0D Bit Name Reset Access Description 7 3 Reserved Must wri...

Page 334: ... the IN1INT register Value Name Description 0 NOT_SET IN Endpoint 2 interrupt inactive 1 SET IN Endpoint 2 interrupt active 1 IN1 0 R IN Endpoint 1 Interrupt Flag This bit is cleared when firmware reads the IN1INT register Value Name Description 0 NOT_SET IN Endpoint 1 interrupt inactive 1 SET IN Endpoint 1 interrupt active 0 EP0 0 R Endpoint 0 Interrupt Flag This bit is cleared when firmware read...

Page 335: ...ive 2 OUT2 0 R OUT Endpoint 2 Interrupt Flag This bit is cleared when firmware reads the OUT1INT register Value Name Description 0 NOT_SET OUT Endpoint 2 interrupt inactive 1 SET OUT Endpoint 2 interrupt active 1 OUT1 0 R OUT Endpoint 1 Interrupt Flag This bit is cleared when firmware reads the OUT1INT register Value Name Description 0 NOT_SET OUT Endpoint 1 interrupt inactive 1 SET OUT Endpoint 1...

Page 336: ... bus This bit is cleared when firmware reads the CMINT register Value Name Description 0 NOT_SET Reset interrupt inactive 1 SET Reset interrupt active 1 RSUINT 0 R Resume Interrupt Flag Set by hardware when resume signaling is detected on the bus while USB0 is in suspend mode This bit is cleared when firmware reads the CMINT register Value Name Description 0 NOT_SET Resume interrupt inactive 1 SET...

Page 337: ...nt 2 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 2 IN interrupts 1 ENABLED Enable Endpoint 2 IN interrupts 1 IN1E 1 RW IN Endpoint 1 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 1 IN interrupts 1 ENABLED Enable Endpoint 1 IN interrupts 0 EP0E 1 RW Endpoint 0 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 0 interrupts 1 ENABLED Ena...

Page 338: ...D Enable Endpoint 3 OUT interrupts 2 OUT2E 1 RW OUT Endpoint 2 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 2 OUT interrupts 1 ENABLED Enable Endpoint 2 OUT interrupts 1 OUT1E 1 RW OUT Endpoint 1 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 1 OUT interrupts 1 ENABLED Enable Endpoint 1 OUT interrupts 0 Reserved Must write reset value This register is ac...

Page 339: ...TE 1 RW Reset Interrupt Enable Value Name Description 0 DISABLED Disable reset interrupts 1 ENABLED Enable reset interrupts 1 RSUINTE 1 RW Resume Interrupt Enable Value Name Description 0 DISABLED Disable resume interrupts 1 ENABLED Enable resume interrupts 0 SUSINTE 0 RW Suspend Interrupt Enable Value Name Description 0 DISABLED Disable suspend interrupts 1 ENABLED Enable suspend interrupts This ...

Page 340: ...o SSUEND 3 DATAEND 0 RW Data End Firmware should write 1 to this bit 1 When writing 1 to INPRDY for the last outgoing data packet 2 When writing 1 to INPRDY for a zero length data packet 3 When writing 1 to SOPRDY after servicing the last incoming data packet This bit is automatically cleared by hardware 2 STSTL 0 RW Sent Stall Hardware sets this bit to 1 after transmitting a STALL handshake signa...

Page 341: ...Must write reset value 6 0 E0CNT 0x00 R Endpoint 0 Data Count This 7 bit number indicates the number of received data bytes in the Endpoint 0 FIFO This number is only valid while OPRDY is 1 This register is accessed indirectly using the USB0ADR and USB0DAT registers EFM8UB3 Reference Manual Universal Serial Bus USB0 silabs com Building a more connected world Rev 0 2 341 ...

Page 342: ...normal 2 EEN2 1 RW Endpoint 2 Enable This bit enables or disables Endpoint 2 Value Name Description 0 DISABLED Disable Endpoint 2 no NACK ACK or STALL on the USB network 1 ENABLED Enable Endpoint 2 normal 1 EEN1 1 RW Endpoint 1 Enable This bit enables or disables Endpoint 1 Value Name Description 0 DISABLED Disable Endpoint 1 no NACK ACK or STALL on the USB network 1 ENABLED Enable Endpoint 1 norm...

Page 343: ... the FLUSH bit to 0 when the FIFO flush is complete 2 UNDRUN 0 RW Data Underrun Flag The function of this bit depends on the IN Endpoint mode Isochronous Set when a zero length packet is sent after an IN token is received while bit INPRDY 0 Interrupt Bulk Set when a NAK is returned in response to an IN token This bit must be cleared by firmware 1 FIFONE 0 RW FIFO Not Empty Value Name Description 0...

Page 344: ...is valid only when the selected FIFO is not split SPLIT 0 Value Name Description 0 OUT Endpoint direction selected as OUT 1 IN Endpoint direction selected as IN 4 Reserved Must write reset value 3 FCDT 0 RW Force Data Toggle Value Name Description 0 ACK_TOGGLE Endpoint data toggle switches only when an ACK is received following a data packet transmission 1 ALWAYS_TOGGLE Endpoint data toggle forced...

Page 345: ...FIFO should be read manually 3 DATERR 0 R Data Error Flag In Isochronous mode this bit is set by hardware if a received packet has a CRC or bit stuffing error It is cleared when firmware clears OPRDY This bit is only valid in Isochronous mode 2 OVRUN 0 RW Data Overrun Flag This bit is set by hardware when an incoming data packet cannot be loaded into the OUT Endpoint FIFO This bit is only valid in...

Page 346: ...for Bulk Interrupt transfers 1 ENABLED Endpoint configured for Isochronous transfers 5 0 Reserved Must write reset value This register is accessed indirectly using the USB0ADR and USB0DAT registers 21 4 27 EOUTCNTL USB0 OUT Endpoint Count Low Bit 7 6 5 4 3 2 1 0 Name EOCL Access R Reset 0x00 Indirect Address 0x16 Bit Name Reset Access Description 7 0 EOCL 0x00 R OUT Endpoint Count Low EOCL holds t...

Page 347: ...set value 1 0 EOCH 0x0 R OUT Endpoint Count High EOCH holds the upper 2 bits of the 10 bit number of data bytes in the last received packet in the current OUT endpoint FIFO This number is only valid while OPRDY 1 This register is accessed indirectly using the USB0ADR and USB0DAT registers EFM8UB3 Reference Manual Universal Serial Bus USB0 silabs com Building a more connected world Rev 0 2 347 ...

Page 348: ...nse event has occurred If VBUS interrupts are enabled an interrupt will be generated any time the VBUS line transitions from high to low or low to high This bit must be cleared by firmware Value Name Description 0 NOT_SET A VBUS event has not occurred 1 SET A VBUS event has occurred 4 3 Reserved Must write reset value 2 0 USBCLK 0x7 RW USB0 Clock Source Select Bits Value Name Description 0x0 HFOSC...

Page 349: ...Bit Name Reset Access Description 0x7 NOCLOCK USB0 clock USB0CLK is turned off EFM8UB3 Reference Manual Universal Serial Bus USB0 silabs com Building a more connected world Rev 0 2 349 ...

Page 350: ...Energy Mode Oscillator Control This field configures how LE mode affects USB clocking It should be set to 00 in most applications Value Name Description 0x0 OSC_GATED_SUS PEND The USB clock source is selectively gated by LE mode and the High Frequency Oscillator HFOSC1 is suspended if possible 0x1 OSC_GATED The USB clock source is selectively gated by LE mode There is no ef fect to HFOSC1 0x3 OSC_...

Page 351: ...lowed to generate charger detect interrupts 2 PDIE 0 RW PD Interrupt Enable Enables the PDI flag as an interrupt source Value Name Description 0 DISABLED PDI will not generate charger detect interrupts 1 ENABLED PDI allowed to generate charger detect interrupts 1 DCDIE 0 RW DCD Interrupt Enable Enables the DCDI flag as an interrupt source Value Name Description 0 DISABLED DCDI will not generate ch...

Page 352: ...EN is 00 When SD finishes the SDEN bit will return to 0 and the SDI flag will be asserted Value Name Description 0 DISABLED Disable secondary detection 1 ENABLED Enable secondary detection 2 PDEN 0 RW Primary Detection Enable This bit enables primary detection PD when CHDEN is set to 1 PD will occur on completion of DCD or when DCDEN is 00 When PD finishes the PDEN bit will return to 0 and the PDI...

Page 353: ...g Downstream Port has been deteted 4 DCP 0 RW Dedicated Charging Port Detected This bit is set at the completion of a secondary detection phase if a Dedicated Chargring Port has been deteted 3 SDI 0 RW Secondary Detection Complete This bit is set at the completion of a SD operation Value Name Description 0 NOT_SET SD operation has not completed 1 SET SD operation has completed If SDIE is set to 1 ...

Page 354: ...firmware 0 DCDTO 0 RW Data Contact Detection Timeout This bit is set at the completion of a DCD operation if the operation was stopped due to DCD timeout Value Name Description 0 NO_TIMEOUT A DCD timeout was not triggered 1 TIMEOUT A DCD timeout was triggered EFM8UB3 Reference Manual Universal Serial Bus USB0 silabs com Building a more connected world Rev 0 2 354 ...

Page 355: ...an be permanently enabled if desired When the WDT is active the low frequency oscillator is forced on All watchdog features are controlled via the Watchdog Timer Control Register WDTCN Watchdog Timer Counter Comparator Always Active Counter WDT Flag Divided LFOSC0 Watchdog Reset Enable Reset Timeout Interval Disable Lock Figure 22 1 Watchdog Timer Block Diagram 22 2 Features The watchdog timer inc...

Page 356: ...to WDTCN locks out the disable feature Once locked out the disable operation is ignored until the next system reset Writing 0xFF does not enable or reset the watchdog timer Applications always intending to use the watchdog should write 0xFF to WDTCN in the initialization code Setting the WDT Interval WDTCN 2 0 controls the watchdog timeout interval The interval is given by the following equation w...

Page 357: ...terval only while the WDT is disabled 22 4 WDT0 Control Registers 22 4 1 WDTCN Watchdog Timer Control Bit 7 6 5 4 3 2 1 0 Name WDTCN Access RW Reset 0x17 SFR Page ALL SFR Address 0x97 Bit Name Reset Access Description 7 0 WDTCN 0x17 RW WDT Control The WDT control field has different behavior for reads and writes Read When reading the WDTCN register the lower three bits WDTCN 2 0 indicate the curre...

Page 358: ...Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in system debugging and flash programming may be per formed C2CK is shared with the RSTb pin while the C2D signal is shared with a port I O pin This is possible because C2 communica tion is typically performed when the device is in the halt state where all on chip peripherals and user software are stalled In this h...

Page 359: ...FPCTL 0xB4 C2FPDAT 23 4 2 C2DEVID C2 Device ID Bit 7 6 5 4 3 2 1 0 Name C2DEVID Access R Reset 0x36 C2 Address 0x00 Bit Name Reset Access Description 7 0 C2DEVID 0x36 R Device ID This read only register returns the 8 bit device ID 23 4 3 C2REVID C2 Revision ID Bit 7 6 5 4 3 2 1 0 Name C2REVID Access R Reset Varies C2 Address 0x01 Bit Name Reset Access Description 7 0 C2REVID Varies R Revision ID T...

Page 360: ...ming is enabled a system reset must be issued to resume normal operation 23 4 5 C2FPDAT C2 Flash Programming Data Bit 7 6 5 4 3 2 1 0 Name C2FPDAT Access RW Reset 0x00 C2 Address 0xB4 Bit Name Reset Access Description 7 0 C2FPDAT 0x00 RW C2 Flash Programming Data Register This register is used to pass flash commands addresses and data during C2 flash accesses Valid commands are listed below 0x03 D...

Page 361: ...tion Updated the WDT behaviour for all the commands in 22 3 Using the Watchdog Timer section Added Synchronization section in 22 3 Using the Watchdog Timer Revision 0 1 October 2017 Initial release EFM8UB3 Reference Manual Revision History silabs com Building a more connected world Rev 0 2 361 ...

Page 362: ... or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significan...

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