SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus master and/or slave modes, select the SMBus clock source,
and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events.
Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA
pins; however, the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all
slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer).
The SMBCS bit field selects the SMBus clock source, which is used only when operating as a master or when the Free Timeout detec-
tion is enabled. When operating as a master, overflows from the selected source determine both the bit rate and the absolute minimum
SCL low and high times. The selected clock source may be shared by other peripherals so long as the timer is left running at all times.
The selected clock source should typically be configured to overflow at three times the desired bit rate. When the interface is operating
as a master (and SCL is not driven or extended by any other devices on the bus), the device will hold the SCL line low for one overflow
period, and release it for two overflow periods. T
HIGH
is typically twice as large as T
LOW
. The actual SCL output may vary due to other
devices on the bus (SCL may be extended low by slower slave devices, driven low by contending master devices, or have long ramp
times). The SMBus hardware will ensure that once SCL does return high, it reads a logic high state for a minimum of one overflow
period.
SCL
Timer Source
Overflows
SCL High Timeout
T
Low
T
High
Figure 18.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the abso-
lute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute mini-
mum time that the current SDA value remains stable after SCL transitions from high-to-low. EXTHOLD should be set so that the mini-
mum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Setup and hold time exten-
sions are typically necessary for SMBus compliance when SYSCLK is above 10 MHz.
Table 18.1. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
0
T
low
– 4 system clocks or 1 system clock + s/w delay 3 system clocks
1
11 system clocks
12 system clocks
Note:
Setup Time for ACK bit transmissions and the MSB of all data transfers. When using software acknowledgment, the s/w delay
occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in the same write that defines
the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts. The SMBus inter-
face will force the associated timer to reload while SCL is high, and allow the timer to count when SCL is low. The timer interrupt serv-
ice routine should be used to reset SMBus communication by disabling and re-enabling the SMBus. SMBus Free Timeout detection can
be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than
10 SMBus clock source periods.
SMBus Pin Swap
The SMBus peripheral is assigned to pins using the priority crossbar decoder. By default, the SMBus signals are assigned to port pins
starting with SDA on the lower-numbered pin, and SCL on the next available pin. The SWAP bit in the SMBus Timing Control register
can be set to 1 to reverse the order in which the SMBus signals are assigned.
EFM8UB3 Reference Manual
System Management Bus / I2C (SMB0)
silabs.com
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