Clock Selection
Clocking for each timer is configured using the TnXCLK bit field and the TnML and TnMH bits. Timer 2 may be clocked by the system
clock, the system clock divided by 12, or the external clock source divided by 8 (synchronized with SYSCLK). The maximum frequency
for the external clock is:
F
SYSCLK
>
F
EXTCLK
×
6
7
Timers 3 and 4 may additionally be clocked from the LFOSC0 output divided by 8, and are capable of operating in both the Suspend
and Snooze power modes. Timer 4 includes Timer 3 overflows as a clock source, allowing the two to be chained together for longer
sleep intervals. When operating in one of the 16-bit modes, the low-side timer clock is used to clock the entire 16-bit timer.
To Timer Low
Clock Input
Timer Clock Selection
SYSCLK
TnXCLK
TnML
TnMH
To Timer High
Clock Input
(for split mode)
SYSCLK / 12
External Clock / 8
LFOSC0 / 8
(T3 and T4)
T3 Overflows (T4)
Figure 19.4. Timer 2, 3, 4, and 5 Clock Source Selection
EFM8UB3 Reference Manual
Timers (Timer0, Timer1, Timer2, Timer3, Timer4, and Timer5)
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