17.3 Functional Description
17.3.1 Counter / Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte of the 16-bit counter/timer and
PCA0L is the low byte. Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read
accesses this “snapshot” register.
Note:
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD register select the timebase
for the counter/timer.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt
request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt
request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared
by software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode.
Table 17.1. PCA Timebase Input Options
CPS2:0
Timebase
000
System clock divided by 12
001
System clock divided by 4
010
Timer 0 overflow
011
High-to-low transitions on ECI (max rate = system clock divided by 4)
100
System clock
101
External oscillator source divided by 8
110
Low frequency oscillator divided by 8
111
Reserved
Note:
1. Synchronized with the system clock.
17.3.2 Interrupt Sources
The PCA0 module shares one interrupt vector among all of its modules. There are are several event flags that can be used to generate
a PCA0 interrupt. They are as follows: the main PCA counter overflow flag (CF), which is set upon a 16-bit overflow of the PCA0 coun-
ter; an intermediate overflow flag (COVF), which can be set on an overflow from the 8th–11th bit of the PCA0 counter; and the individu-
al flags for each PCA channel (CCFn), which are set according to the operation mode of that module. These event flags are always set
when the trigger condition occurs. Each of these flags can be individually selected to generate a PCA0 interrupt using the correspond-
ing interrupt enable flag (ECF for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before
any individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by setting the EA bit and the
EPCA0 bit to logic 1.
17.3.3 Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high-
speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit pulse width modulator.
PCA0PWM Bit Settings for PCA Capture/Compare Modules on page 167
summarizes the bit settings in the PCA0CPMn and
PCA0PWM registers used to select the PCA capture/compare module’s operating mode. All modules set to use 8-, 9-, 10-, or 11-bit
PWM mode must use the same cycle length (8–11 bits). Setting the ECCFn bit in a PCA0CPMn register enables the module's CCFn
interrupt.
EFM8SB2 Reference Manual
Programmable Counter Array (PCA0)
silabs.com
| Smart. Connected. Energy-friendly.
Rev. 0.1 | 166
