20. System Management Bus / I2C (SMB0)
20.1 Introduction
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica-
tion, version 1.1, and compatible with the I
2
C serial bus.
SMB0
Slave Address
Recognition
SMB0DAT
Master SCL Clock
Generation
Shift Register
SDA
SCL
State Control
Logic
SI
Timers 0,
1 or 2
SCL Low
Timer 3
Data /
Address
Figure 20.1. SMBus 0 Block Diagram
20.2 Features
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
• Support for master, slave, and multi-master modes.
• Hardware synchronization and arbitration for multi-master mode.
• Clock low extending (clock stretching) to interface with faster masters.
• Hardware support for 7-bit slave and general call address recognition.
• Firmware support for 10-bit slave address decoding.
• Ability to inhibit all slave states.
• Programmable data setup/hold times.
20.3 Functional Description
20.3.1 Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
• The I
2
C-Bus and How to Use It (including specifications), Philips Semiconductor.
• The I
2
C-Bus Specification—Version 2.0, Philips Semiconductor.
• System Management Bus Specification—Version 1.1, SBS Implementers Forum.
EFM8SB2 Reference Manual
System Management Bus / I2C (SMB0)
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