20.3.2 SMBus Protocol
The SMBus specification allows any recessive voltage between 3.0 and 5.0 V; different devices on the bus may operate at different
voltage levels. However, the maximum voltage on any port pin must conform to the electrical characteristics specifications. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or
similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so
that both are pulled high (recessive state) when the bus is free. The maximum number of devices on the bus is limited only by the
requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
VDD = 5 V
Master
Device
SlaveDevice
1
SlaveDevice
2
VDD = 3 V
VDD = 5 V
VDD = 3 V
SDA
SCL
Figure 20.2. Typical SMBus System Connection
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data
transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and
provides the serial clock pulses on SCL. The SMBus interface may operate as a master or a slave, and multiple master devices on the
same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed
with a single master always winning the arbitration. It is not necessary to specify one device as the Master in a system; any device who
transmits a START and a slave address becomes the master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address; Bit0: R/W direc-
tion bit), one or more bytes of data, and a STOP condition. Bytes that are received (by a master or slave) are acknowledged (ACK) with
a low SDA during a high SCL (see
Figure 20.3 SMBus Transaction on page 225
). If the receiving device does not ACK, the transmit-
ting device will read a NACK (not acknowledge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a
"READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START
condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave,
the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the
slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master gener-
ates a STOP condition to terminate the transaction and free the bus.
Figure 20.3 SMBus Transaction on page 225
SMBus transaction.
EFM8SB2 Reference Manual
System Management Bus / I2C (SMB0)
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