Master Read Sequence
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the
address byte, and a receiver during all data bytes. The SMBus interface generates the START condition and transmits the first byte
containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ).
Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of
serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each received byte. Software must
write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK, and then post the interrupt. It
is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware
ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to the ACK bit for the last data
transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated. The interface
will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver.
Figure 20.7 Typical Master Read Se-
shows a typical master read sequence as it appears on the bus, and
Figure 20.8 Master Read Sequence State
Diagram (EHACK = 1) on page 236
shows the corresponding firmware state machine. Two received data bytes are shown, though any
number of bytes may be received. Notice that the "data byte transferred" interrupts occur at different places in the sequence, depending
on whether hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and
after the ACK when hardware ACK generation is enabled.
a
a
Data Byte
Data Byte
A
N
A
S
R
P
SLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
b
c
d
b
c
d
Figure 20.7. Typical Master Read Sequence
EFM8SB2 Reference Manual
System Management Bus / I2C (SMB0)
silabs.com
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