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2016-04-28 - Giant Gecko Family - d0053_Rev1.20
284
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A typical isochronous IN operation in DMA mode is shown in Figure 15.18 (p. 283) . See channel 2
(ch_2). The assumptions are:
• The application is attempting to receive one packet in every frame (up to 1 maximum packet size of
1,024 bytes).
• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDS per
packet (1,031 bytes).
• Periodic Request Queue depth = 4.
15.4.3.6.16.1 Normal Isochronous IN Operation
The sequence of operations in Figure 15.18 (p. 283) (channel 2) is as follows:
1. Initialize and enable channel 2 as explained in Channel Initialization (p. 256) .
2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from the
arbiter (round-robin with fairness). In high-bandwidth transfers, the host performs consecutive writes
up to MC times.
3. The host attempts to send an IN token at the beginning of the next (odd) frame.
4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD
interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
15.4.3.6.16.2 Handling Interrupts
The channel-specific interrupt service routine for an isochronous IN transaction in DMA mode is as
follows.
Isochronous IN
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL or FRMOVRUN)
{
if (XFERCOMPL and (USB_HCx_TSIZ.PKTCNT == 0))
{
Reset Error Count
De-allocate Channel
}
else
{
De-allocate Channel
}
}
else if (XACTERR or BBLERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Increment Error Count
Re-enable Channel (in next b_interval - 1 Frame)
}
}
}
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