Silicon Laboratories Giant Gecko EFM32GG, Reference Manual

Page 1: ... µs The EFM32GG microcontroller series revolutionizes the 8 to 32 bit market with a combination of unmatched performance and ultra low power consumption in both active and sleep modes EFM32GG devices consume as little as 219 µA MHz in run mode EFM32GG s low energy consumption outperforms any other available 8 16 and 32 bit solution The EFM32GG includes autonomous and energy efficient peripherals h...

Page 2: ...igners get more out of the available energy in a variety of applications Ultra low energy EFM32GG microcontrollers are perfect for Gas metering Energy metering Water metering Smart metering Alarm and security systems Health and fitness applications Industrial and home automation 0 1 2 3 4 1 2 EFM32GG Development Because EFM32GG use the Cortex M3 CPU embedded designers benefit from the largest deve...

Page 3: ...egister where x denotes the port instance A B Bit Fields Registers contain one or more bit fields which can be 1 to 32 bits wide Multi bit fields are denoted with x y where x is the start bit and y is the end bit Address The address for each register can be found by adding the base address of the module found in the Memory Map and the offset address for the register found in module Register Map Ac...

Page 4: ...egisters denoted with X have an unknown reset value and need to be initialized before use Note that before these registers are initialized read modify write operations might result in undefined register values Pin Connections Pin connections are given as a module prefix followed by a short pin name USn_TX USARTn TX pin The pin locations referenced in this document are given in the device specific ...

Page 5: ...n 3 4 p 7 Figure 3 1 Block Diagram of EFM32GG Clock Management Energy Management Serial Interfaces I O Ports Core and Memory Timers and Triggers Analog Interfaces Security 32 bit bus Peripheral Reflex System ARM Cortex M3 processor Flash Program Memory LESENSE High Freq RC Oscillator High Freq Crystal Oscillator Timer Counter Low Energy Timer Pulse Counter Real Time Counter Low Freq Crystal Oscill...

Page 6: ... 16 asynchronous external interrupts Output state retention and wake up from Shutoff Mode 12 Channel DMA Controller Alternate primary descriptors with scatter gather ping pong operation 12 Channel Peripheral Reflex System Autonomous inter peripheral signaling enables smart operation in low energy modes External Bus Interface EBI Up to 4x256 MB of external memory mapped space TFT Controller support...

Page 7: ...l to Analog Converter 2 single ended channels 1 differential channel Up to 3 Operational Amplifiers Supports rail to rail inputs and outputs Programmable gain 2 Analog Comparator Programmable speed current Capacitive sensing with up to 8 inputs Supply Voltage Comparator Ultra low power sensor interface Autonomous sensor monitoring in Deep Sleep Mode Wide range of sensors supported including LC sen...

Page 8: ...utonomous operation with a current consumption as low as 1 1 µA with RTC enabled Power on Reset Brown out Detection and full RAM and CPU retention is also included 0 1 2 3 4 EM3 Energy Mode 3 Stop Mode In EM3 the low frequency oscillator is disabled but there is still full CPU and RAM retention as well as Power on Reset Pin reset EM4 wake up and Brown out Detection with a consumption of only 0 8 µ...

Page 9: ...Y 3 QFN64 330F1024 1024 128 53 Y 3 2 2 4 12 1 1 3 1 1 8 2 2 2 12 Y Y 3 QFN64 332F512 512 128 50 Y 3 2 2 4 11 1 1 3 1 1 8 2 2 1 4 Y Y 3 TQFP64 332F1024 1024 128 50 Y 3 2 2 4 11 1 1 3 1 1 8 2 2 1 4 Y Y 3 TQFP64 380F512 512 128 83 Y 3 2 2 2 4 12 1 1 3 1 1 8 2 2 2 12 Y Y Y 3 LQFP100 380F1024 1024 128 83 Y 3 2 2 2 4 12 1 1 3 1 1 8 2 2 2 12 Y Y Y 3 LQFP100 390F512 512 128 87 Y 3 2 2 2 4 12 1 1 3 1 1 8 2...

Page 10: ... 1 8 2 2 2 12 Y Y 1 Y 3 LQFP100 980F1024 1024 128 83 Y 8x34 3 2 2 2 4 12 1 1 3 1 1 8 2 2 2 12 Y Y 1 Y 3 LQFP100 990F512 512 128 87 Y 8x34 3 2 2 2 4 12 1 1 3 1 1 8 2 2 2 12 Y Y 1 Y 3 LFBGA112 990F1024 1024 128 87 Y 8x34 3 2 2 2 4 12 1 1 3 1 1 8 2 2 2 12 Y Y 1 Y 3 LFBGA112 995F512 512 128 93 Y 8x36 3 2 2 2 4 12 1 1 3 1 1 8 2 2 2 16 Y Y 1 Y 3 VFBGA120 995F1024 1024 128 93 Y 8x36 3 2 2 2 4 12 1 1 3 1 ...

Page 11: ...the revisions and the user is referred to the errata document for an overview of erratas that apply to the EFM32GG This document can be found in Simplicity Studio and online at http www silabs com support pages document library aspx p MCUs 32 bit In addition there are a couple of differences not covered by any errata as new functionality is added to later revisions Those differences are listed her...

Page 12: ...ng computational performance and exceptional system response to interrupts while meeting low cost requirements and low power consumption The ARM Cortex M3 implemented is revision r2p1 4 2 Features Harvard Architecture Separate data and program memory buses No memory bottleneck as for a single bus system 3 stage pipeline Thumb 2 instruction set Enhanced levels of performance energy efficiency and c...

Page 13: ...rupt The EFM32GG devices have up to 38 interrupt request lines IRQ which are connected to the Cortex M3 Each of these lines shown in Table 4 1 p 13 are connected to one or more interrupt flags in one or more modules The interrupt flags are set by hardware on an interrupt condition It is also possible to set clear the interrupt flags through the IFS IFC registers Each interrupt flag is then qualifi...

Page 14: ...abs com IRQ Source 10 I2C1 11 GPIO_ODD 12 TIMER1 13 TIMER2 14 TIMER3 15 USART1_RX 16 USART1_TX 17 LESENSE 18 USART2_RX 19 USART2_TX 20 UART0_RX 21 UART0_TX 22 UART1_RX 23 UART1_TX 24 LEUART0 25 LEUART1 26 LETIMER0 27 PCNT0 28 PCNT1 29 PCNT2 30 RTC 31 BURTC 32 CMU 33 VCMP 34 LCD 35 MSC 36 AES 37 EBI 38 EMU ...

Page 15: ...omous transfers with predictable response time 5 1 Introduction The EFM32GG contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space A multilayer AHB bus matrix using a Round robin arbitration scheme connects the master bus interfaces to the AHB slaves Figure 5 1 p 16 The bus matrix allows several AHB slaves to be accessed simultaneously An AMBA APB interface ...

Page 16: ...gure 5 1 EFM32GG Bus System Cortex AHB Multilayer Bus Matrix DCode System USB DMA Flash RAM EBI AHB APB Bridge ICode AES Peripheral 0 Peripheral n DMA USB 5 2 Functional Description The memory segments are mapped together with the internal segments of the Cortex M3 into the system memory map shown by Figure 5 2 p 17 ...

Page 17: ...AM bit band alias and peripheral bit band alias regions are located at 0x22000000 and 0x42000000 respectively Read and write operations to these regions are converted into masked single bit reads and atomic single bit writes to the embedded SRAM and peripherals of the EFM32GG The standard approach to modify a single register or SRAM bit in the aliased regions requires software to read the value of...

Page 18: ...xed size address range according to Table 5 1 p 18 Table 5 2 p 18 and Table 5 3 p 19 Table 5 1 Memory System Core Peripherals Core peripherals Address Range Module Name 0xE0041000 0xE0080FFF ETM 0x400E0000 0x400E03FF AES 0x400CA000 0x400CA3FF RMU 0x400C8000 0x400C83FF CMU 0x400C6000 0x400C63FF EMU 0x400C4000 0x400C43FF USB 0x400C2000 0x400C3FFF DMA 0x400C0000 0x400C03FF MSC 0x40008000 0x400083FF E...

Page 19: ... the memory segments to the bus masters Code CPU instruction or data fetches from the code space System CPU read and write to the SRAM EBI and peripherals DMA Access to EBI SRAM Flash and peripherals USB DMA Access to EBI SRAM and Flash 5 2 3 1 Arbitration The Bus Matrix uses a round robin arbitration algorithm which enables high throughput and low latency while starvation of simultaneous accesses...

Page 20: ...ncy oscillator and core system is powered off i e in energy mode EM2 and in some cases also EM3 This enables the peripherals to perform tasks while the system energy consumption is minimal The Low Energy Peripherals are Liquid Crystal Display driver LCD Low Energy Timer LETIMER Low Energy UART LEUART Pulse Counter PCNT Real Time Counter RTC Watchdog WDOG Low Energy Sensor Interface LESENSE Backup ...

Page 21: ...cbusy Register n Set 0 Set 1 Set n Freeze Synchronization Done Clear 0 Clear 1 Clear n Core Clock Low Frequency Clock Low Frequency Clock Core Clock Domain Low Frequency Clock Domain 5 3 1 1 2 Immediate synchronization Contrary to the peripherals with delayed synchronization data written to peripherals with immediate synchronization takes effect in the peripheral immediately They are updated immed...

Page 22: ... Low Frequency Clock Low Frequency Clock Core Clock Domain Low Frequency Clock Domain Low Energy Peripheral Main Function HW Status Register 0 HW Status Register 1 HW Status Register m Read Synchronizer Read Data 5 3 2 FREEZE register For Low Energy Peripherals with delayed synchronization there is a module_name _FREEZE register e g RTC_FREEZE containing a bit named REGFREEZE If precise control of...

Page 23: ...ontents DI Address Register Description 0x0FE08020 CMU_LFRCOCTRL Register reset value 0x0FE08028 CMU_HFRCOCTRL Register reset value 0x0FE08030 CMU_AUXHFRCOCTRL Register reset value 0x0FE08040 ADC0_CAL Register reset value 0x0FE08048 ADC0_BIASPROG Register reset value 0x0FE08050 DAC0_CAL Register reset value 0x0FE08058 DAC0_BIASPROG Register reset value 0x0FE08060 ACMP0_CTRL Register reset value 0x...

Page 24: ...x0FE081D6 AUXHFRCO_CALIB_BAND_11 7 0 Tuning for the 11 MHz AUXHFRCO band 0x0FE081D7 AUXHFRCO_CALIB_BAND_14 7 0 Tuning for the 14 MHz AUXHFRCO band 0x0FE081D8 AUXHFRCO_CALIB_BAND_21 7 0 Tuning for the 21 MHz AUXHFRCO band 0x0FE081D9 AUXHFRCO_CALIB_BAND_28 7 0 Tuning for the 28 MHz AUXHFRCO band 0x0FE081DC HFRCO_CALIB_BAND_1 7 0 Tuning for the 1 2 MHz HFRCO band 0x0FE081DD HFRCO_CALIB_BAND_7 7 0 Tun...

Page 25: ...a instruction tracing In addition there is also a Serial Wire Viewer pin which can be used to output profiling information data trace and software generated messages For more technical information about the debug interface the reader is referred to ARM Cortex M3 Technical Reference Manual ARM CoreSight Components Technical Reference Manual ARM Debug Interface v5 Architecture Specification 6 2 Feat...

Page 26: ...Data 3 TD0 TD3 The data pins provide the compressed trace stream These pins are disabled after reset For information on how to configure the ETM see the ARM Embedded Trace Macrocell Architecture Specification The Trace Clock and Trace Data pins can be enabled through the GPIO For more information on how to enable the ETM Trace pins the reader is referred to Section 32 3 4 2 p 762 6 3 3 Debug and E...

Page 27: ...ocked by writing a valid key to the AAP_CMDKEY register and then setting the DEVICEERASE bit of the AAP_CMD register via the debug interface The commands are not executed before AAP_CMDKEY is invalidated so this register should be cleared to to start the erase operation This operation erases the main block of flash all lock bits are reset and debug access through the AHB AP is enabled The operatio...

Page 28: ... to 0 More information in Section 2 1 p 3 1 SYSRESETREQ 0 W1 System Reset Request A system reset request is generated when set to 1 This register is write enabled from the AAP_CMDKEY register 0 DEVICEERASE 0 W1 Erase the Flash Main Block SRAM and Lock Bits When set all data and program code in the main block is erased the SRAM is cleared and then the Lock Bit LB page is erased This also includes t...

Page 29: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name ERASEBUSY Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 ERASEBUSY 0 R Device Erase Command Status This bit is set when a device erase is executing 6 6 4 AAP_IDR AAP Identification Register Offset Bit Position 0x0FC 31 30 29 28 27 26 25...

Page 30: ... the developer the ability to dynamically customize the memory system performance security level energy consumption and error handling capabilities to the requirements at hand How The MSC integrates a low energy Flash IP with a charge pump enabling minimum energy consumption while eliminating the need for external programming voltage to erase the memory An easy to use write and erase interface is ...

Page 31: ...d EM1 Command and status interface Flash write and erase Accessible from Cortex M3 in EM0 DMA write support in EM0 and EM1 Read while write support Write two words at a time Core clock independent Flash timing Internal oscillator and internal timers for precise and autonomous Flash timing General purpose timers are not occupied during Flash erase and write operations Configurable interrupt erase a...

Page 32: ... 4 kB Information 0x0FE09000 Reserved Reserved 0x0FE10000 Reserved for flash expansion Rest of code space 1 Block page erased by a device erase 7 3 1 User Data UD Page Description This is the user data page in the information block The page can be erased and written by software The page is erased by the ERASEPAGE command of the MSC_WRITECMD register Note that the page is not erased by a device era...

Page 33: ...3 7 3 4 Post reset Behavior Calibration values are automatically written to registers by the MSC before application code startup The values are also available to read from the DI page for later reference by software Other information such as the device ID and production date is also stored in the DI page and is readable from software 7 3 4 1 One Wait state Access After reset the HFCORECLK is norma...

Page 34: ...is optimized at the cost of higher energy consumption as the processor fetches more instructions from memory than it actually executes To disable the mode write a 1 to the DISFOLD bit in the NVIC Auxiliary Control Register see the Cortex M3 Technical Reference Manual for details Normally it is expected that this feature is most efficient at core frequencies above 16 MHz Folding is enabled by defau...

Page 35: ...e The range of the performance counters can thus be extended by increasing a counter in the MSC interrupt routine The performance counters only count when a cache lookup is performed If the lookup fails MSC_CACHEMISSES is increased If the lookup is successful MSC_CACHEHITS is increased For example a cache lookup is not performed if the cache is disabled or the code is executed from RAM outside the...

Page 36: ..._WRITECMD register The LADDRIM bit only has to be written once when loading the first address After each word is written the internal address register ADDR will be incremented automatically by 4 The INVADDR bit of the MSC_STATUS register is set if the loaded address is outside the flash and the LOCKED bit of the MSC_STATUS register is set if the page addressed is locked Any attempts to command era...

Page 37: ...nt 7 3 5 3 Low Power Write The maximum write current can also be limited by slowing down write operations by setting LPWRITE in MSC_WRITECTRL For single word writes this has no effect on write time but for consecutive writes the write time doubles LPWRITE cannot be set while WDOUBLE is set 7 3 5 4 Read While Write Reading from the lower half of the flash is possible while writing erasing from the ...

Page 38: ... MSC_LOCK RW Configuration Lock Register 0x040 MSC_CMD W1 Command Register 0x044 MSC_CACHEHITS R Cache Hits Performance Counter 0x048 MSC_CACHEMISSES R Cache Misses Performance Counter 0x050 MSC_TIMEBASE RW Flash Write and Erase Timebase 0x054 MSC_MASSLOCK RW Mass Erase Lock Register 7 5 Register Description 7 5 1 MSC_CTRL Memory System Control Register Offset Bit Position 0x000 31 30 29 28 27 26 ...

Page 39: ...tically invalidated when a write or page erase is performed 3 IFCDIS 0 RW Internal Flash Cache Disable Disable instruction cache for internal flash memory 2 0 MODE 0x1 RW Read Mode If software wants to set a core clock frequency above 16 MHz this register must be set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency When changing to a lower frequency this register can be...

Page 40: ... versa Reading from the same half as a flash write erase will stall the access until the write erase has completed 4 LPERASE 0 RW Low Power Erase When set the erase time doubles while halving the erase current 3 LPWRITE 0 RW Low Power Erase When set write times might double while reducing current consumption 2 WDOUBLE 0 RW Write two words at a time When set two words are written to the flash at a ...

Page 41: ...written to MSC_WDATA within the 30 µs timeout 3 WRITEONCE 0 W1 Word Write Once Trigger Start write of the first word written to MSC_WDATA then add 4 to ADDR and write the next word if available within a 30 µs timeout When ADDR is incremented past the page boundary ADDR is set to the base of the page If WDOUBLE is set two words are required every time and ADDR is incremented by 8 2 WRITEEND 0 W1 En...

Page 42: ...ibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 PCRUNNING 0 R Performance Counters Running This bit is set while the performance counters are running When one performance counter reaches the maximum value this bit is cleared 5 ERASEABORTED 0 R The Current Flash Erase Operation Aborted When set the current erase operation was aborted by interrupt 4 WORDTIMEO...

Page 43: ...ache Misses Overflow Interrupt Flag Set when MSC_CACHEMISSES overflows 2 CHOF 0 R Cache Hits Overflow Interrupt Flag Set when MSC_CACHEHITS overflows 1 WRITE 0 R Write Done Interrupt Read Flag Set when a write is done 0 ERASE 0 R Erase Done Interrupt Read Flag Set when erase is done 7 5 9 MSC_IFS Interrupt Flag Set Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 44: ...che Hits Overflow Interrupt Clear Clear the CHOF interrupt flag 1 WRITE 0 W1 Write Done Interrupt Clear Clear the write done bit 0 ERASE 0 W1 Erase Done Interrupt Clear Clear the erase done bit 7 5 11 MSC_IEN Interrupt Enable Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access RW RW RW RW Name CMOF CHOF WRITE...

Page 45: ...the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 MSC registers are unlocked LOCKED 1 MSC registers are locked Write Operation LOCK 0 Lock MSC registers UNLOCK 0x1B71 Unlock MSC registers 7 5 13 MSC_CMD Command Register Offset Bit Position 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access...

Page 46: ...e cache performance for a particular code section 7 5 15 MSC_CACHEMISSES Cache Misses Performance Counter Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000 Access R Name CACHEMISSES Bit Name Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sectio...

Page 47: ...iven by MSC_TIMEBASE_PERIOD I e 1 1 us or 5 5 us with PERIOD cleared or set respectively The resetvalue of the timebase matches a 14 MHz AUXHFRCO which is the default frequency of the AUXHFRCO 7 5 17 MSC_MASSLOCK Mass Erase Lock Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0001 Access RW Name LOCKKEY Bit Name Reset...

Page 48: ... Memory Access DMA controller performs memory operations independently of the CPU This has the benefit of reducing the energy consumption and the workload of the CPU and enables the system to stay in low energy modes for example when moving data from the USART to RAM or from the External Bus Interface EBI to the DAC The DMA controller uses the PL230 µDMA controller licensed from ARM 1 Each of the ...

Page 49: ...Interrupts upon transfer completion Data transfer to from LEUART in EM2 is supported by the DMA providing extremely low energy consumption while performing UART communications 8 3 Block Diagram An overview of the DMA and the modules it interacts with is shown in Figure 8 1 p 49 Figure 8 1 DMA Block Diagram Interrupts APB block APB memory mapped registers AHB block AHB Lite master interface DMA con...

Page 50: ...e channel descriptor is described in detail in Section 8 4 3 p 61 In addition to the basic transfer mode the DMA Controller also supports two advanced transfer modes ping pong and scatter gather Ping pong transfers are ideally suited for streaming data for high speed peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately while the processor core is s...

Page 51: ...at need to be done is specified by the user When N 2 R and is not an integer multiple of 2 R then the controller always performs sequences of 2 R transfers until N 2 R remain to be transferred The controller performs the remaining N transfers at the end of the DMA cycle You store the value of the R_power bits in the channel control data structure See Section 8 4 3 3 p 64 for more information about...

Page 52: ...igh 3 High 4 High 5 High 6 High 7 High 8 High 9 High 10 High 11 High 0 Default 1 Default 2 Default 3 Default 4 Default 5 Default 6 Default 7 Default 8 Default 9 Default 10 Default 11 Default Lowest priority DMA channel After a DMA transfer completes the controller polls all the DMA channels that are available Figure 8 2 p 53 shows the process it uses to determine which DMA transfer to perform next...

Page 53: ...rol data structure is invalid b001 Basic DMA transfer b010 Auto request b011 Ping pong b100 Memory scatter gather using the primary data structure b101 Memory scatter gather using the alternate data structure b110 Peripheral scatter gather using the primary data structure b111 Peripheral scatter gather using the alternate data structure Note The cycle_ctrl bits are located in the channel_cfg memor...

Page 54: ...ceive a single request to enable it to complete the entire DMA cycle This enables a large data transfer to occur without significantly increasing the latency for servicing higher priority requests or requiring multiple requests from the processor or peripheral You can configure the controller to use either the primary or the alternate data structure After you enable the channel C and the controlle...

Page 55: ...completes provided that a higher priority channel does not require servicing 3 The controller receives a request and performs four DMA transfers 4 The controller arbitrates After the controller receives a request for this channel the flow continues if the channel has the highest priority 5 The controller performs the remaining two DMA transfers 6 The controller sets dma_done C HIGH for one HFCOREC...

Page 56: ...ller performs the remaining DMA transfer 18 The controller sets dma_done C HIGH for one HFCORECLK cycle and enters the arbitration process After the controller receives a new request for the channel and it has the highest priority then task E commences Task E 19 The controller performs four DMA transfers 20 The controller arbitrates After the controller receives a request for this channel the flow...

Page 57: ...b10 Configures the controller to use word increments for the address 29 28 dst_size b10 Configures the controller to use word transfers 27 26 src_inc b10 Configures the controller to use word increments for the address 25 24 src_size b10 Configures the controller to use word transfers 17 14 R_power b0010 Configures the controller to perform four DMA transfers 3 next_useburst 0 For a memory scatter...

Page 58: ...perate in memory scatter gather mode by setting cycle_ctrl to b100 Because a data structure for a single channel consists of four words then you must set 2 R to 4 In this example there are four tasks and therefore N is set to 16 2 The host processor writes the data structure for tasks A B C and D to the memory locations that the primary src_data_end_ptr specifies 3 The host processor enables the c...

Page 59: ...iority then it performs another four DMA transfers using the primary data structure It then immediately starts a DMA cycle using the alternate data structure without re arbitrating The controller continues to switch from primary to alternate to primary until either the host processor configures the alternate data structure for a basic cycle it reads an invalid data structure Note After the control...

Page 60: ...DMA transfer that the alternate channel control data structure specifies 1 Configure primary to enable the copy A B C and D operations cycle_ctrl b110 2R 4 N 16 Initialization 2 Write the primary source data in memory using the structure shown in the following table cycle_ctrl b111 2R 4 N 3 cycle_ctrl b111 2R 2 N 8 cycle_ctrl b111 2R 8 N 5 cycle_ctrl b001 2R 4 N 4 src_data_end_ptr dst_data_end_ptr...

Page 61: ...imary copy D 10 The controller performs four DMA transfers These transfers write the alternate data structure for task D 11 The controller sets the cycle_ctrl bits of the primary data structure to b000 to indicate that this data structure is now invalid Task D 12 The controller performs task D using a basic cycle 13 The controller sets dma_done C HIGH for one HFCORECLK cycle and enters the arbitra...

Page 62: ...s to enable it to access all of the elements in the structure and therefore the base address must be at 0xXXXXXX00 You can configure the base address for the primary data structure by writing the appropriate value in the DMA_CTRLBASE register You do not need to set aside the full 384 bytes if all dma channels are not used or if all alternate descriptors are not used If for example only 4 channels ...

Page 63: ...nnel 11 Primary for channel 1 Primary for channel 0 The controller uses the system memory to enable it to access two pointers and the control information that it requires for each channel The following subsections will describe these 32 bit memory locations and how the controller calculates the DMA transfer address 8 4 3 1 Source data end pointer The src_data_end_ptr memory location contains a poi...

Page 64: ...hannel_cfg bit assignments 31 21 20 13 4 0 dst_inc src_prot_ctrl R_power n_minus_1 next_useburst 30 29 28 27 26 25 24 23 dst_size src_size src_inc dst_prot_ctrl 18 17 cycle_ctrl 3 14 2 Table 8 9 p 64 lists the bit assignments for this memory location Table 8 9 channel_cfg bit assignments Bit Name Description 31 30 dst_inc Destination address increment The address increment depends on the source da...

Page 65: ...This bit has no effect on the DMA Bit 22 This bit has no effect on the DMA Bit 21 Controls the state of HPROT as follows 0 HPROT is LOW and the access is non privileged 1 HPROT is HIGH and the access is privileged 20 18 src_prot_ctrl Set the bits to control the state of HPROT when the controller reads the source data Bit 20 This bit has no effect on the DMA Bit 19 This bit has no effect on the DMA...

Page 66: ...nd dma_sreq when it performs a DMA cycle that uses an alternate data structure 1 the controller sets the chnl_useburst_set C bit to a 1 Therefore for the remaining DMA cycles in the peripheral scatter gather transaction the controller only responds to requests on dma_req when it performs a DMA cycle that uses an alternate data structure 2 0 cycle_ctrl The operating mode of the DMA cycle The modes ...

Page 67: ...A transfer it performs a left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies and then subtracts the resulting value from the destination end pointer Depending on the value of src_inc and dst_inc the source address and destination address can be calculated using the equations src_inc b00 and dst_inc b00 source address src_data_end_ptr n_minus_1 destination address d...

Page 68: ...ta one option is to use ping pong mode alternating between two descriptors and having software update one descriptor while the other is being used Another way is to use looped transfers For DMA channels 0 and 1 looping can be enabled by setting EN in DMA_LOOP0 and DMA_LOOP1 respectively A looping DMA channel will on completion set the respective DONE interrupt flag but then reload n_minus_1 in the...

Page 69: ...ecified by HEIGHT in DMA_RECT0 has been copied The source and destination addresses in the channel descriptor will then point at the last element of the source and destination rectangles On completion the DONE interrupt flag of channel 0 is set Looping is not supported for rectangle copy In some cases e g when performing graphics operations it is desirable to create a list of copy operations and h...

Page 70: ... for transferring 42 bytes from the USART1 to memory location 0x20003420 Assumes that the channel 0 is currently disabled and that the DMA_ALTCTRLBASE register has already been configured Example 8 1 DMA Transfer 1 Configure the channel select for using USART1 with DMA channel 0 a Write SOURCESEL 0b001101 and SIGSEL XX to DMA_CHCTRL0 2 Configure the primary channel descriptor for DMA channel 0 a W...

Page 71: ... Register 0x028 DMA_CHENS RW1 Channel Enable Set Register 0x02C DMA_CHENC W1 Channel Enable Clear Register 0x030 DMA_CHALTS RW1 Channel Alternate Set Register 0x034 DMA_CHALTC W1 Channel Alternate Clear Register 0x038 DMA_CHPRIS RW1 Channel Priority Set Register 0x03C DMA_CHPRIC W1 Channel Priority Clear Register 0x04C DMA_ERRORC RW Bus Error Clear Register 0xE10 DMA_CHREQSTATUS R Channel Request ...

Page 72: ...s 11 15 are undefined Value Mode Description 0 IDLE Idle 1 RDCHCTRLDATA Reading channel controller data 2 RDSRCENDPTR Reading source data end pointer 3 RDDSTENDPTR Reading destination data end pointer 4 RDSRCDATA Reading source data 5 WRDSTDATA Writing destination data 6 WAITREQCLR Waiting for DMA request to clear 7 WRCHCTRLDATA Writing channel controller data 8 STALLED Stalled 9 DONE Done 10 PERS...

Page 73: ...sition 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name CTRLBASE Bit Name Reset Access Description 31 0 CTRLBASE 0x00000000 RW Channel Control Data Base Pointer The base pointer for a location in system memory that holds the channel control data structure This register must be written to point to a location in system memory...

Page 74: ...or wait on request for channel 11 10 CH10WAITSTATUS 1 R Channel 10 Wait on Request Status Status for wait on request for channel 10 9 CH9WAITSTATUS 1 R Channel 9 Wait on Request Status Status for wait on request for channel 9 8 CH8WAITSTATUS 1 R Channel 8 Wait on Request Status Status for wait on request for channel 8 7 CH7WAITSTATUS 1 R Channel 7 Wait on Request Status Status for wait on request ...

Page 75: ...0 W1 Channel 9 Software Request Write 1 to this bit to generate a DMA request for this channel 8 CH8SWREQ 0 W1 Channel 8 Software Request Write 1 to this bit to generate a DMA request for this channel 7 CH7SWREQ 0 W1 Channel 7 Software Request Write 1 to this bit to generate a DMA request for this channel 6 CH6SWREQ 0 W1 Channel 6 Software Request Write 1 to this bit to generate a DMA request for ...

Page 76: ...7 Useburst Set See description for channel 0 6 CH6USEBURSTS 0 RW1H Channel 6 Useburst Set See description for channel 0 5 CH5USEBURSTS 0 RW1H Channel 5 Useburst Set See description for channel 0 4 CH4USEBURSTS 0 RW1H Channel 4 Useburst Set See description for channel 0 3 CH3USEBURSTS 0 RW1H Channel 3 Useburst Set See description for channel 0 2 CH2USEBURSTS 0 RW1H Channel 2 Useburst Set See descri...

Page 77: ...useburst setting for this channel 9 CH9USEBURSTC 0 W1 Channel 9 Useburst Clear Write to 1 to disable useburst setting for this channel 8 CH08USEBURSTC 0 W1 Channel 8 Useburst Clear Write to 1 to disable useburst setting for this channel 7 CH7USEBURSTC 0 W1 Channel 7 Useburst Clear Write to 1 to disable useburst setting for this channel 6 CH6USEBURSTC 0 W1 Channel 6 Useburst Clear Write to 1 to dis...

Page 78: ... this channel 9 CH9REQMASKS 0 RW1 Channel 9 Request Mask Set Write to 1 to disable peripheral requests for this channel 8 CH8REQMASKS 0 RW1 Channel 8 Request Mask Set Write to 1 to disable peripheral requests for this channel 7 CH7REQMASKS 0 RW1 Channel 7 Request Mask Set Write to 1 to disable peripheral requests for this channel 6 CH6REQMASKS 0 RW1 Channel 6 Request Mask Set Write to 1 to disable...

Page 79: ...s channel 9 CH9REQMASKC 0 W1 Channel 9 Request Mask Clear Write to 1 to enable peripheral requests for this channel 8 CH8REQMASKC 0 W1 Channel 8 Request Mask Clear Write to 1 to enable peripheral requests for this channel 7 CH7REQMASKC 0 W1 Channel 7 Request Mask Clear Write to 1 to enable peripheral requests for this channel 6 CH6REQMASKC 0 W1 Channel 6 Request Mask Clear Write to 1 to enable per...

Page 80: ...nel 7 CH7ENS 0 RW1 Channel 7 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 6 CH6ENS 0 RW1 Channel 6 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 5 CH5ENS 0 RW1 Channel 5 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 4 CH4ENS 0 RW1 Channel 4 Enable Set Wri...

Page 81: ...See also description for channel 0 2 CH2ENC 0 W1 Channel 2 Enable Clear Write to 1 to disable this channel See also description for channel 0 1 CH1ENC 0 W1 Channel 1 Enable Clear Write to 1 to disable this channel See also description for channel 0 0 CH0ENC 0 W1 Channel 0 Enable Clear Write to 1 to disable this channel Note that the controller disables a channel by setting the appropriate bit when...

Page 82: ...lect the alternate structure for this channel 0 CH0ALTS 0 RW1 Channel 0 Alternate Structure Set Write to 1 to select the alternate structure for this channel 8 7 14 DMA_CHALTC Channel Alternate Clear Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name C...

Page 83: ...uture devices always write bits to 0 More information in Section 2 1 p 3 11 CH11PRIS 0 RW1 Channel 11 High Priority Set Write to 1 to obtain high priority for this channel Reading returns the channel priority status 10 CH10PRIS 0 RW1 Channel 10 High Priority Set Write to 1 to obtain high priority for this channel Reading returns the channel priority status 9 CH9PRIS 0 RW1 Channel 9 High Priority S...

Page 84: ...formation in Section 2 1 p 3 11 CH11PRIC 0 W1 Channel 11 High Priority Clear Write to 1 to clear high priority for this channel 10 CH10PRIC 0 W1 Channel 10 High Priority Clear Write to 1 to clear high priority for this channel 9 CH9PRIC 0 W1 Channel 9 High Priority Clear Write to 1 to clear high priority for this channel 8 CH8PRIC 0 W1 Channel 8 High Priority Clear Write to 1 to clear high priorit...

Page 85: ...his DMA channel is requesting the controller to service the DMA channel The controller services the request by performing the DMA cycle using 2 R DMA transfers 10 CH10REQSTATUS 0 R Channel 10 Request Status When this bit is 1 it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel The controller services the request by per...

Page 86: ...STATUS Channel Single Request Status Offset Bit Position 0xE18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R R R Name CH11SREQSTATUS CH10SREQSTATUS CH9SREQSTATUS CH8SREQSTATUS CH7SREQSTATUS CH6SREQSTATUS CH5SREQSTATUS CH4SREQSTATUS CH3SREQSTATUS CH2SREQSTATUS CH1SREQSTATUS CH0SREQSTATUS Bit Name Reset ...

Page 87: ...ransfers 0 CH0SREQSTATUS 0 R Channel 0 Single Request Status When this bit is 1 it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel The controller services the request by performing the DMA cycle using single DMA transfers 8 7 20 DMA_IF Interrupt Flag Register Offset Bit Position 0x1000 31 30 29 28 27 26 25 24 23 22 21...

Page 88: ...cess W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name ERR CH11DONE CH10DONE CH9DONE CH8DONE CH7DONE CH6DONE CH5DONE CH4DONE CH3DONE CH2DONE CH1DONE CH0DONE Bit Name Reset Access Description 31 ERR 0 W1 DMA Error Interrupt Flag Set Set to 1 to set DMA error interrupt flag 30 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 CH11DONE 0 W...

Page 89: ...rupt flag 10 CH10DONE 0 W1 DMA Channel 10 Complete Interrupt Flag Clear Write to 1 to clear the corresponding DMA channel complete interrupt flag 9 CH9DONE 0 W1 DMA Channel 9 Complete Interrupt Flag Clear Write to 1 to clear the corresponding DMA channel complete interrupt flag 8 CH8DONE 0 W1 DMA Channel 8 Complete Interrupt Flag Clear Write to 1 to clear the corresponding DMA channel complete int...

Page 90: ... the interrupt 8 CH8DONE 0 RW DMA Channel 8 Complete Interrupt Enable Write to 1 to enable complete interrupt on this DMA channel Clear to disable the interrupt 7 CH7DONE 0 RW DMA Channel 7 Complete Interrupt Enable Write to 1 to enable complete interrupt on this DMA channel Clear to disable the interrupt 6 CH6DONE 0 RW DMA Channel 6 Complete Interrupt Enable Write to 1 to enable complete interrup...

Page 91: ...y with future devices always write bits to 0 More information in Section 2 1 p 3 11 RDSCH11 0 RW Retain Descriptor State Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous 10 RDSCH10 0 RW Retain Descriptor State Speed up execution of consecutive DMA requests from the ...

Page 92: ...tor at the start of every arbitration cycle if the next channel is the same as the previous 1 RDSCH1 0 RW Retain Descriptor State Speed up execution of consecutive DMA requests from the same channel by not reading descriptor at the start of every arbitration cycle if the next channel is the same as the previous 0 RDSCH0 0 RW Retain Descriptor State Speed up execution of consecutive DMA requests fr...

Page 93: ...uture devices always write bits to 0 More information in Section 2 1 p 3 9 0 WIDTH 0x000 RW DMA Channel 1 Loop Width Reload value for N_MINUS_1 when loop is enabled 8 7 28 DMA_RECT0 Channel 0 Rectangle Register Offset Bit Position 0x1060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 0x000 0x000 Access RW RWH RWH Name DSTSTRIDE SRCSTRIDE HEIGHT Bi...

Page 94: ...ynchronous Receiver Transmitter 2 0b010000 LEUART0 Low Energy UART 0 0b010001 LEUART1 Low Energy UART 1 0b010100 I2C0 I2C 0 0b010101 I2C1 I2C 1 0b011000 TIMER0 Timer 0 0b011001 TIMER1 Timer 1 0b011010 TIMER2 Timer 2 0b011011 TIMER3 Timer 3 0b101100 UART0 Universal Asynchronous Receiver Transmitter 0 0b101101 UART1 Universal Asynchronous Receiver Transmitter 1 0b110000 MSC 0b110001 AES Advanced Enc...

Page 95: ...RT0TXEMPTY SOURCESEL 0b010001 LEUART1 0b0000 LEUART1RXDATAV LEUART1RXDATAV 0b0001 LEUART1TXBL LEUART1TXBL 0b0010 LEUART1TXEMPTY LEUART1TXEMPTY SOURCESEL 0b010100 I2C0 0b0000 I2C0RXDATAV I2C0RXDATAV 0b0001 I2C0TXBL I2C0TXBL SOURCESEL 0b010101 I2C1 0b0000 I2C1RXDATAV I2C1RXDATAV 0b0001 I2C1TXBL I2C1TXBL SOURCESEL 0b011000 TIMER0 0b0000 TIMER0UFOF TIMER0UFOF 0b0001 TIMER0CC0 TIMER0CC0 0b0010 TIMER0CC...

Page 96: ...UART1TXBL REQ SREQ 0b0010 UART1TXEMPTY UART1TXEMPTY SOURCESEL 0b110000 MSC 0b0000 MSCWDATA MSCWDATA SOURCESEL 0b110001 AES 0b0000 AESDATAWR AESDATAWR 0b0001 AESXORDATAWR AESXORDATAWR 0b0010 AESDATARD AESDATARD 0b0011 AESKEYWR AESKEYWR SOURCESEL 0b110010 LESENSE 0b0000 LESENSEBUFDATAV LESENSEBUFDATAV REQ SREQ SOURCESEL 0b110011 EBI 0b0000 EBIPXL0EMPTY EBIPXL0EMPTY 0b0001 EBIPXL1EMPTY EBIPXL1EMPTY 0...

Page 97: ...tionally low power consumption The cause of the reset may be read from a register thus providing software with information about the cause of the reset 9 1 Introduction The RMU is responsible for handling the reset functionality of the EFM32GG 9 2 Features Reset sources Power on Reset POR Brown out Detection BOD on the following power domains Regulated domain Unregulated domain Analog Power Domain...

Page 98: ...nections SYSREQRST WDOG Reset Management Unit PORESETn SYSRESETn LOCKUP POWERONn BROWNOUT_UNREGn RESETn Filter LOCKUPRDIS VDD POR BOD Core Debug Interface Cortex Peripherals VDD_REGULATED RMU_RSTCAUSE BROWNOUT_REGn RCCLR Edge to pulse filter BOD AVDD0 BROWNOUT_AVDD0 BOD AVDD1 BROWNOUT_AVDD1 BOD EM4 wakeup em4 Backup mode Backup mode exit 9 3 1 RMU_RSTCAUSE Register The RMU_RSTCAUSE register indica...

Page 99: ...G 0bXXX1 XXXX XXXX 0XX0 A Brown out has been detected by the Backup BOD on BU_VIN 0bXX1X XXXX XXXX 0XX0 A Brown out has been detected by the Backup BOD on unregulated power 0bX1XX XXXX XXXX 0XX0 A Brown out has been detected by the Backup BOD on regulated power 0b1XXX XXXX XXXX XXX0 The system has been in Backup mode Note When exiting EM4 with external reset both the BODREGRST and BODUNREGRST in R...

Page 100: ...h prevents glitches from resetting the EFM32GG 9 3 5 Watchdog Reset The Watchdog circuit is a timer which when enabled must be cleared by software regularly If software does not clear it a Watchdog reset is activated This functionality provides recovery from a software stalemate Refer to the Watchdog section for specifications and description 9 3 6 Lockup Reset A Cortex M3 lockup is the result of ...

Page 101: ...1 20 101 www silabs com 9 3 9 EM4 Wakeup Reset Whenever the system is woken up from EM4 on a pin wake up request the EM4WURST bit is set This bit enables the user to identify that the device was woken up from EM4 using a pin wake up request Upon wake up this bit should be cleared by software ...

Page 102: ...it to disable the LOCKUP signal from the Cortex from resetting the device 9 5 2 RMU_RSTCAUSE Reset Cause Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R R R R R R R Name BUMODERST BUBODREG BUBODUNREG BUBODBUVIN BUBODVDDDREG BODAVDD1 BODAVDD0 EM4WURST EM4RST SYSR...

Page 103: ...n EM4 Must be cleared by software Please see Table 9 1 p 99 for details on how to interpret this bit 6 SYSREQRST 0 R System Request Reset Set if a system request reset has been performed Must be cleared by software Please see Table 9 1 p 99 for details on how to interpret this bit 5 LOCKUPRST 0 R LOCKUP Reset Set if a LOCKUP reset has been requested Must be cleared by software Please see Table 9 1...

Page 104: ...et Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 RCCLR 0 W1 Reset Cause Clear Set this bit to clear the LOCKUPRST and SYSREQRST bits in the RMU_RSTCAUSE register Use the HRCCLR bit in the EMU_AUXCTRL register to clear the remaining bits ...

Page 105: ...32GG microcontrollers Each energy mode manages if the CPU and the various peripherals are available The energy modes range from EM0 to EM4 where EM0 also called run mode enables the CPU and all peripherals The lowest recoverable energy mode EM3 disables the CPU and most peripherals while maintaining wake up and RAM functionality EM4 disables everything except the POR pin reset and optionally Backu...

Page 106: ...gy mode in which any peripheral function can be enabled and the Cortex M3 core is executing instructions EM1 through EM4 also called low energy modes provide a selection of reduced peripheral functionality that also lead to reduced energy consumption as described below Figure 10 2 p 107 shows the transitions between different energy modes After reset the EMU will always start in EM0 A transition f...

Page 107: ...er on reset EM4 wakeup BURTC interrupt No direct transitions between EM1 EM2 or EM3 are available as can also be seen from Figure 10 2 p 107 Instead a wakeup will transition back to EM0 in which software can enter any other low energy mode An overview of the supported energy modes and the functionality available in each mode is shown in Table 10 1 p 108 Most peripheral functionality indicated as O...

Page 108: ...On On On On ACMP On On On On I 2 C receive address recognition On On On On Watchdog On On On On 3 Pin interrupts On On On On RAM voltage regulator RAM retention On On On On Brown Out Reset On On On On Power On Reset On On On On On Pin Reset On On On On On GPIO state retention On On On On On 4 EM4 Reset Wakeup Request On 4 Backup RTC On On On On On Backup retention registers On On On On On 1 Energy...

Page 109: ...om Backup RTC interrupt external pin reset or pins that support EM4 wakeup 10 3 2 Entering a Low Energy Mode A low energy mode is entered by first configuring the desired Energy Mode through the EMU_CTRL register and the SLEEPDEEP bit in the Cortex M3 System Control Register see Table 10 2 p 110 A Wait For Interrupt WFI or Wait For Event WFE instruction from the Cortex M3 triggers the transition i...

Page 110: ... WFE EM2 0 0 0 1 WFI or WFE EM4 Write sequence 2 3 2 3 2 3 2 3 2 x x x x x means don t care 10 3 3 Leaving a Low Energy Mode In each low energy mode a selection of peripheral units are available and software can either enable or disable the functionality Enabled interrupts that can cause wakeup from a low energy mode are shown in Table 10 3 p 111 The wakeup triggers always return the EFM32 to EM0 ...

Page 111: ...bled edge interrupt Yes Yes Yes VCMP Any enabled edge interrupt Yes Yes Yes Pin interrupts Asynchronous Yes Yes Yes Pin Reset Yes Yes Yes Yes EM4 wakeup on supported pins Asynchronous Yes Backup RTC Any enabled interrupt Yes Yes Yes Yes Yes Power Cycle Off On Yes Yes Yes Yes 1 Energy Mode 0 Active Mode 2 Energy mode 1 2 3 4 3 When the 1 kHz ULFRCO is selected 4 When using an external clock 10 3 4 ...

Page 112: ...he RSTCAUSE register in the RMU are set when the associated BOD triggers The locations of the Backup BODs are indicated in Figure 10 3 p 112 A brown out on the main power supply will trigger a switch to the backup power supply if the backup functionality is enabled and the BOD sensing on the backup power supply has not triggered The two other BODs are used for error indication and will only set th...

Page 113: ...ackup mode has been active the BURST bit in RMU_RSTCAUSE is set Figure 10 4 Entering and leaving backup mode EMU_BUACT_BUEXRANGE EMU_BUACT_BUEXTHRES VDDREG Time Backup mode active EMU_BUINACT_BUENRANGE EMU_BUINACT_BUENTHRES Figure 10 4 p 113 illustrates how the BOD sensing on VDD_DREG can be programmed to implement hysteresis on entering and exiting backup mode 10 3 4 5 Threshold calibration The t...

Page 114: ...WRRES in EMU_PWRCONF this configuration applies both to backup mode and normal mode 10 3 4 7 Supply voltage output To be able to power external devices the supply voltage for the backup domain is available as an output Three switches connect the backup supply voltage to the BU_VOUT pin To be able to control the series resistance the switches have different strengths weak medium and strong The swit...

Page 115: ...o enable the Backup RTC to be powered from the regulator making sure it survives a watchdog reset 10 3 4 10 1 Oscillators in EM4 When the system is in EM4 or backup mode with the voltage regulator enabled the ULFRCO is by default enabled If the LFXO or LFRCO is used by the Backup RTC the ULFRCO can be shut down to reduce power consumption To do this configure the OSC bitfield in EMU_EM4CONF Note I...

Page 116: ... the world s most energy friendly microcontrollers 2016 04 28 Giant Gecko Family d0053_Rev1 20 116 www silabs com All the blocks can be turned off except the first one ...

Page 117: ...RW Interrupt Enable Register 0x058 EMU_BUBODBUVINCAL RW BU_VIN Backup BOD calibration 0x05C EMU_BUBODUNREGCAL RW Unregulated power Backup BOD calibration 10 5 Register Description 10 5 1 EMU_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 Access RW RW RW Name EM4CTRL EM2BLOCK EMVREG Bit Name Reset A...

Page 118: ... down Value Mode Description 4 BLK3 Power down RAM block 3 address range 0x20018000 0x2001FFFF 6 BLK23 Power down RAM blocks 2 3 address range 0x20010000 0x2001FFFF 7 BLK123 Power down RAM blocks 1 3 address range 0x20008000 0x2001FFFF 10 5 3 EMU_LOCK Configuration Lock Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x...

Page 119: ... Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 0 0 Access RW RW RW RW RW Name LOCKCONF BUBODRSTDIS OSC BURTCWU VREGEN Bit Name Reset Access Description 31 17 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 16 LOCKCONF 0 RW EM4 configuration lock enable Lock regulator...

Page 120: ...SABLE Disable voltage probe 1 VDDDREG Connect probe to VDD_DREG 2 BUIN Connect probe to BU_IN 3 BUOUT Connect probe to BU_OUT 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 BUMODEBODEN 0 RW Enable brown out detection on BU_VIN when in backup mode When set a reset and switch back to main power will be performed when in backup mode...

Page 121: ...register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x1 0x3 Access RW RW RW Name PWRCON BUENRANGE BUENTHRES Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 5 PWRCON 0x0 RW Power connection configuration when not in B...

Page 122: ...nnected through a diode allowing current to flow from main power source to backup power source but not the other way 3 NODIODE Main power and backup power are connected without diode 4 3 BUEXRANGE 0x1 RW Threshold range for Backup BOD sensing on VDD_DREG when in backup mode This field is set to the threshold range calibrated during production hence the reset value might differ from device to devic...

Page 123: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name BURDY Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 BURDY 0 R Backup functionality ready Interrupt Flag Set when the Backup functionality is ready for use 10 5 13 EMU_IFS Interrupt Flag Set Registe...

Page 124: ...11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name BURDY Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 BURDY 0 RW Backup functionality ready Interrupt Enable Enable interrupt when Backup functionality is ready 10 5 16 EMU_BUBODBUVINCAL BU_VIN Backup BOD calibration Offset Bit Position 0x058 31 ...

Page 125: ... 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x1 0x3 Access RW RW Name RANGE THRES Bit Name Reset Access Description 31 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 3 RANGE 0x1 RW Threshold range for Backup BOD sensing on unregulated power This field is set to the threshold range calibrated during production hence t...

Page 126: ...r the different clocks The short oscillator start up times makes duty cycling between active mode and the different low energy modes EM2 EM4 very efficient The calibration feature ensures high accuracy RC oscillators Several interrupts are available to avoid CPU polling of flags 11 1 Introduction The Clock Management Unit CMU is responsible for controlling the oscillators and clocks on board the E...

Page 127: ... individual basis to core modules and all peripherals Selectable clocks can be output on two pins for use externally Auxiliary 1 28 MHz RC oscillator AUXHFRCO for flash programming and debug trace and LESENSE timing 11 3 Functional Description An overview of the CMU is shown in Figure 11 1 p 128 The number of peripheral modules that are connected to the different clocks varies from device to devic...

Page 128: ...NTnCLK PCNTn_S0 WDOG WDOG_CTRL CLKSEL CMU_LFCLKSEL LFB LFBE CMU_LFCLKSEL LFA LFAE CMU_LFBCLKEN0 LEUART1 CMU_LCDCTRL FDIV CMU_HFPERCLKDIV HFPERCLKDIV CMU_HFCORECLKDIV CMU_LFBPRESC0 LEUART1 CMU_LFBPRESC0 LEUART0 CMU_LFAPRESC0 LCD CMU_LFAPRESC0 LETIMER0 CMU_LFAPRESC0 RTC CMU_PCNTCTRL PCNTnCLKSEL LFACLKLCDpre AUXHFRCO Debug Trace MSC Flash Programming Timeout AUXCLK WDOGCLK CMU_CMD HFCLKSEL clock swit...

Page 129: ... by reading CMU_STATUS The clock switch can take up to 1 5 32 kHz cycle 45 us To avoid polling the clock selection status when switching from 32 kHz to HFCLK when coming up from EM2 the USBCHFCLKSEL interrupt can be used EM3 is not supported when the USB is active Note Note that if HFPERCLK runs faster than HFCORECLK the number of clock cycles for each bus access to peripheral modules will increas...

Page 130: ...an be configured to use an external pin PCNTn_S0 or LFACLK as PCNTnCLK 11 3 1 7 WDOGCLK Watchdog Timer Clock The Watchdog Timer WDOG can be configured to use one of three different clock sources LFRCO LFXO or ULFRCO ULFRCO Ultra Low Frequency RC Oscillator is a separate 1 kHz RC oscillator that also runs in EM3 11 3 1 8 AUXCLK Auxiliary Clock AUXCLK is a 1 28 MHz clock driven by a separate RC osci...

Page 131: ...or a description of the sequence of events for this specific operation Note It is important first to enable the HFXO since switching to a disabled oscillator will effectively stop HFCLK and only a reset can recover the system During the start up period HFCLK will stop since the oscillator driving it is not ready This effectively stalls the Core Modules and the High Frequency Peripherals It is poss...

Page 132: ...ors not in use 11 3 3 Oscillator Configuration 11 3 3 1 HFXO and LFXO The crystal oscillators are by default configured to ensure safe startup and operation of the most common crystals In order to optimize startup margin startup time and power consumption for a given crystal it is possible to adjust the gain in the oscillator HFXO gain can be increased by setting HFXOBOOST field in CMU_CTRL LFXO g...

Page 133: ...lds in CMU_HFRCOCTRL CMU_AUXHFRCOCTRL CMU_LFRCOCTRL Changing to a higher value will result in a higher frequency Please refer to the datasheet for stepsize details The CMU has built in HW support to efficiently calibrate the RC oscillators at run time see Figure 11 6 p 134 The concept is to select a reference and compare the RC frequency with the reference frequency When the calibration circuit is...

Page 134: ...ith top value in continouous mode Take snapshot of up counter in up counter bufffer If in continouous mode restart up counter from 0 The counter operation for single and continuous mode are shown in Figure 11 7 p 134 and Figure 11 8 p 134 respectively Figure 11 7 Single Calibration CONT 0 TOP 0 Calibration Started Calibration Stopped counters stopped 0 Down counter Up counter Up counter sampled an...

Page 135: ...ing at 32 MHz or below the default value BOOSTUPTO32MHZ should be used HFLE in CMU_CTRL is only required for frequencies above 32 MHz and ensures correct operation of LE peripherals The CMU_CTRL_HFLE is or ed with HFCORECLKLEDIV in CMU_HFCORECLKDIV so setting either of this bits will reduce the the frequency of CMU_HFCORECLKLEDIV2 11 3 5 Output Clock on a Pin It is possible to configure the CMU to...

Page 136: ...r 0x028 CMU_LFCLKSEL RW Low Frequency Clock Select Register 0x02C CMU_STATUS R Status Register 0x030 CMU_IF R Interrupt Flag Register 0x034 CMU_IFS W1 Interrupt Flag Set Register 0x038 CMU_IFC W1 Interrupt Flag Clear Register 0x03C CMU_IEN RW Interrupt Enable Register 0x040 CMU_HFCORECLKEN0 RW High Frequency Core Clock Enable Register 0 0x044 CMU_HFPERCLKEN0 RW High Frequency Peripheral Clock Enab...

Page 137: ...re information in Section 2 1 p 3 28 DBGCLK 0 RW Debug Clock Select clock used for the debug system Value Mode Description 0 AUXHFRCO AUXHFRCO is the debug clock 1 HFCLK The system clock is the debug clock 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 26 23 CLKOUTSEL1 0x0 RW Clock Output Select 1 Controls the clock output multipl...

Page 138: ...XOTIMEOUT 0x3 RW HFXO Timeout Configures the start up delay for HFXO Value Mode Description 0 8CYCLES Timeout period of 8 cycles 1 256CYCLES Timeout period of 256 cycles 2 1KCYCLES Timeout period of 1024 cycles 3 16KCYCLES Timeout period of 16384 cycles 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 HFXOGLITCHDETEN 0 RW HFXO Glit...

Page 139: ...0 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 Access RW RW Name HFCORECLKLEDIV HFCORECLKDIV Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 HFCORECLKLEDIV 0 RW Additional Division Factor For HFCORECLKLE Additional division factor for HFCORECLKLE When running at frequencies higher than 32 MHz this must be s...

Page 140: ...CLK Divider Specifies the clock divider for the HFPERCLK Value Mode Description 0 HFCLK HFPERCLK HFCLK 1 HFCLK2 HFPERCLK HFCLK 2 2 HFCLK4 HFPERCLK HFCLK 4 3 HFCLK8 HFPERCLK HFCLK 8 4 HFCLK16 HFPERCLK HFCLK 16 5 HFCLK32 HFPERCLK HFCLK 32 6 HFCLK64 HFPERCLK HFCLK 64 7 HFCLK128 HFPERCLK HFCLK 128 8 HFCLK256 HFPERCLK HFCLK 256 9 HFCLK512 HFPERCLK HFCLK 512 11 5 4 CMU_HFRCOCTRL HFRCO Control Register O...

Page 141: ...t the TUNING value bits 7 0 when changing band 7 0 TUNING 0x80 RW HFRCO Tuning Value Writing this field adjusts the HFRCO frequency the higher value the higher frequency This field is updated with the production calibrated value for the 14 MHz band during reset and the reset value might therefore vary between devices 11 5 5 CMU_LFRCOCTRL LFRCO Control Register Offset Bit Position 0x010 31 30 29 28...

Page 142: ... MHz band NOTE Also set the TUNING value bits 7 0 when changing band 7 0 TUNING 0x80 RW AUXHFRCO Tuning Value Writing this field adjusts the AUXHFRCO frequency the higher value the higher frequency This field is updated with the production calibrated value during reset and the reset value might therefore vary between devices 11 5 7 CMU_CALCTRL Calibration Control Register Offset Bit Position 0x018...

Page 143: ...25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name LFXODIS LFXOEN LFRCODIS LFRCOEN AUXHFRCODIS AUXHFRCOEN HFXODIS HFXOEN HFRCODIS HFRCOEN Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 LFXODIS 0 W1 LFXO Disab...

Page 144: ...me Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 5 USBCCLKSEL 0x0 W1 USB Core Clock Select Selects the clock for HFCORECLKUSBC The status register is updated when the clock switch has taken effect Value Mode Description 1 HFCLKNODIV Select HFCLK undivided as HFCORECLKUSBC 2 LFXO Select LFXO as HFCOREC...

Page 145: ...its to 0 More information in Section 2 1 p 3 16 LFAE 0 RW Clock Select for LFA Extended This bit redefines the meaning of the LFA field Value Mode Description 0 DISABLED LFACLK is disabled when LFA DISABLED 1 ULFRCO ULFRCO selected as LFACLK when LFA DISABLED 15 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 2 LFB 0x1 RW Clock Se...

Page 146: ...XO is selected and active as HFCORECLKUSBC 15 USBCHFCLKSEL 0 R USBC HFCLK Selected HFCLK is selected and active as HFCORECLKUSBC 14 CALBSY 0 R Calibration Busy Calibration is on going 13 LFXOSEL 0 R LFXO Selected LFXO is selected as HFCLK clock source 12 LFRCOSEL 0 R LFRCO Selected LFRCO is selected as HFCLK clock source 11 HFXOSEL 0 R HFXO Selected HFXO is selected as HFCLK clock source 10 HFRCOS...

Page 147: ...FCLK is selected as HFCORECLKUSBC 6 CALOF 0 R Calibration Overflow Interrupt Flag Set when calibration overflow has occurred 5 CALRDY 0 R Calibration Ready Interrupt Flag Set when calibration is completed 4 AUXHFRCORDY 0 R AUXHFRCO Ready Interrupt Flag Set when AUXHFRCO is ready start up time exceeded 3 LFXORDY 0 R LFXO Ready Interrupt Flag Set when LFXO is ready start up time exceeded 2 LFRCORDY ...

Page 148: ...Set Write to 1 to set the HFRCO Ready Interrupt Flag 11 5 15 CMU_IFC Interrupt Flag Clear Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name USBCHFCLKSEL CALOF CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY Bit Name Reset Access Description 31 8 Reserved To ensure c...

Page 149: ...t Enable Set to enable the USBC HFCLK Selected Interrupt 6 CALOF 0 RW Calibration Overflow Interrupt Enable Set to enable the Calibration Overflow Interrupt 5 CALRDY 0 RW Calibration Ready Interrupt Enable Set to enable the Calibration Ready Interrupt 4 AUXHFRCORDY 0 RW AUXHFRCO Ready Interrupt Enable Set to enable the AUXHFRCO Ready Interrupt 3 LFXORDY 0 RW LFXO Ready Interrupt Enable Set to enab...

Page 150: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DAC0 ADC0 PRS VCMP GPIO I2C1 I2C0 ACMP1 ACMP0 TIMER3 TIMER2 TIMER1 TIMER0 UART1 UART0 USART2 USART1 USART0 Bit Name Reset Access Description 31 18 Reserved To ensure compatibility with future devices always write b...

Page 151: ...nous Receiver Transmitter 0 Clock Enable Set to enable the clock for USART0 11 5 19 CMU_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access R R R R Name LFBPRESC0 LFBCLKEN0 LFAPRESC0 LFACLKEN0 Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future dev...

Page 152: ... Name REGFREEZE Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 REGFREEZE 0 RW Register Update Freeze When set the update of the Low Frequency clock control registers is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE E...

Page 153: ...eset 0 0 Access RW RW Name LEUART1 LEUART0 Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 LEUART1 0 RW Low Energy UART 1 Clock Enable Set to enable the clock for LEUART1 0 LEUART0 0 RW Low Energy UART 0 Clock Enable Set to enable the clock for LEUART0 11 5 23 CMU_LFAPRESC0 Low Frequency A Pres...

Page 154: ...LFACLKLETIMER0 LFACLK 8192 14 DIV16384 LFACLKLETIMER0 LFACLK 16384 15 DIV32768 LFACLKLETIMER0 LFACLK 32768 7 4 RTC 0x0 RW Real Time Counter Prescaler Configure Real Time Counter prescaler Value Mode Description 0 DIV1 LFACLKRTC LFACLK 1 DIV2 LFACLKRTC LFACLK 2 2 DIV4 LFACLKRTC LFACLK 4 3 DIV8 LFACLKRTC LFACLK 8 4 DIV16 LFACLKRTC LFACLK 16 5 DIV32 LFACLKRTC LFACLK 32 6 DIV64 LFACLKRTC LFACLK 64 7 D...

Page 155: ... compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 0 LEUART0 0x0 RW Low Energy UART 0 Prescaler Configure Low Energy UART 0 prescaler Value Mode Description 0 DIV1 LFBCLKLEUART0 LFBCLK 1 DIV2 LFBCLKLEUART0 LFBCLK 2 2 DIV4 LFBCLKLEUART0 LFBCLK 4 3 DIV8 LFBCLKLEUART0 LFBCLK 8 11 5 25 CMU_PCNTCTRL PCNT Control Register Offset Bit Position 0x078 31 30 29 28...

Page 156: ...PCNT0 1 PCNT0S0 External pin PCNT0_S0 is clocking PCNT0 0 PCNT0CLKEN 0 RW PCNT0 Clock Enable This bit enables disables the clock to the PCNT Value Description 0 PCNT0 is disabled 1 PCNT0 is enabled 11 5 26 CMU_LCDCTRL LCD Control Register Offset Bit Position 0x07C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x2 0 0x0 Access RW RW RW Name VBFDIV VBOOS...

Page 157: ...10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 Access RW RW RW Name LOCATION CLKOUT1PEN CLKOUT0PEN Bit Name Reset Access Description 31 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 2 LOCATION 0x0 RW I O Location Decides the location of the CMU I O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 1 CLKOUT1...

Page 158: ...DIV CMU_HFRCOCTRL CMU_LFRCOCTRL CMU_AUXHFRCOCTRL CMU_OSCENCMD CMU_CMD CMU_LFCLKSEL CMU_HFCORECLKEN0 CMU_HFPERCLKEN0 CMU_LFACLKEN0 CMU_LFBCLKEN0 CMU_LFAPRESC0 CMU_LFBPRESC0 and CMU_PCNTCTRL from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Operation UNLOCKED 0 CMU registers are unlocked LOCKED 1 CMU registers are...

Page 159: ...liability The failure may e g be caused by an external event such as an ESD pulse or by a software failure 12 2 Features Clock input from selectable oscillators Internal 32 768 Hz RC oscillator Internal 1 kHz RC oscillator External 32 768 Hz XTAL oscillator Configurable timeout period from 9 to 256k watchdog clock cycles Individual selection to keep running or freeze when entering EM2 or EM3 Selec...

Page 160: ...the watchdog will continue counting where it left off 12 3 3 Energy Mode Handling The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3 The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in WDOG_CTRL When the watchdog has been frozen and is re entering an energy mode where it is running the watchdog timer will conti...

Page 161: ...s to 0 More information in Section 2 1 p 3 13 12 CLKSEL 0x0 RW Watchdog Clock Select Selects the WDOG oscillator i e the clock on which the watchdog will run Value Mode Description 0 ULFRCO ULFRCO 1 LFRCO LFRCO 2 LFXO LFXO 11 8 PERSEL 0xF RW Watchdog Timeout Period Select Select watchdog timeout period Value Description 0 Timeout period of 9 watchdog clock cycles 1 Timeout period of 17 watchdog cl...

Page 162: ...be entered 4 LOCK 0 RW Configuration lock Set to lock the watchdog configuration This bit can only be cleared by reset Value Description 0 Watchdog configuration can be changed 1 Watchdog configuration cannot be changed 3 EM3RUN 0 RW Energy Mode 3 Run Enable Set to keep watchdog running in EM3 Value Description 0 Watchdog timer is frozen in EM3 1 Watchdog timer is running in EM3 2 EM2RUN 0 RW Ener...

Page 163: ...on 0 UNCHANGED Watchdog timer is unchanged 1 CLEARED Watchdog timer is cleared to 0 12 5 3 WDOG_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access R R Name CMD CTRL Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 Mor...

Page 164: ...s are called producers The PRS routes these reflex signals to consumer peripherals which apply actions depending on the reflex signals received The format for the reflex signals is not given but edge triggers and other functionality can be applied by the PRS 13 2 Features 12 configurable interconnect channels Each channel can be connected to any producing peripheral Consumers can choose which chan...

Page 165: ...in the PRS Each channel includes an edge detector to enable generation of pulse signals from level signals It is also possible to generate output reflex signals by configuring the SWPULSE and SWLEVEL bits SWLEVEL is a programmable level for each channel and holds the value it is programmed to The SWPULSE will give out a one cycle high pulse if it is written to 1 otherwise a 0 is asserted The SWLEV...

Page 166: ... Input Level Yes Pin 2 Input Level Yes Pin 3 Input Level Yes Pin 4 Input Level Yes Pin 5 Input Level Yes Pin 6 Input Level Yes Pin 7 Input Level Yes Pin 8 Input Level Yes Pin 9 Input Level Yes Pin 10 Input Level Yes Pin 11 Input Level Yes Pin 12 Input Level Yes Pin 13 Input Level Yes Pin 14 Input Level Yes GPIO Pin 15 Input Level Yes Overflow Pulse Yes Compare Match 0 Pulse Yes RTC Compare Match 1...

Page 167: ... listen to a PRS channel and perform an action based on the signal received on that channel Most consumers expect pulse input while some can handle level inputs as well Table 13 2 Reflex Consumers Module Reflex Input Input Format Async Support Single Mode Trigger Pulse ADC Scan Mode Trigger Pulse Channel 0 Trigger Pulse DAC Channel 1 Trigger Pulse CC0 Input Pulse Level CC1 Input Pulse Level CC2 In...

Page 168: ...PERCLK cycle high pulse using PRS channel 5 Set SOURCESEL in PRS_CH5_CTRL to 0b011100 to select TIMER0 as input to PRS channel 5 Set SIGSEL in PRS_CH5_CTRL to 0b001 to select the overflow signal from TIMER0 Configure ADC0 with the desired conversion set up Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal Set SINGLEPRSSEL in ADC0_SINGLECT...

Page 169: ...0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name CH11PULSE CH10PULSE CH9PULSE CH8PULSE CH7PULSE CH6PULSE CH5PULSE CH4PULSE CH3PULSE CH2PULSE CH1PULSE CH0PULSE Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 CH11PULSE 0 W1 Channel 11 Pulse Generation See bit 0 10...

Page 170: ...LEVEL CH2LEVEL CH1LEVEL CH0LEVEL Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 CH11LEVEL 0 RW Channel 11 Software Level See bit 0 10 CH10LEVEL 0 RW Channel 10 Software Level See bit 0 9 CH9LEVEL 0 RW Channel 9 Software Level See bit 0 8 CH8LEVEL 0 RW Channel 8 Software Level See bit 0 7 CH7...

Page 171: ...et GPIO output from PRS channel 3 is enabled 2 CH2PEN 0 RW CH2 Pin Enable When set GPIO output from PRS channel 2 is enabled 1 CH1PEN 0 RW CH1 Pin Enable When set GPIO output from PRS channel 1 is enabled 0 CH0PEN 0 RW CH0 Pin Enable When set GPIO output from PRS channel 0 is enabled 13 5 4 PRS_CHx_CTRL Channel Control Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 172: ...ous Receiver Transmitter 2 0b011100 TIMER0 Timer 0 0b011101 TIMER1 Timer 1 0b011110 TIMER2 Timer 2 0b011111 TIMER3 Timer 3 0b100100 USB Universal Serial Bus Interface 0b101000 RTC Real Time Counter 0b101001 UART0 Universal Asynchronous Receiver Transmitter 0 0b101010 UART1 Universal Asynchronous Receiver Transmitter 1 0b110000 GPIOL General purpose Input Output 0b110001 GPIOH General purpose Input...

Page 173: ... TIMER1OF 0b010 TIMER1CC0 Timer 1 Compare Capture 0 TIMER1CC0 0b011 TIMER1CC1 Timer 1 Compare Capture 1 TIMER1CC1 0b100 TIMER1CC2 Timer 1 Compare Capture 2 TIMER1CC2 SOURCESEL 0b011110 TIMER2 0b000 TIMER2UF Timer 2 Underflow TIMER2UF 0b001 TIMER2OF Timer 2 Overflow TIMER2OF 0b010 TIMER2CC0 Timer 2 Compare Capture 0 TIMER2CC0 0b011 TIMER2CC1 Timer 2 Compare Capture 1 TIMER2CC1 0b100 TIMER2CC2 Timer...

Page 174: ...SESCANRES0 0b001 LESENSESCANRES1 LESENSE SCANRES register bit 1 LESENSESCANRES1 0b010 LESENSESCANRES2 LESENSE SCANRES register bit 2 LESENSESCANRES2 0b011 LESENSESCANRES3 LESENSE SCANRES register bit 3 LESENSESCANRES3 0b100 LESENSESCANRES4 LESENSE SCANRES register bit 4 LESENSESCANRES4 0b101 LESENSESCANRES5 LESENSE SCANRES register bit 5 LESENSESCANRES5 0b110 LESENSESCANRES6 LESENSE SCANRES regist...

Page 175: ... interface is memory mapped into the address bus of the Cortex M3 This enables seamless access from software without manually manipulating the IO settings each time a read or write is performed The data and address lines can be multiplexed in order to reduce the number of pins required to interface the external devices The bus timing is adjustable to meet specifications of the external devices The...

Page 176: ...external latch but they use a significantly lower number of pins The use of the 16 EBI_AD pin connections depends on the addressing mode They are used for both address and data in the multiplexed modes Also for the non multiplexed 8 bit address mode both the address and data fit into these 16 EBI_AD pins If more address bits or data bits are needed external latches can be used to support up to 24 ...

Page 177: ... 0 EBI_WEn EBI_NANDWEn EBI_NANDREn Memory Interface EBI TFT Interface 14 3 1 Non multiplexed 8 bit Data 8 bit Address Mode In this mode 8 bit address and 8 bit data is supported The address is put on the higher 8 bits of the EBI_AD lines while the data uses the lower 8 bits This mode is set by programming the MODE field in the EBI_CTRL register to D8A8 The address space can be extended to 256 MB b...

Page 178: ...of an external latch is required The 16 bit address and 16 bit data bits are multiplexed on the EBI_AD lines An illustration of such a setup is shown in Figure 14 4 p 179 This mode is set by programming the MODE field in the EBI_CTRL register to D16A16ALE Note In this mode the 16 bit address is organized in 2 byte chunks at memory addresses aligned to 2 byte offsets Consequently the LSB of the 16 ...

Page 179: ...5 0 EBI_ALE ADDRSETUP 1 2 3 Z DATA 15 0 EBI_CSn EBI_REn Z RDSETUP 0 1 2 RDSTRB 1 2 3 RDHOLD 0 1 2 Figure 14 6 EBI Multiplexed 16 bit Data 16 bit Address Write Operation ADDR 16 1 EBI_AD 15 0 EBI_ALE ADDRSETUP 1 2 3 DATA 15 0 EBI_CSn EBI_WEn Z WRSETUP 0 1 2 WRSTRB 1 2 3 WRHOLD 0 1 2 ADDRHOLD 0 1 2 14 3 3 Multiplexed 8 bit Data 24 bit Address Mode This mode allows 24 bit address with 8 bit data mult...

Page 180: ...s The addresses are driven on the EBI_A lines The address space can be up to 256 MB as described in Section 14 3 6 p 183 This mode is set by programming the MODE field in the EBI_CTRL register to D16 Read and write signals are shown in Figure 14 9 p 181 and Figure 14 10 p 181 respectively for the case in which N address lines on EBI_A have been enabled Note In this mode the 16 bit address is organ...

Page 181: ...intrapage addresses to be read faster Page mode operation is enabled by setting the PAGEMODE bitfield in the EBI_RDTIMING or EBI_RDTIMINGn register to 1 If enabled the RDPA bitfield in the EBI_PAGECTRL register defines the duration of an intrapage access and the PAGELEN bitfield in the EBI_PAGECTRL register defines the number of members in a page Page mode reads can for example be triggered by con...

Page 182: ... hold state RDHOLD is only performed at the end of a page mode read sequence or when bus turn around occurs Note that bus turn around can occur even if only read transactions are performed as the D16A16ALE addressing mode will drive the EBI_AD lines when programming the external address latch In this case one bus turn around RDHOLDX cycle is automatically inserted in between the read and the write...

Page 183: ...cenario as much as possible read transactions can often be made back to back This is achieved by enabling prefetching by setting PREFETCH to 1 in the EBI_RDTIMING or EBI_RDTIMINGn register and by disallowing idle state insertion in between transfers by setting the NOIDLE or NOIDLEn bit to 1 in EBI_CTRL register Figure 14 15 p 183 shows an example in which only ADDR1 benefits from intrapage timing ...

Page 184: ...Latch is controlled by the ALE Address Latch Enable signal and stores the address Then the data is read or written according to operation The higher address bits are output on the EBI_A lines throughout the transfer Figure 14 17 EBI 16 bit Data Multiplexed Read Operation using Extended Addressing ADDR 16 1 EBI_AD 15 0 EBI_ALE ADDRSETUP 1 2 3 Z DATA 15 0 EBI_CSn EBI_REn Z RDSETUP 0 1 2 RDSTRB 1 2 3...

Page 185: ...er is set to 0 the PREFETCH bitfield from EBI_RDTIMING applies to all 4 memory banks When ITS is set to 1 the prefetch unit can be individually enabled per bank In this case register EBI_RDTIMING only applies to bank 0 Prefetch enabling for bank n is then defined in the EBI_RDTIMINGn register The EBI has a 1 entry 32 bit wide write buffer The write buffer can be used to limit stalling by partially...

Page 186: ...AD lines can be driven by either the EFM32GG or by the external device Depending on the characteristics of an external device the RDHOLD should be programmed to ensure adequate bus turn around time Default the EBI inserts an initial IDLE cycle during which the EBI does not drive the EBI_AD lines after each external transaction Furthermore the EBI deasserts the EBI_CSn EBI_REn and EBI_WEn lines dur...

Page 187: ...s can remain asserted for back to back transfers if no further separation is guaranteed via for example RDSETUP RDHOLD WRSETUP or WRHOLD bitfields 14 3 10 Timing The duration of the states in the transaction is defined by the corresponding uppercase name above the state e g the address setup state in Figure 14 8 p 180 is active for a number of internal clock cycles defined by ADDRSET bitfield in t...

Page 188: ...into multiple external transactions then the external transactions have incrementing addresses and start with the lowest data byte s from the AHB transaction The translation and possibly bus fault generation is explained below and in Table 14 3 p 188 If the AHB transaction width is larger than the external device width then multiple consecutive external transactions are performed starting with the...

Page 189: ... be used for code execution When running code via EBI regions starting at this address the Cortex M3 uses the System bus interface to fetch instructions This results in reduced performance as the Cortex M3 accesses stack other data in SRAM and peripherals using the System bus interface Code accesses via the System bus interface will not be cached Furthermore it should be noted that the address are...

Page 190: ...x20000000 0x7fffffff 0x12000000 EBI Region 1 32 MB EBI Region 2 32 MB 0x13ffffff 0x14000000 0x15ffffff 0x16000000 0x17ffffff 0x18000000 0x1fffffff EBI Region 3 128 MB EBI Region 0 64 MB 0x80000000 EBI Region 2 64 MB EBI Region 1 64 MB 0x83ffffff 0x84000000 0x87ffffff 0x88000000 0x8bffffff 0x8c000000 0x8fffffff EBI Region 3 64 MB EBI Regions 0x80000000 0xbfffffff 0xc0000000 0xffffffff 0x12000000 0x...

Page 191: ... cycles for slow devices The interpretation of the polarity of this signal can be configured with the ARDYPOL bit in EBI_POLARITY E g if the ARDYPOL is set to ACTIVELOW then the REn WEn cycle is extended while the ARDY line is kept low The ARDY functionality is enabled by setting the ARDYEN bit in the EBI_CTRL register It is also possible to enable a timeout check which generates a bus error if th...

Page 192: ... which memory bank has a NAND Flash devices attached to it NAND Flash data width read timing and write timing are programmed via the standard EBI registers as described in Section 14 3 14 2 p 193 ECC support is described in Section 14 3 15 p 197 Both standard and Chip Enable Don t Care CEDC NAND Flash devices are supported and they can be attached as shown in Figure 14 25 p 192 and Figure 14 26 p ...

Page 193: ...and Address and Data registers NAND Flash does not use dedicated address lines Because of this indirect I O interface the NAND Flash memory size is not restricted by the memory map of the EFM32GG The NAND Command Address and Data registers can be accessed via memory mapped IO in which two address lines are chosen for connection with the ALE and CLE signals The memory mapping and the two used addre...

Page 194: ...idth does not match the external NAND device transaction width then automatic transaction translation is performed as described in Section 14 3 11 p 188 Note that a bus fault is generated in case of an 8 bit write to a 16 bit NAND device as neither byte lanes nor read modify write is supported for NAND Flash NAND Flash write timing is defined in the EBI_WRTIMING n register Figure 14 27 p 194 Figur...

Page 195: ...latching address latching and data input timing are shown in Table 14 5 p 195 Table 14 5 EBI NAND Flash Write Timing NAND Flash Write Timing Parameter EBI Write Timing Parameter Requirements tADL t WRHOLD t WRSETUP t WRSTRB tALS t WRSETUP t WRSTRB tCS t WRSETUP t WRSTRB tCLS t WRSETUP t WRSTRB tDS t WRSETUP t WRSTRB tALH t WRHOLD tCH t WRHOLD tCLH t WRHOLD tDH t WRHOLD tWC t WRHOLD t WRSETUP t WRS...

Page 196: ... t RDHOLD t RDSETUP t RDSTRB tRR t RDSETUP assuming software wait for R B high tAR t RDSETUP tCLR t RDSETUP tIR t RDSETUP The NAND Flash timing parameters tWHR and tRHW define separation of read and write pulses and therefore they can be satisfied by a combination of EBI_RDTIMING n and EBI_WRTIMING n settings as shown in Table 14 7 p 196 Table 14 7 EBI NAND Flash Read Write Timing Requirements NAN...

Page 197: ...software can accept correct or discard the read data according the comparison result No automatic correction is performed A typical 528 byte page program sequence for an 8 bit wide NAND Flash is as follows Configuration Configure the EBI for NAND Flash support via the EBI_NANDCTRL EBI_CTRL EBI_RDTIMING and EBI_WRTIMING registers Command and address phase Program the NAND Command register to comman...

Page 198: ...it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 0 Byte 1 Byte 2 Byte 3 Byte N 4 Byte N 3 Byte N 2 Byte N 1 P8 P8 P8 P8 P32 P16 P16 P8 P8 P8 P8 P32 P16 P16 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P4 P4 Table 14 8 EBI ECC Bit Column Parity Parity bit Generation for 8 bit data P1 Bit 6 xor Bit 4 xor Bit 2 xor Bit 0 xor P1 P1 Bit 7 xor Bit 5 xor Bit 3 xor Bit 1 xor P1 P2 Bit 5 xor Bit 4 xor Bit 1 xor Bit 0 xor P2...

Page 199: ...ware can compare XOR the parity data generated in EBI_ECCPARITY with the parity information stored in the spare area for the used data set The syndrome resulting from XOR ing the valid EBI_ECCPARITY bits with the ECC code read from the spare area can be used for error detection and correction as shown in Table 14 11 p 199 Table 14 11 EBI Error Detection Result Error Detection Result Syndrome Inter...

Page 200: ...g to Equation 14 1 p 200 and Equation 14 2 p 200 respectively EBI TFT Total Width Number of EBI_DCLK pulses per line HBPORCH HSZ 1 HFPORCH 14 1 EBI TFT Total Height Number of lines per frame VBPORCH VSZ 1 VFPORCH 14 2 The horizontal and vertical synchronization pulses begin at the starts of the horizontal and vertical back porch intervals respectively For the HSYNC pulse a delayed start position c...

Page 201: ...ow compared to the external device access time interleaving can also be allowed during the active interval of the TFT by setting the INTERLEAVE bitfield to ONEPERDCLK or UNLIMITED In both cases interleaving during the porch intervals is unlimited as it is when the PORCH setting is used If INTERLEAVE is set to ONEPERDCLK then at most 1 EBI access is inserted per EBI_DCLK period in the active displa...

Page 202: ... EBI_AD lines Whether the EBI_TFTDD buffer is full or empty is also signaled by the DDEMPTY interrupt flag in the EBI_IF register and by the TFTDDEMPTY status bit in the EBI_STATUS register Given the relatively low performance of using software polling and interrupts compared to using DMA these non DMA mechanisms are only advised for very low pixel rates If pixel data is not provided in time the E...

Page 203: ...AMEBASE register The Direct Drive address is automatically incremented for each visible pixel and it does therefore not depend on the programmed porch sizes The address increment depends on the WIDTH bitfield in the EBI_TFTCTRL register The increment per visible pixel is 1 if the WIDTH bitfield in the EBI_TFTCTRL register is programmed to BYTE and it is 2 if WIDTH is programmed to HALFWORD Additio...

Page 204: ...ddress Visible Display P 0 0 Local frame base copy FBC gets assigned with EBI_TFTFRAMEBASE on every EBI_VSYNC stobe P 1 0 P 2 0 P 3 0 P HSZ 0 P 0 1 P 1 1 P 2 1 P 3 1 P HSZ 1 P 0 2 P 1 2 P 2 2 P 3 2 P HSZ 2 P 0 VSZ P 1 VSZ P 2 VSZ P 3 VSZ P HSZ VSZ HFPORCH HBPORCH VFPORCH VBPORCH The address increment per pixel PSZ is 1 if the WIDTH bitfield in EBI_TFTCTRL is programmed to BYTE and 2 if the WIDTH b...

Page 205: ...gister Alpha blending works on two data items a foreground Color0 R0 G0 B0 and a background Color1 R1 G1 B1 These data items are encoded in either 565 RGB or 555 RGB format as defined in the RGBMODE bitfield of the EBI_TFTCTRL register In case that the 555 RGB format is used only the 15 least significant bits of Color0 and Color1 are used for the alpha blending operation itself The most significan...

Page 206: ...ed by writing RGB data D to EBI_TFTPIXEL0 with COLOR1SRC set to PIXEL1 and MASKBLEND set to IMASK IALPHA or IMASKEALPHA This alpha blending interface is intended for use by both the Cortex M3 and the DMA controller For DMA operation three DMA requests are generated One DMA request indicating that EBI_TFTPIXEL0 requires new data one DMA request indicating that EBI_TFTPIXEL1 requires new data and on...

Page 207: ...set by HW and writing a value n to this bitfield results in an extended duration of 1 n cycles After performing the required actions to produce the required TFT pixel data on the EBI_AD lines the TFT transaction will pass through its TFTSETUP and TFTHOLD states as indicated in Figure 14 39 p 208 In this figure the duration of the states in the TFT transaction is defined by the corresponding upperc...

Page 208: ...ct Drive to generate transactions satisfying the requirements of both the memory device and the TFT display The timing definition for the external memory device should be programmed according to its requirements independent of the TFT timing Figure 14 41 p 208 shows an example of the Direct Drive engine accessing an external memory using the multiplexed 16 bit data 16 bit address D16A16ALE mode Th...

Page 209: ... VSZ 1 2 3 VERTICAL BACK PORCH L1 LVSZ VERTICAL FRONT PORCH VBPORCH 0 1 2 VFPORCH 0 1 2 EBI_VSYNC VSYNC 1 2 3 The active edge of the EBI_DCLK and the other TFT related signals are by default driven off the positive edge of the internal clock The edges of the EBI_DCLK can also be driven off the negative edge of the internal clock by setting the SHIFTDCLK bitfield in the EBI_TFTCTRL register to 1 Th...

Page 210: ...egister The EBI_AD EBI_WEn and EBI_REn pins are all enabled by the EBIPEN bit the EBI_CSn pins are enabled by the corresponding CSxPEN bit the EBI_ALE pin is enabled by the ALEPEN bit the EBI_BL pins are enabled by the BLPEN bit the EBI_NANDWEn and EBI_NANDREn pins are enabled by the NANDPEN bit the TFT pins EBI_DCLK EBI_VSYNC and EBI_HSYNC are all enabled by the TFTPEN bit the EBI_DATAEN pin is e...

Page 211: ...request is initially set and it is cleared when EBI_TFTDD is written It is set again once the pixel data has been transferred to the display One DMA request is generated for each visible pixel The masking and alpha blending hardware uses three DMA requests related to the status of thee internal masking and alpha blending registers EBI_TFTPIXEL0 EBI_TFTPIXEL1 and EBI_TFTPIXEL The DMA request for EB...

Page 212: ...EBI_RDTIMING3 RW Read Timing Register 3 0x040 EBI_WRTIMING3 RW Write Timing Register 3 0x044 EBI_POLARITY3 RW Polarity Register 3 0x048 EBI_PAGECTRL RW Page Control Register 0x04C EBI_NANDCTRL RW NAND Control Register 0x050 EBI_CMD W1 Command Register 0x054 EBI_STATUS R Status Register 0x058 EBI_ECCPARITY R ECC Parity register 0x05C EBI_TFTCTRL RW TFT Control Register 0x060 EBI_TFTSTATUS R TFT Sta...

Page 213: ...isables the Byte Lane functionality for bank 2 Ignored when ITS 0 25 BL1 0 RW Byte Lane Enable for bank 1 Enables or disables the Byte Lane functionality for bank 1 Ignored when ITS 0 24 BL 0 RW Byte Lane Enable for bank 0 Enables or disables the Byte Lane functionality for bank 0 Applies to all banks when ITS 0 Applies to only bank 0 when ITS 1 23 ARDYTO3DIS 0 RW ARDY Timeout Disable for bank 3 E...

Page 214: ...ess bits can be enabled on EBI_A in the EBI_ROUTE register 3 D16 EBI_AD drives 16 bit data ALE not used Extended address bits can be enabled on EBI_A in the EBI_ROUTE register 5 4 MODE2 0x0 RW Mode 2 This field sets the access mode the EBI will use for interfacing devices on bank 2 Ignored when ITS 0 Value Mode Description 0 D8A8 EBI_AD drives 8 bit data 8 bit address ALE not used Extended address...

Page 215: ...ved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable Enables or disables half cycle duration of the ALE strobe in the last ADDRSETUP cycle 27 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 8 ADDRHOLD 0x3 RW Address Hold Ti...

Page 216: ... of cycles the address setup before REn is asserted 14 5 4 EBI_WRTIMING Write Timing Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x3 0x3F 0x3 Access RW RW RW RW RW Name WBUFDIS HALFWE WRHOLD WRSTRB WRSETUP Bit Name Reset Access Description 31 30 Reserved To ensure compatibility with future devices always write b...

Page 217: ...YPOL 0 RW ARDY Polarity Sets the polarity of the EBI_ARDY line Value Mode Description 0 ACTIVELOW ARDY is active low 1 ACTIVEHIGH ARDY is active high 3 ALEPOL 0 RW Address Latch Polarity Sets the polarity of the EBI_ALE line Value Mode Description 0 ACTIVELOW ALE is active low 1 ACTIVEHIGH ALE is active high 2 WEPOL 0 RW Write Enable Polarity Sets the polarity of the EBI_WEn and EBI_NANDWEn lines ...

Page 218: ...EBI_CSTFT pin is enabled 25 DATAENPEN 0 RW EBI_TFT Pin Enable When set the EBI_DATAEN pin is enabled 24 TFTPEN 0 RW EBI_TFT Pin Enable When set the EBI_DCLK EBI_VSYNC and EBI_HSYNC pins are enabled 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 18 APEN 0x00 RW EBI_A Pin Enable Selects which non multiplexed address lines are ena...

Page 219: ... enabled 11 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 BLPEN 0 RW EBI_BL 1 0 Pin Enable When set the EBI_BL 1 0 pins are enabled 6 ARDYPEN 0 RW EBI_ARDY Pin Enable When set the EBI_ARDY pin is enabled 5 ALEPEN 0 RW EBI_ALE Pin Enable When set the EBI_ALE pin is enabled 4 CS3PEN 0 RW EBI_CS3 Pin Enable When set the EBI_CS3 pin...

Page 220: ... Access Description 31 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 PAGEMODE 0 RW Page Mode Access Enable Enables or disables page mode reads 29 PREFETCH 0 RW Prefetch Enable Enables or disables prefetching of data from sequential address 28 HALFRE 0 RW Half Cycle REn Strobe Duration Enable Enables or disables half cycle duratio...

Page 221: ...cycles CSn is held active after the WEn is deasserted 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 8 WRSTRB 0x3F RW Write Strobe Time Sets the number of cycles the WEn is held active If set to 0 1 cycle is inserted by HW 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sec...

Page 222: ...e Mode Description 0 ACTIVELOW CSn is active low 1 ACTIVEHIGH CSn is active high 14 5 11 EBI_ADDRTIMING2 Address Timing Register 2 Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x3 0x3 Access RW RW RW Name HALFALE ADDRHOLD ADDRSETUP Bit Name Reset Access Description 31 29 Reserved To ensure compatibility with future devices ...

Page 223: ...3 RW Read Hold Time Sets the number of cycles CSn is held active after the REn is deasserted This interval is used for bus turnaround 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 8 RDSTRB 0x3F RW Read Strobe Time Sets the number of cycles the REn is held active After the specified number of cycles data is read If set to 0 ...

Page 224: ...ITY2 Polarity Register 2 Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access RW RW RW RW RW RW Name BLPOL ARDYPOL ALEPOL WEPOL REPOL CSPOL Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 BLPOL 0 RW BL Polarity ...

Page 225: ...robe Duration Enable Enables or disables half cycle duration of the ALE strobe in the last address setup cycle 27 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 8 ADDRHOLD 0x3 RW Address Hold Time Sets the number of cycles the address is held after ALE is asserted 7 2 Reserved To ensure compatibility with future devices always w...

Page 226: ...ime Sets the number of cycles the address setup before REn is asserted 14 5 17 EBI_WRTIMING3 Write Timing Register 3 Offset Bit Position 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x3 0x3F 0x3 Access RW RW RW RW RW Name WBUFDIS HALFWE WRHOLD WRSTRB WRSETUP Bit Name Reset Access Description 31 30 Reserved To ensure compatibility with future...

Page 227: ...RDYPOL 0 RW ARDY Polarity Sets the polarity of the EBI_ARDY line Value Mode Description 0 ACTIVELOW ARDY is active low 1 ACTIVEHIGH ARDY is active high 3 ALEPOL 0 RW Address Latch Polarity Sets the polarity of the EBI_ALE line Value Mode Description 0 ACTIVELOW ALE is active low 1 ACTIVEHIGH ALE is active high 2 WEPOL 0 RW Write Enable Polarity Sets the polarity of the EBI_WEn and EBI_NANDWEn line...

Page 228: ...ved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 INCHIT 0 RW Intrapage hit only on incremental addresses Sets whether page hits occur on any member in a page or only on incremental addresses 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 0 PAGELEN 0x0 RW Page Length Se...

Page 229: ...on in Section 2 1 p 3 2 ECCCLEAR 0 W1 Error Correction Code Clear Write to 1 to clear ECCPARITY 1 ECCSTOP 0 W1 Error Correction Code Generation Stop Write to 1 to stop ECC generation 0 ECCSTART 0 W1 Error Correction Code Generation Start Write to 1 to start ECC generation 14 5 22 EBI_STATUS Status Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ...

Page 230: ...Busy with AHB Transaction Indicates that EBI is busy with an AHB Transaction 14 5 23 EBI_ECCPARITY ECC Parity register Offset Bit Position 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name ECCPARITY Bit Name Reset Access Description 31 0 ECCPARITY 0x00000000 R ECC Parity Data ECC Parity Data 14 5 24 EBI_TFTCTRL TFT Control Re...

Page 231: ...om external memory 1 PIXEL1 Masking Alpha Blending color 1 is read from EBI_TFTPIXEL1 11 10 INTERLEAVE 0x0 RW Interleave Mode This field sets the TFT Direct Drive Interleave mode Value Mode Description 0 UNLIMITED Allow unlimited interleaved EBI accesses per EBI_DCLK period This can cause jitter on the EBI_DCLK 1 ONEPERDCLK Allow 1 interleaved EBI access per EBI_DCLK period 2 PORCH Only allow EBI ...

Page 232: ...27 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 26 16 VCNT 0x000 R Vertical Count Contains the current line position within a frame initial line in vertical back porch has VCNT 0 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 0 HCNT 0x000 R Horizontal Count C...

Page 233: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 0x000 Access RW RW Name VSZ HSZ Bit Name Reset Access Description 31 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 25 16 VSZ 0x000 RW Vertical Size excluding porches Sets the vertical size in lines Set to required size minus 1 15 10 Reserved To e...

Page 234: ...ection 2 1 p 3 6 0 HSYNC 0x00 RW Horizontal Synchronization Pulse Width Sets the horizontal synchronization pulse width Set to required width minus 1 Width is reduced in case HSYNCSTART 0 14 5 30 EBI_TFTVPORCH TFT Vertical Porch Register Offset Bit Position 0x074 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 Access RW RW RW Name VBPORCH ...

Page 235: ...ore information in Section 2 1 p 3 22 12 TFTSTART 0x000 RW TFT Direct Drive Transaction Start Sets the starting position of the External Direct Drive Transaction relative to the DCLK inactive edge 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 0 DCLKPERIOD 0x000 RW TFT Direct Drive Transaction EBI_DCLK Period Sets the Direct Dr...

Page 236: ...ity Sets the polarity of the EBI_CSTFT line Value Mode Description 0 ACTIVELOW CSTFT is active low 1 ACTIVEHIGH CSTFT is active high 14 5 33 EBI_TFTDD TFT Direct Drive Data Register Offset Bit Position 0x080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name DATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility ...

Page 237: ... 0 Reset 0x0000 Access RW Name DATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DATA 0x0000 RW RGB data Sets the RGB data value according to the format defined in RGBMODE 14 5 36 EBI_TFTPIXEL1 TFT Pixel 1 Register Offset Bit Position 0x08C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 238: ...peration according to the format defined in RGBMODE 14 5 38 EBI_TFTMASK TFT Masking Register Offset Bit Position 0x094 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name TFTMASK Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 TF...

Page 239: ...g Set Register Offset Bit Position 0x09C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 Name DDJIT DDEMPTY VFPORCH VBPORCH HSYNC VSYNC Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 DDJIT 0 W1 Direct Drive Jitter...

Page 240: ... Porch interrupt flag 1 HSYNC 0 W1 Horizontal Sync Interrupt Flag Clear Write to 1 to clear Horizontal Sync interrupt flag 0 VSYNC 0 W1 Vertical Sync Interrupt Flag Clear Write to 1 to clear Vertical Sync interrupt flag 14 5 42 EBI_IEN Interrupt Enable Register Offset Bit Position 0x0A4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access R...

Page 241: ...016 04 28 Giant Gecko Family d0053_Rev1 20 241 www silabs com Bit Name Reset Access Description Set to enable interrupt on Horizontal Sync interrupt flag 0 VSYNC 0 RW Vertical Sync Interrupt Enable Set to enable interrupt on Vertical Sync interrupt flag ...

Page 242: ... the number of external components to a minimum Third party USB software stacks are also available reducing the development time substantially By utilizing the very low energy consumption in EM2 the USB device will be able to wake up and perform tasks several times a second without violating the 2 5 mA maximum average current during suspend 15 1 Introduction The USB is a full speed low speed USB 2...

Page 243: ...ow quiescent current 100 uA Dedicated input pin allows regulator to be used in OTG and host configurations Output pin can be used to power the EFM32 itself as well as external components Regulator voltage output sense feature for detecting USB plug unplug events also available in EM2 3 15 3 USB System Description A block diagram of the USB is shown in Figure 15 1 p 243 Figure 15 1 USB Block Diagra...

Page 244: ... to run a 48 MHz crystal 2500 ppm or better The core part of the USB will always run from HFCORECLKUSBC which is 48 MHz The current consumption for the rest of the device can be reduced by dividing down HFCORECLK using the CMU_HFCORECLKDIV register Bandwidth requirements for the specific USB application must be taken into account when dividing down HFCORECLK 15 3 2 USB Initialization Follow these ...

Page 245: ...powered Device A self powered device configuration is shown in Figure 15 3 p 245 When the USB is configured as a self powered device the voltage regulator is typically used to power the PHY only although it may also be used to power other 3 3 V components When the USB is connected to a host the voltage regulator is activated Software can detect this event by enabling the VREGO Sense High VREGOSH i...

Page 246: ...ent consumption before switching to the USB power source If VBUS voltage is removed the circuit switches automatically back to the battery power supply If necessary software must react quickly to this event and reduce the current consumption for example by reducing the clock frequency to avoid excessive voltage drop This configuration is shown in Figure 15 4 p 246 In this configuration the VREGO s...

Page 247: ...uses the PHY to be powered directly from the external 3 0 3 6 V supply The voltage regulator should be disabled when operating in this mode For over current detection a regular GPIO input pin with interrupt is used The application should turn off or limit VBUS power when over current is detected In OTG mode the maximum VBUS decoupling capacitance is 6 5 uF In this configuration the VREGO sense cir...

Page 248: ...DIS in USB_CTRL after power up Then the regulator is effectively bypassed When VREGO Sense is enabled the PHY is automatically disabled internally when the VREGO Sense output is low This will happen if VBUS power disappears The application can detect this by keeping the VREGO Sense Low Interrupt enabled Note that PHYPEN in USB_ROUTE will not be set to 0 in this case Also the PHY must always be dis...

Page 249: ...S outputs go to 0 in EM2 3 15 3 7 USB in EM2 During suspend and session off EM2 should be used to save power and meet the average current requirements dictated by the USB standard Before entering EM2 HFCORECLKUSBC must be switched from 48 MHz to 32 kHz LFXO or LFRCO This is done using the CMU_CMD and CMU_STATUS registers Upon EM2 wake up HFCORECLKUSBC must be switched back to 48 MHz before accessi...

Page 250: ...odic TxFIFO Empty Level can be enabled only when the core is operating in Slave mode as a host Periodic TxFIFO Empty Level can be enabled only when the core is operating in Slave mode 2 Program the following field in the Global Interrupt Mask USB_GINTMSK register USB_GINTMSK RXFLVLMSK 0 3 Program the following fields in USB_GUSBCFG register HNP Capable bit SRP Capable bit External HS PHY or Intern...

Page 251: ... flow 1 When the USB Cable is plugged to the Host port the core triggers USB_GINTSTS CONIDSTSCHNG interrupt 2 When the Host application detects USB_GINTSTS CONIDSTSCHNG interrupt the application can perform one of the following actions Turn on VBUS by setting USB_HPRT PRTPWR 1 or Wait for SRP Signaling from Device to turn on VBUS 3 The PHY indicates VBUS power on by detecting a VBUS valid voltage ...

Page 252: ...SESSREQINT interrupt it programs the required bits in the USB_DCFG register 3 When the Host drives Reset the Device triggers USB_GINTSTS USBRST bit 12 on detecting the Reset The host then follows the USB 2 0 Enumeration sequence When VBUS is off When the Device is Connected If VBUS is off when the device is connected to the USB cable the device initiates SRP in OTG Revision 1 3 mode The device con...

Page 253: ...ode and the PHY clock stops 3 The application clears the Stop PHY Clock bit in the Power and Clock Gating Control register and waits for the PHY clock to come back The core takes the PHY back to normal mode and the PHY clock comes back 4 The application sets the Soft disconnect bit SFTDISCON in Device Control Register USB_DCTL 5 The application sets the Soft Reset bit CSFTRST in the Reset Register...

Page 254: ... transfer The application is interrupted on completion of every packet The application performs transaction level operations for a channel endpoint for a transmission host OUT device IN or reception host IN device OUT as shown in Figure 15 8 p 255 and Figure 15 9 p 255 Host Mode For an OUT transaction the application enables the channel and writes the data packet into the corresponding Periodic or...

Page 255: ...t to the Transmit FIFO Get channel endpoint interrupt status Done Start Rewrite packet to the Transmit FIFO Yes Yes No Yes No Transfer complete Retry required Get interrupt No Figure 15 9 Receive Transaction Level Operation in Slave Mode Done Start Yes Retry required No No Transfer complete Yes Read Receive Status Queue No RXFLVL or Ch EP interrupt Yes Set up the Channel endpoint Read the packet f...

Page 256: ...imum packet size packet of the channel in the top of the Request queue 15 4 2 3 2 2 Device mode For an IN transaction the application sets up a transfer and enables the endpoint The application can write multiple packets back to back for the same endpoint into the transmit FIFO based on available space It can also pipeline IN transactions for multiple channels by writing into the USB_DIEPx_CTL reg...

Page 257: ...initializes the channel by following these steps 15 4 3 2 Halting a Channel The application can disable any channel by programming the USB_HCx_CHAR register with the USB_HCx_CHAR CHDIS and USB_HCx_CHAR CHENA bits set to 1 This enables the host to flush the posted requests if any and generates a Channel Halted interrupt The application must wait for the USB_HCx_INT CHHLTD interrupt before reallocat...

Page 258: ...channel with CHENA 1 and the device s endpoint characteristics such as type speed and direction The application must treat a zero length data packet as a separate transfer and cannot combine it with a non zero length transfer 15 4 3 4 Handling Babble Conditions The core handles two cases of babble packet babble and port babble Packet babble occurs if the device sends more data than the maximum pac...

Page 259: ... IN Transactions in DMA Mode p 277 Interrupt OUT Transactions in DMA Mode p 275 Isochronous Slave Isochronous IN Transactions in Slave Mode p 281 Isochronous OUT Transactions in Slave Mode p 279 DMA Isochronous IN Transactions in DMA Mode p 283 Isochronous OUT Transactions in DMA Mode p 282 15 4 3 6 1 Writing the Transmit FIFO in Slave Mode Figure 15 10 p 260 shows the flow diagram for writing to ...

Page 260: ...11 Receive FIFO Read Task in Slave Mode Read USB_GRXSTSP PKTSTS 0b0010 Yes Yes Unmask RXFLVL interrupt BCNT 0 No Mask RXFLVL interrupt Yes Unmask RXFLVL interrupt No No Start RXFLVL Interrupt Read the received packet from the Receive FIFO 15 4 3 6 3 Control Transactions in Slave Mode Setup Data and Status stages of a control transfer must be performed as three separate transfers Setup Data or Stat...

Page 261: ...tes the same way but has only one packet The assumptions are The application is attempting to send two maximum packet size packets transfer size 1 024 bytes The Non periodic Transmit FIFO can hold two packets 128 bytes for FS The Non periodic Request Queue depth 4 15 4 3 6 4 1 Normal Bulk and Control OUT SETUP Operations The sequence of operations in Figure 15 12 p 262 channel 1 is as follows 1 In...

Page 262: ...S read_rx_stsre ad_rx_fifo read_rx_sts Disable ch_2 1 2 3 4 5 6 7 De allocate ch_2 ch_2 2 3 5 7 8 9 12 13 read_rx_sts 10 11 DATA1 MPS DATA1 RXFLVL interrupt XFERCOMPL interrupt RXFLVL interrupt RXFLVL interrupt XFERCOMPL interrupt RXFLVL interrupt CHHLTD interrupt Non Periodic Request Queue Assume that this queue can hold 4 entries 15 4 3 6 4 2 Handling Interrupts The channel specific interrupt se...

Page 263: ...lable and until the XFERCOMPL interrupt is received 15 4 3 6 5 Bulk and Control IN Transactions in Slave Mode To initialize the core after power on reset the application must follow the sequence in Overview Programming the Core p 250 Before it can communicate with the connected device it must initialize a channel as described in Channel Initialization p 256 See Figure 15 10 p 260 and Figure 15 11 ...

Page 264: ...ng a Channel p 257 and stop writing the USB_HC2_CHAR register for further requests The core writes a channel disable request to the non periodic request queue as soon as the USB_HC2_CHAR register is written 10 The core generates the RXFLVL interrupt as soon as the halt status is written to the receive FIFO 11 Read and ignore the receive packet status 12 The core generates a CHHLTD interrupt as soo...

Page 265: ...nitialize a channel as described in Channel Initialization p 256 This section discusses the following topics Overview p 265 Normal Bulk and Control OUT SETUP Operations p 265 NAK Handling with DMA p 265 Handling Interrupts p 267 15 4 3 6 7 1 Overview The application is attempting to send two maximum packet size packets transfer size 1 024 bytes The Non periodic Transmit FIFO can hold two packets 1...

Page 266: ...plication The NAK interrupt is masked by the application The core does not generate a separate interrupt when NAK is received by the Host functionality Application Programming Flow 1 The application programs a channel to do a bulk transfer for a particular data size in each transaction Packet Data size can be up to 512 KBytes Zero length data must be programmed as a separate transaction 2 Program ...

Page 267: ...init_reg ch_1 init_reg ch_2 ch_2 ch_2 ch_1 ch_1 De allocate ch_1 IN ch_2 ch_2 ch_2 ch_1 ACK OUT DATA1 MPS 3 1 ACK DATA0 IN ACK DATA1 1 MPS 1 MPS 1 2 2 5 4 5 De allocate ch_2 ch_2 8 6 3 4 7 CHHLTD interrupt CHHLTD interrupt Non Periodic Request Queue Assume that this queue can hold 4 entries 15 4 3 6 7 4 Handling Interrupts The channel specific interrupt service routine for bulk and control OUT SET...

Page 268: ...ed the required USB_HAINTMSK and USB_HCx_INTMSK status bits Read USB_HAINT to determine the channel which caused the Interrupt and read the corresponding USB_HCx_INT USB_HCx_INT CHHLTD 1 In Figure 15 14 p 268 that the Interrupt Service Routine is not required to handle NAK responses This is the difference of proposed flow with respect to current flow Similar flow is applicable for Control flow als...

Page 269: ...is enabled the core attempts to fetch and write data packets in multiples of the maximum packet size to the transmit FIFO when space is available in the transmit FIFO and the Request queue The core stops fetching as soon as the last packet is fetched 15 4 3 6 8 Bulk and Control IN Transactions in DMA Mode To initialize the core after power on reset the application must follow the sequence in Overv...

Page 270: ...ue 5 The host flushes the extra requests 6 The final request to disable channel 2 is written to the Request queue At this point channel 2 is internally masked for further arbitration 7 The host generates the CHHLTD interrupt as soon as the disable request comes to the top of the queue 8 In response to the CHHLTD interrupt de allocate the channel for other transfers 15 4 3 6 8 2 Handling Interrupts...

Page 271: ...acket Periodic Request Queue depth 4 15 4 3 6 9 1 Normal Interrupt OUT Operation The sequence of operations in Figure 15 15 p 272 is as follows 1 Initialize and enable channel 1 as explained in Channel Initialization p 256 The application must set the USB_HC1_CHAR ODDFRM bit 2 Write the first packet for channel 1 For a high bandwidth interrupt transfer the application must write the subsequent pac...

Page 272: ...es 1 5 DATA0 IN 1 MPS read_rx_sts read_rx_fifo read_rx_sts 1 2 3 4 6 2 3 6 7 8 9 Odd frame Even frame init_reg ch_1 set_ch_en ch_2 init _reg ch_2 write _tx_fifo ch_1 init_reg ch_1 1 MPS DATA1 5 4 ACK ACK ACK ch_1 ch_2 ch_2 ch_1 XFERCOMPL interrupt XFERCOMPL interrupt XFERCOMPL interrupt RXFLVL interrupt RXFLVL interrupt Interrupt Service Routine for Interrupt OUT Transactions in Slave Mode Interru...

Page 273: ...ite Task in Slave Mode and Receive FIFO Read Task in Slave Mode for read or write data to and from the FIFO in Slave mode A typical interrupt IN operation in Slave mode is shown in Figure 15 15 p 272 See channel 2 ch_2 The assumptions are 1 The application is attempting to receive one packet up to 1 maximum packet size in every frame starting with odd transfer size 1 024 bytes 2 The receive FIFO c...

Page 274: ...t status is read 9 In response to the XFERCOMPL interrupt read the USB_HC2_TSIZ PKTCNT field If USB_HC2_TSIZ PKTCNT 0 disable the channel as explained in Halting a Channel p 257 before re initializing the channel for the next transfer if any If USB_HC2_TSIZ PKTCNT 0 reinitialize the channel for the next transfer This time the application must reset the USB_HC2_CHAR ODDFRM bit 15 4 3 6 10 2 Handlin...

Page 275: ...cal interrupt OUT operation in DMA mode is shown in Figure 15 16 p 276 See channel 1 ch_1 The assumptions are The application is attempting to transmit one packet in every frame up to 1 maximum packet size of 1 024 bytes The Periodic Transmit FIFO can hold one packet 1 KB for FS Periodic Request Queue depth 4 15 4 3 6 11 1 Normal Interrupt OUT Operation 1 Initialize and enable channel 1 as explain...

Page 276: ...ic Request Queue Assume that this queue can hold 4 entries 1 DATA0 IN 1 MPS 1 2 3 5 ch_1 2 4 5 init_reg ch_1 init_reg ch_2 init_reg ch_1 1 MPS DATA1 ch_2 4 3 ACK ACK ACK Odd frame Even frame CHHLTD interrupt CHHLTD interrupt CHHLTD interrupt 15 4 3 6 11 2 Handling Interrupts The following code sample shows the channel specific ISR for an interrupt OUT transaction in DMA mode Interrupt OUT Unmask C...

Page 277: ...FO and the Request queue The core stops fetching as soon as the last packet is fetched the number of packets is determined by the MC field of the USB_HCx_CHAR register 15 4 3 6 12 Interrupt IN Transactions in DMA Mode To initialize the core after power on reset the application must follow the sequence in Overview Programming the Core p 250 Before it can communicate with the connected device it mus...

Page 278: ...e CHHLTD interrupt reinitialize the channel for the next transfer 15 4 3 6 12 2 Handling Interrupts The channel specific interrupt service routine for Interrupt IN transactions in DMA mode is as follows Interrupt Service Routine for Interrupt IN Transactions in DMA Mode Unmask CHHLTD if CHHLTD if XFERCOMPL Reset Error Count Mask ACK if Transfer Done De allocate Channel else Re initialize Channel i...

Page 279: ...rame transfer size 1 024 bytes The Periodic Transmit FIFO can hold one packet 1 KB Periodic Request Queue depth 4 15 4 3 6 13 1 Normal Isochronous OUT Operation The sequence of operations in Figure 15 17 p 280 channel 1 is as follows 1 Initialize and enable channel 1 as explained in Channel Initialization p 256 The application must set the USB_HC1_CHAR ODDFRM bit 2 Write the first packet for chann...

Page 280: ...sts read_rx_fifo read_rx_sts 1 2 3 4 6 2 3 6 7 8 9 init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write _tx_fifo ch_1 init_reg ch_1 1 MPS DATA 0 5 4 ch_2 ch_1 Even frame Odd frame XFERCOMPL interrupt XFERCOMPL interrupt XFERCOMPL interrupt RXFLVL interrupt RXFLVL interrupt Periodic Requests Queue Asume that this queue can hold 4 entries Interrupt Service Routine for Isochronous OUT Transactions in Sla...

Page 281: ...s in the next frame times before switching to another channel 3 The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register write with the CHENA bit set 4 The host attempts to send an IN token in the next odd frame 5 As soon as the IN packet is received and written to the receive FIFO the host generates an RXFLVL interrupt 6 In response to the RXFLVL interrupt read t...

Page 282: ...lication is attempting to transmit one packet every frame up to 1 maximum packet size of 1 024 bytes The Periodic Transmit FIFO can hold one packet 1 KB Periodic Request Queue depth 4 15 4 3 6 15 1 Normal Isochronous OUT Operation 1 Initialize and enable channel 1 as explained in Channel Initialization p 256 2 The host starts fetching the first packet as soon as the channel is enabled and writes t...

Page 283: ... init_reg ch_1 init_reg ch_2 init_reg ch_1 1 MPS DATA0 ch_2 4 3 Odd frame Even frame CHHLTD interrupt CHHLTD interrupt CHHLTD interrupt Interrupt Service Routine for Isochronous OUT Transactions in DMA Mode Isochronous OUT Unmask CHHLTD if CHHLTD if XFERCOMPL or FRMOVRUN De allocate Channel 15 4 3 6 16 Isochronous IN Transactions in DMA Mode To initialize the core after power on reset the applicat...

Page 284: ...IN request to the Request queue as soon as the channel 2 gets the grant from the arbiter round robin with fairness In high bandwidth transfers the host performs consecutive writes up to MC times 3 The host attempts to send an IN token at the beginning of the next odd frame 4 As soon the packet is received and written to the receive FIFO the host generates a CHHLTD interrupt 5 In response to the CH...

Page 285: ...gram the USB_GRXFSIZ Register to be able to receive control OUT data and setup data At a minimum this must be equal to 1 max packet size of control endpoint 0 2 DWORDs for the status of the control OUT data packet 10 DWORDs for setup packets Program the Device IN Endpoint Transmit FIFO size register depending on the FIFO number chosen to be able to transmit control IN data At a minimum this must b...

Page 286: ...int Deactivation p 286 5 Unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the USB_USB_DAINTMSK register 6 Set up the Data FIFO RAM for each FIFO See Data FIFO RAM Allocation p 331 for more detail 7 After all required endpoints are configured the application must program the core to send a status IN packet At this point the device core is configure...

Page 287: ...ed When this bit is cleared it ensures that there is no data left in the TX FIFO 15 4 4 1 8 2 Transfer Stop Programming Flow for OUT Endpoints Sequence of operations 1 Enable all OUT endpoints by setting USB_DOEP0CTL USB_DOEPx_CTL EPENA 1 2 Before disabling any OUT endpoint the application must enable Global OUT NAK mode in the core according to the instructions in Setting the Global OUT NAK p 295...

Page 288: ...in DMA and Slave Mode p 312 Generic Non Isochronous OUT Data Transfers Without Thresholding in DMA and Slave Modes p 297 Interrupt Slave Generic Periodic IN Interrupt and Isochronous Data Transfers Without Thresholding p 317 and Generic Periodic IN Data Transfers Without Thresholding Using the Periodic Transfer Interrupt Feature p 319 Generic Non Isochronous OUT Data Transfers Without Thresholding...

Page 289: ...USB_DOEPx_CTL NAK status and USB_DOEPx_CTL EPENA bit setting The SUPCNT field is decremented every time the control endpoint receives a SETUP packet If the SUPCNT field is not programmed to a proper value before receiving a SETUP packet the core still receives the SETUP packet and decrements the SUPCNT field but the application possibly is not be able to determine the correct number of SETUP packe...

Page 290: ...n DMA mode program the USB_DOEPx_DMAADDR register and USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint Enable bit USB_DOEPx_CTL EPENA Endpoint Enable 1 3 In Slave mode wait for the USB_GINTSTS RXFLVL interrupt and empty the data packets from the receive FIFO as explained in Packet Read from FIFO in Slave Mode p 294 This step can be repeated many times 4 Assertion of th...

Page 291: ...endpoint However the USB 2 0 specification does not limit the number of back to back SETUP packets a host can send to the same endpoint When this condition occurs the core generates an interrupt USB_DOEPx_INT BACK2BACKSETUP In DMA mode the core also rewinds the DMA address for that endpoint USB_DOEPx_DMAADDR and overwrites the first SETUP packet in system memory with the fourth second with the fif...

Page 292: ...eceived Setup command the application must program the required registers in the core This step is optional based on the type of Setup command received 6 For the status IN phase the application must program the core as described in Generic Non Periodic Bulk and Control IN Data Transfers Without Thresholding in DMA and Slave Mode p 312 to perform a data IN transfer 7 Assertion of the USB_DIEPx_INT ...

Page 293: ... Slave and DMA Modes p 289 for details USB_DOEPx_CTL EPENA 1 Depending on the type of Setup command received the application can be required to program registers in the core to execute the received Setup command 3 For the status IN phase the application must program the core described in Generic Non Periodic Bulk and Control IN Data Transfers Without Thresholding in DMA and Slave Mode p 312 to per...

Page 294: ...a rdy proc_ setup_pkt 2 idle until intr rcv_out_data idle until intr rcv_out_data idle until intr rcv_out_data idle until intr 1 3 4 RXFLVLINTR 5 6 7 8 Ctl IN NAK 1 Ctl OUT NAK 1 Control IN NAK 1 Control OUT NAK 1 8 bytes 8 bytes setup data 1 XFERSIZE 0 bytes PKTCNT 1 EPENA 1 15 4 4 2 2 4 Packet Read from FIFO in Slave Mode This section describes how to read packets OUT data and SETUP packets from...

Page 295: ...ng for the PKTSTS is listed in Section 15 6 p 353 6 After the data payload is popped from the receive FIFO the USB_GINTSTS RXFLVL interrupt must be unmasked 7 Steps 1 5 are repeated every time the application detects assertion of the interrupt line due to USB_GINTSTS RXFLVL Reading an empty receive FIFO can result in undefined core behavior Figure 15 21 p 295 provides a flow chart of this procedur...

Page 296: ...FMSK 1 15 4 4 2 2 6 Disabling an OUT Endpoint The application must use this sequence to disable an OUT endpoint that it has enabled Application Programming Sequence 1 Before disabling any OUT endpoint the application must enable Global OUT NAK mode in the core as described in Setting the Global OUT NAK p 295 USB_DCTL SGOUTNAK 1 Wait for the USB_GINTSTS GOUTNAKEFF interrupt 2 Disable the required O...

Page 297: ... packet size of the endpoint is not a multiple of 4 the core inserts byte pads at end of a maximum packet size packet up to the end of the DWORD 3 On any OUT endpoint interrupt the application must read the endpoint s Transfer Size register to calculate the size of the payload in the memory The received payload size can be less than the programmed transfer size Payload size in memory application p...

Page 298: ...o the receive FIFO is a short packet 0 packet size maximum packet size 7 When either the application or the DMA pops this entry OUT Data Transfer Completed a Transfer Completed interrupt is generated for the endpoint and the endpoint enable is cleared Application Programming Sequence 1 Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count Additionally in DMA ...

Page 299: ...ndpoint internally to prevent it from receiving any more packets 5 The application processes the interrupt and reads the data from the RxFIFO 6 When the application has read all the data equivalent to XFERSIZE the core generates a USB_DOEPx_INT XFERCOMPL interrupt 7 The application processes the interrupt and uses the setting of the USB_DOEPx_INT XFERCOMPL interrupt bit to determine that the inten...

Page 300: ...r the transfer size and the corresponding packet count When in DMA mode also program the USB_DOEPx_DMAADDR register 2 Program the USB_DOEPx_CTL register with the endpoint characteristics and set the Endpoint Enable ClearNAK and Even Odd frame bits Endpoint Enable 1 CNAK 1 Even Odd frame 0 Even 1 Odd 1 In Slave mode wait for the USB_GINTSTS Rx StsQ level interrupt and empty the data packets from th...

Page 301: ... frame number on which a specific packet has been received 4 On USB_DOEPx_INT XFERCOMPL interrupt the application must read the endpoint s Transfer Size register to calculate the size of the payload in the memory The received payload size can be less than the programmed transfer size Payload size in memory application programmed initial transfer size core updated final transfer size Number of USB ...

Page 302: ...escribed in Endpoint Initialization p 285 For packet writes in Slave mode see Packet Read from FIFO in Slave Mode p 294 Application Requirements 1 Before setting up ISOC OUT transfers spanned across multiple frames the application must allocate buffer in the memory to accommodate all data to be received as part of the OUT transfers then program that buffer s size and start address in the endpoint ...

Page 303: ...ability of space in the RxFifo or due to any packet errors the endpoint enable bit is cleared In case of packet drop on the USB application must re enable the endpoint after recalculating the values USB_DOEPx_TSIZ XFERSIZE and USB_DOEPx_TSIZ PKTCNT Payload size in memory application programmed initial transfer size core updated final transfer size Number of USB packets in which this payload was re...

Page 304: ...t NO Re compute XFERSIZE and ERROR NO USB_DOEPx_CTL SNAK USB_DOEPx_CTL EPDIS USB_DOEPx_DMA PKTCNT Internal Data Flow 1 The application must set the Transfer Size Packets to be received in a frame and Packet Count Fields in the endpoint specific registers clear the NAK bit and enable the endpoint to receive the data 2 When an isochronous OUT endpoint is enabled by setting the Endpoint Enable and cl...

Page 305: ... return Receive Pkt and Store in RXFifo PktCnt PktCnt 1 DMA Pop RxFifo XferSize XferSize MaxPktSize PKtSize MaxPktSize NO Received Short Packet PktCnt PktCnt 1 NO If PktCnt 0 XferSize 0 USB_DOEPx_INT XFERCOMPL 1 DMA Pop RxFifo XferSize XferSize ActPktSize YES YES If End Of PerFrInt ISOC Out Packet Naked Disable endpoint YES NO YES YES A NO NO A YES Disable endpoint NO 15 4 4 2 2 12 Incomplete Isoc...

Page 306: ...ol registers of all isochronous OUT endpoints USB_DOEPx_CTL to determine which endpoints had an incomplete transfer in the current frame An endpoint transfer is incomplete if both the following conditions are met USB_DOEPx_CTL DPIDEOF Even Odd frame USB_DSTS SOFFN 0 USB_DOEPx_CTL EPENA Endpoint Enable 1 7 The previous step must be performed before the USB_GINTSTS SOF interrupt is detected to ensur...

Page 307: ...ng transfer complete for the previous transaction 15 4 4 2 3 2 Setting Global Non Periodic IN Endpoint NAK Internal Data Flow 1 When the application sets the Global Non periodic IN NAK bit USB_DCTL SGNPINNAK the core stops transmitting data on the non periodic endpoint irrespective of data availability in the Non periodic Transmit FIFO 2 Non isochronous IN tokens receive a NAK handshake reply 3 Th...

Page 308: ...fective bit USB_DIEPMSK INEPNAKEFFMSK NAK Effective 0 5 To exit Endpoint NAK mode the application must clear the USB_DIEPx_CTL NAK status This also clears the USB_DIEPx_INT INEPNAKEFF NAK Effective interrupt USB_DIEPx_CTL CNAK 1 6 If the application masked this interrupt earlier it must be unmasked as follows USB_DIEPMSK INEPNAKEFFMSK NAK Effective 1 15 4 4 2 3 4 IN Endpoint Disable Use the follow...

Page 309: ...r the endpoint on the USB 3 On receiving the interrupt the application flushes the Non periodic Transmit FIFO and clears the USB_DCTL SGNPINNAK Global IN NP NAK bit 4 On receiving the ClearFeature Endpoint Halt command the application clears the Stall bit 5 The endpoint behaves normally and the application can re enable the endpoint for new transfers Figure 15 25 Bulk IN Stall Host Application Dev...

Page 310: ... Transfer interrupt indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints 3 The application must read the Endpoint Control register for all isochronous IN endpoints to detect endpoints with incomplete IN data transfers 4 In Slave mode the application must stop writing data to the Periodic Transmit FIFOs associated with these endpoints on the AHB 5 In both ...

Page 311: ... core responds to bulk interrupt tokens with a NAK and drops isochronous and SETUP tokens The host interprets this as a timeout condition for SETUP and retries the SETUP packet For isochronous transfers the INCOMPISOIN and INCOMPLP interrupts inform the application that isochronous IN OUT packets were dropped 15 4 4 2 3 9 Choosing the Value of USB_GUSBCFG USBTRDTIM The value in USB_GUSBCFG USBTRDT...

Page 312: ...ch is very close to SOF the core generates an early_suspend interrupt USB_GINTSTS ERLYSUSP On receiving this interrupt the application must check the erratic_error status bit USB_DSTS ERRTICERR If this bit is set the application must take it as a long babble and perform a soft reset 15 4 4 2 3 11 Generic Non Periodic Bulk and Control IN Data Transfers in DMA and Slave Mode To initialize the core a...

Page 313: ... Transfer Size and Packet Count fields in the endpoint specific registers and enable the endpoint to transmit the data 2 In Slave mode the application must also write the required data to the transmit FIFO for the endpoint In DMA mode the core fetches the data from memory according to the application setting for the endpoint 3 Every time a packet is written into the transmit FIFO either by the cor...

Page 314: ...ta is available in the transmit FIFO 3 To indicate to the application that there was no data to send the core generates a USB_DIEPx_INT INTKNTXFEMP IN Token Received When TxFIFO Empty interrupt 4 When data is ready the application sets up the USB_DIEPx_TSIZ register with the Transfer Size and Packet Count fields 5 The application writes one maximum packet size or less of data to the Non periodic T...

Page 315: ...6 The host reattempts the IN token 7 Because data is now ready in the FIFO the core responds with the data and the host ACKs it 8 When the TxFIFO level falls below the halfway mark the core generates a USB_GINTSTS NPTXFEMP NonPeriodic TxFIFO Empty interrupt This triggers the application to start writing additional data packets to the FIFO 9 A data packet for the second transaction is ready in the ...

Page 316: ...r with the Transfer Size and Packet Count fields The application starts writing the transaction data to the transmit FIFO 4 The application writes one maximum packet size or less of data for endpoint 1 to the Non periodic TxFIFO 5 Meanwhile the host attempts to read data IN token from endpoint 2 6 On receiving the IN token on the USB the core returns a NAK handshake because no data is available in...

Page 317: ...dpoint one packet has been sent and XFERSIZE is now zero the intended transfer is complete The core generates a USB_DIEP1_INT XFERCOMPL interrupt for this endpoint 23 The application processes the interrupt and uses the setting of the USB_DIEP1_INT XFERCOMPL interrupt bit to determine that the intended transfer on endpoint 1 is complete Figure 15 29 Slave Mode Bulk IN Two Endpoint Transfer 10 byte...

Page 318: ... can schedule data transfers for multiple frames only if multiples of max packet sizes up to 3 packets must be transmitted every frame This is can be done only when the core is operating in DMA mode This is not a recommended mode though n USB_DIEPx_TSIZ MC 1 USB_DIEPx_CTL MPS USB_DIEPx_TSIZ XFERSIZE n USB_DIEPx_TSIZ MC USB_DIEPx_CTL MPS USB_DIEPx_TSIZ PKTCNT n USB_DIEPx_TSIZ MC n is the number of ...

Page 319: ...et the CNAK and Endpoint Enable bits 3 In Slave mode write the data to be transmitted in the next frame to the transmit FIFO 4 Asserting the USB_DIEPx_INT INTKNTXFEMP In Token Received When TxFifo Empty interrupt indicates that either the DMA or application has not yet written all data to be transmitted to the transmit FIFO 5 If the interrupt endpoint is already enabled when this interrupt is dete...

Page 320: ...p 0 packet count epnum n 1 Otherwise packet count epnum n mc epnum number of packets to be sent out in a frame e The application cannot transmit a zero length data packet at the end of transfer It can transmit a single zero length data packet by itself To transmit a single zero length data packet transfer size epnum 0 packet count epnum 1 mc epnum packet count epnum 3 In DMA mode the core fetches ...

Page 321: ...re will read packets from System Memory only from DWORD aligned addresses 6 If MaxPktSize is not DWORD aligned Application must insert pads at the end of the packet so that new packet is always DWORD aligned 7 Thresholding in not supported for the Periodic Transfer Interrupt enhancement START De allocate Data Ram Mem ory Program EP Ctrl register to start the xfer USB_DIEPx_CTL CNAK 0b1 USB_DIEPx_C...

Page 322: ...the USB_DCFG PERFRINT register core will internally set the even odd internal bit to match the next frame 6 The packet count for the endpoint is decremented by 1 under the following conditions For isochronous endpoints when a zero or non zero length data packet is transmitted For interrupt endpoints when an ACK handshake is transmitted 7 The data PID of the transmitted data packet is based on the ...

Page 323: ...fication The core is an OTG device supporting HNP and SRP When the core is connected to an A plug it is referred to as an A device When the core is connected to a B plug it is referred to as a B device In Host mode the core turns off Vbus to conserve power SRP is a method by which the B device signals the A device to turn on Vbus power A device must perform both data line pulsing and Vbus pulsing ...

Page 324: ...nd Status register The core perform data line pulsing followed by Vbus pulsing 5 The host detects SRP from either the data line or Vbus pulsing and turns on Vbus The PHY indicates Vbus power on by detecting a valid VBUS level 6 The core performs Vbus pulsing The host starts a new session by turning on Vbus indicating SRP success The core interrupts the application by setting the Session Request Su...

Page 325: ...Enable bit in the OTG Control and Status register to indicate HNP support The application sets the HNP Request bit in the OTG Control and Status register to indicate to the core to initiate HNP 2 When it has finished using the bus the A device suspends by writing the Port Suspend bit in the Host Port Control and Status register The core sets the Early Suspend bit in the Core Interrupt register aft...

Page 326: ...upports enhanced SRP and HNP which are described in the following sections OTG Revision 2 0 Session Request Protocol p 326 OTG Revision 2 0 Host Negotiation Protocol p 328 Note VBUS pulsing is not supported in OTG Revision 2 0 mode 15 4 6 1 OTG Revision 2 0 Session Request Protocol When the core is behaving as an A device it can power off VBUS when no session is active until the B device initiates...

Page 327: ...ected during this process it means that the connector has been plugged out or interchanged This can be confirmed by reading Host mode PHY not driving VBUS Program USB_GINTMSK Unmask OTGINT MODEMIS SESSREQINT GINTSTS SESSREQINT 1 USB_GINTSTS CONIDSTSCHNG Host Initialization Steps Refer to the Host Initialization section of this chapter for more information In this step the OTG FSM is in a_host stat...

Page 328: ...tions Device OTG FSM in b_idle state USB_GOTGCTL BSESVLD 1 Set USB_GOTGCTL SESREQ 1 USB_GINTSTS OTGINT 1 Note The programming flow illustrated in Figure 15 33 p 328 is similar to OTG revision 1 3 This is because the presence or absence of VBUS pulsing is transparent to the application 15 4 6 2 OTG Revision 2 0 Host Negotiation Protocol When the core is operating as A device the application must ex...

Page 329: ... transactions C1 C1 Interrupt No No Yes Read USB_GINTSTS Interrupt No No Yes A Device as USB Host Read USB_GINTSTS Interrupt within 200 ms yes No Yes No A Device as USB Device Read USB_GINTSTS Check that CURMOD 0 Host Mode Transactions Yes Application starts 200 ms timer Host Initialization Steps For more information see Host Initialization section of this chapter USB_GINTSTS ERLYSUSP 1 USB_GINTST...

Page 330: ...ialization Steps For more information see Device Initialization section in this chapter USB_GOTGINT HSTNEGSUCSTSCHNG 1 USB_GOTGCTL DEVSETHNPEN 1 USB_GOTGCTL HNPREQ 1 USB_GINTSTS ERLYSUSP 1 USB_GINTSTS USBSUSP 1 USB_GINTSTS OTGINT 1 Clear USB_GOTGINT HSTNEGSUCSTSCHNG USB_GOTGCTL HSTNEGSUCS 1 Read USB_GINTSTS Check that CURMOD 1 Host Initialization Steps USB_HPRT PRTPWR should not be programmed For ...

Page 331: ... stored at the end of the FIFO RAM after the space allocated for receive and Transmit FIFO These register space must also be taken into account when calculating the total FIFO depth of the core as explained in the following sections The registers USB_DIEPx_DMAADDR USB_DOEPx_DMAADDR are maintained in RAM The following rules apply while calculating how much RAM space must be allocated to store these...

Page 332: ...packets OUT endpoint control information and data OUT packets as mentioned earlier Transmit FIFO 0 tx_fifo_size 0 Transmit FIFO 1 tx_fifo_size 1 Transmit FIFO 2 tx_fifo_size 2 Transmit FIFO i tx_fifo_size i With this information the following registers must be programmed as follows 1 Receive FIFO Size Register USB_GRXFSIZ USB_GRXFSIZ Receive FIFO Depth rx_fifo_size 2 Device IN Endpoint Transmit FI...

Page 333: ...ntrol OUT endpoint and three Bulk OUT endpoints and all these must fit into the non periodic TX_FIFO at the same time then four extra locations are required in the RX FIFO to store the rewind status information for each of these endpoints Transmit FIFO RAM allocation The minimum amount of RAM required for the Host Non periodic Transmit FIFO is the largest maximum packet size among all supported no...

Page 334: ... 2 2 2 is required by the core for the status quadlets internally 15 4 7 1 3 2 Non periodic TX FIFO size This should be equal to at least twice the largest value of MPS size used The recommended minimum non periodic TXFIFO depth largest packet size 4 2 15 4 7 1 3 3 Periodic TX FIFO size The recommended size for Periodic TXFIFO is sum total of MPS MC 4 for all the channels Note Note In the above re...

Page 335: ...d minimum FIFO depth allocation with support for high bandwidth endpoints This FIFO allocation enables the core to transfer a packet on the USB while the previous next packet is simultaneously transferred to the AHB This FIFO allocation improves the core s performance Device RxFIFO 4 number of control endpoints 6 2 largest USB packet used 4 1 2 number of OUT endpoints 1 Host RxFIFO Slave mode 2 la...

Page 336: ...alue is rounded to the nearest integer For example x 20 ms 17 039 ms 1 17 ms 2 ms Device RxFIFO 4 number of control endpoints 6 x 1 largest USB packet used 4 1 2 number of OUT endpoints 1 Note Include the Control OUT endpoint in the number of OUT endpoints Host RxFIFO Slave mode x 1 largest USB packet used 4 1 1 DMA mode x 1 largest USB packet used 4 1 1 1 location each bulk control out endpoint f...

Page 337: ...de In Device mode before changing FIFO data RAM allocation the application must determine the following All IN and OUT endpoints are disabled NAK mode is enabled in the core on all IN endpoints Global OUT NAK mode is enabled in the core All FIFOs are empty Once these conditions are met the application can reallocate FIFO data RAM as explained in Data FIFO RAM Allocation p 331 When NAK mode is enab...

Page 338: ...TL AHBIDLE until it is 1 AHBIDLE 1 indicates that the core is not reading anything from the FIFO 4 Set USB_GRSTCTL RXFFLSH 1 and wait for it to clear 5 Set the USB_DCTL GCOUTNAK bit The Core Interrupt Handler Figure 15 36 Core Interrupt Handler otg_intr _ handler Wait for interrupt OTG interrupt Read USB_GINTSTS Yes Read USB_GOTGCTL Generate OTG software interrupt Clear interrupt Host Device commo...

Page 339: ...owing bits in the USB_HPRT register USB_HPRT PRTPWR 0 USB_HPRT PRTENA 0 2 To put PHY in low power mode perform read modify write operation to set the following bits in the USB_PCGCCTL register USB_PCGCCTL STOPPCLK 1 USB_PCGCCTL GATEHCLK 0 Programming flow for the Host Core to make PHY exit low power mode If your device is non SRP capable the host must implement polling to detect the device connect...

Page 340: ...section discusses methods of conserving power by using one of the above methods 15 4 8 2 1 Using EM2 15 4 8 2 1 1 Overview of the EM2 Programming Model When the USB is suspended or the session is not valid the PHY is driven into Suspend mode stopping the PHY clock to reduce power consumption in the PHY and the core To further reduce power consumption the core also supports AHB clock gating and usi...

Page 341: ...arts earlier 7 The application clears the Port Resume bit and the core stops driving Resume signaling The core is in normal operating mode Note The application must insert delays of at least 2 PHY clocks between all steps in this sequence This requirement applies to all USB EM2 programming sequences Host Mode Remote Wakeup in EM2 Sequence of operations 1 The core detects Remote Wakeup signaling on...

Page 342: ...t EM2 Enter EM0 2 Switch USBC clock back to 48 MHz 3 The application clears the Stop PHY Clock bit 4 The application clears the Power Clamp bit The application clears the Reset to Power Down Modules bit 5 The application programs CSRs and sets the Port Power bit to turn on VBUS 6 The core detects the connection and drives the USB reset The core enters normal operating mode Host Mode Session End EM...

Page 343: ...uired 75 clock cycles at 32 KHz to detect the resume Hence the application programs USB_DCFG RESVALID with a value of 4 clock cycles 125 µs If the core is in Suspend mode the device thus detects the resume and the host signals a resume for a minimum of 125 µs If the device is being reset from suspend it begins a high speed detection handshake after detecting SE0 for no fewer than 2 5 µs With a 48 ...

Page 344: ...then sets the Power On Programming Done bit in the Device Control register Device Mode Remote Wakeup EM2 EM0 Sequence if operations 1 An interrupt wakes up the device from EM2 2 Switch USB Core Clock USBC back to 48 MHz 3 The application clears the STOPPCLK and GATEHCLK bits in the USB_PCGCCTL register 4 The application clears the USB_PCGCCTL PWRCLMP and USB_PCGCCTL RSTPDWNMODULE bits 5 Restore th...

Page 345: ...lears the Reset to Power Down Modules bit 6 The application programs CSRs 7 The cores detects a USB reset The core enters normal operating mode 15 4 8 2 2 Using Clock Gating in EM0 EM1 The core supports HCLK gating to reduce dynamic power to internal modules to the core during Suspend session off state in EM0 and EM1 15 4 8 2 2 1 Internal Clock Gating when the Core is in Host Mode The following se...

Page 346: ...on clears the Stop PHY Clock bit to start the PHY clock 6 The application sets the Port Power bit to turn on VBUS 7 The core detects device connection and drives a USB reset 8 The core is in normal operating mode Host Mode Session End and SRP With Clock Gating Sequence of operations 1 The application sets the Port Suspend bit in the Host Port CSR and the core drives a USB suspend 2 The application...

Page 347: ...The host turns off VBUS 2 The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register The application sets the Gate hclk bit in the Power and Clock Gating Control register and the core gates hclk 3 The core remains in Low Power mode 4 The new session is detected A session valid voltage is detected A New Session Detected interrupt is generated 5 The application clears...

Page 348: ...and typically start with first letter G Host Mode Registers are located in the address offset range 0x3C400 0x3C7FF and start with first letter H Device Mode Registers are located in the address offset range 0x3C800 0x3CDFF and start with first letter D The Power and Clock Gating register is located at offset 0x3CE00 The Device EP Host Channel FIFOs start at address offset 0x3D000 with 4K spacing ...

Page 349: ...gister 0x3C05C USB_GDFIFOCFG RW Global DFIFO Configuration Register 0x3C100 USB_HPTXFSIZ RW Host Periodic Transmit FIFO Size Register 0x3C104 USB_DIEPTXF1 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x3C108 USB_DIEPTXF2 RW Device IN Endpoint Transmit FIFO 2 Size Register 0x3C10C USB_DIEPTXF3 RW Device IN Endpoint Transmit FIFO 3 Size Register 0x3C110 USB_DIEPTXF4 RW Device IN Endpoint Tran...

Page 350: ...C908 USB_DIEP0INT RWH Device IN Endpoint 0 Interrupt Register 0x3C910 USB_DIEP0TSIZ RW Device IN Endpoint 0 Transfer Size Register 0x3C914 USB_DIEP0DMAADDR RW Device IN Endpoint 0 DMA Address Register 0x3C918 USB_DIEP0TXFSTS R Device IN Endpoint 0 Transmit FIFO Status Register 0x3C920 USB_DIEP0_CTL RWH Device IN Endpoint x 1 Control Register 0x3C928 USB_DIEP0_INT RWH Device IN Endpoint x 1 Interru...

Page 351: ...e OUT Endpoint x 1 Transfer Size Register 0x3CB34 USB_DOEP0_DMAADDR RW Device OUT Endpoint x 1 DMA Address Register 0x3CB40 USB_DOEP1_CTL RWH Device OUT Endpoint x 1 Control Register 0x3CB48 USB_DOEP1_INT RWH Device OUT Endpoint x 1 Interrupt Register 0x3CB50 USB_DOEP1_TSIZ RWH Device OUT Endpoint x 1 Transfer Size Register 0x3CB54 USB_DOEP1_DMAADDR RW Device OUT Endpoint x 1 DMA Address Register ...

Page 352: ... FIFO 0x427FC USB_FIFO5D511 RW Device EP 5 Host Channel 5 FIFO 0x43000 USB_FIFO6D0 RW Device EP 6 Host Channel 6 FIFO USB_FIFO6Dx RW Device EP 6 Host Channel 6 FIFO 0x437FC USB_FIFO6D511 RW Device EP 6 Host Channel 6 FIFO 0x44000 USB_FIFO7D0 RW Host Channel 7 FIFO USB_FIFO7Dx RW Host Channel 7 FIFO 0x447FC USB_FIFO7D511 RW Host Channel 7 FIFO 0x45000 USB_FIFO8D0 RW Host Channel 8 FIFO USB_FIFO8Dx ...

Page 353: ...SB in suspend 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 21 20 BIASPROGEM01 0x0 RW Regulator Bias Programming Value in EM0 1 Regulator bias current setting in EM0 1 i e while USB active 19 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 17 VREGOSEN 0 RW VREG...

Page 354: ...gister Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 1 Access R R Name VREGOSL VREGOSH Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 VREGOSL 1 R VREGO Sense Low Interrupt Flag Set when USB_VREGO drops below approximatel...

Page 355: ...tibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 VREGOSL 0 W1 Clear VREGO Sense Low Interrupt Flag Write to 1 to clear the VREGO Sense Low Interrupt Flag 0 VREGOSH 0 W1 Clear VREGO Sense High Interrupt Flag Write to 1 to clear the VREGO Sense High Interrupt Flag 15 6 6 USB_IEN Interrupt Enable Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22...

Page 356: ...ion of the core Offset Bit Position 0x3C000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Access RW R R R R RW RW RW R RW RW RW RW RW RW RW R Name OTGVER BSESVLD ASESVLD DBNCTIME CONIDSTS DEVHNPEN HSTSETHNPEN HNPREQ HSTNEGSCS AVALIDOVVAL AVALIDOVEN BVALIDOVVAL BVALIDOVEN VBVALIDOVVAL VBVALIDOVEN SESREQ SESREQSCS Bit Na...

Page 357: ...de value for Avalid signal when USB_GOTGCTL AVALIDOVEN is set 6 AVALIDOVEN 0 RW AValid Override Enable This bit is used to enable disable the software to override the Avalid signal using the USB_GOTGCTL AVALIDOVVAL When set Avalid received from the PHY is overridden with USB_GOTGCTL AVALIDOVVAL 5 BVALIDOVVAL 0 RW Bvalid Override Value This bit is used to set Override value for Bvalid signal when U...

Page 358: ...ibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 HSTNEGSUCSTSCHNG 0 RW1H Host Negotiation Success Status Change host and device The core sets this bit on the success or failure of a USB host negotiation request The application must read the Host Negotiation Success bit of the OTG Control and Status register USB_GOTGCTL HSTNEGSCS to check for success or failu...

Page 359: ...ete the Data Transfer corresponding to a particular Channel Endpoint When cleared the int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the HSOTG Core Boundary and it doesn t wait for the sys_dma_done signal to complete the DATA 20 9 Reserved To ensure compatibility with future devic...

Page 360: ...t and device This bit is for debug purposes only Never Set this bit to 1 The application should always write 0 to this bit 30 FORCEDEVMODE 0 RW Force Device Mode host and device Writing a 1 to this bit forces the core to device mode irrespective of the state of the ID pin After setting the force bit the application must wait at least 25 ms before the change to take effect 29 FORCEHSTMODE 0 RW Forc...

Page 361: ...8 7 6 5 4 3 2 1 0 Reset 1 0 0x00 0 0 0 0 Access R R RW RW1H RW1H RW1H RW1H Name AHBIDLE DMAREQ TXFNUM TXFFLSH RXFFLSH FRMCNTRRST CSFTRST Bit Name Reset Access Description 31 AHBIDLE 1 R AHB Master Idle host and device Indicates that the AHB Master State Machine is in the IDLE condition 30 DMAREQ 0 R DMA Request Signal host and device Indicates that the DMA request is in progress Used for debug 29 ...

Page 362: ... phase of an AHB transfer Any transactions on the USB are terminated immediately The application can write to this bit any time it wants to reset the core This is a self clearing bit and the core clears this bit after all the necessary logic is reset in the core which can take several clocks depending on the current state of the core Once this bit is cleared software must wait at least 3 clock cyc...

Page 363: ...ce This interrupt is used by the application for an endpoint mismatch algorithm For example after detecting an endpoint mismatch the application Sets a Global non periodic IN NAK handshake Disables In endpoints Flushes the FIFO Determines the token sequence from the IN Token Sequence Re enables the endpoints Clears the Global non periodic IN NAK handshake If the Global non periodic IN NAK is clear...

Page 364: ...the Clear Global Non periodic IN NAK bit in the Device Control register USB_DCTL CGNPINNAK This interrupt does not necessarily mean that a NAK handshake is sent out on the USB The STALL bit takes precedence over the NAK bit 5 NPTXFEMP 1 R Non Periodic TxFIFO Empty host only This interrupt is asserted when the Non periodic TxFIFO is either half or completely empty and there is space for at least on...

Page 365: ...upt Mask host and device Set to 1 to unmask SESSREQINT interrupt 29 DISCONNINTMSK 0 RW Disconnect Detected Interrupt Mask host and device Set to 1 to unmask DISCONNINT interrupt 28 CONIDSTSCHNGMSK 0 RW Connector ID Status Change Mask host and device Set to 1 to unmask CONIDSTSCHNG interrupt 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2...

Page 366: ... 0 RW Non Periodic TxFIFO Empty Mask host only Set to 1 to unmask NPTXFEMP interrupt 4 RXFLVLMSK 0 RW Receive FIFO Non Empty Mask host and device Set to 1 to unmask RXFLVL interrupt 3 SOFMSK 0 RW Start of Frame Mask host and device Set to 1 to unmask SOF interrupt 2 OTGINTMSK 0 RW OTG Interrupt Mask host and device Set to 1 to unmask OTGINT interrupt 1 MODEMISMSK 0 RW Mode Mismatch Interrupt Mask ...

Page 367: ...Description 0 DATA0 DATA0 PID 1 DATA1 DATA1 PID 2 DATA2 DATA2 PID 3 MDATA MDATA PID 14 4 BCNT 0x000 R Byte Count host or device Host mode Indicates the byte count of the received IN data packet Device mode Indicates the byte count of the received data packet 3 0 CHEPNUM 0x0 R Channel Number host only Endpoint Number device only Host mode Indicates the channel number to which the current received p...

Page 368: ...icates the Data PID of the received packet Device mode Indicates the Data PID of the received OUT data packet Value Mode Description 0 DATA0 DATA0 PID 1 DATA1 DATA1 PID 2 DATA2 DATA2 PID 3 MDATA MDATA PID 14 4 BCNT 0x000 R Byte Count host or device Host mode Indicates the byte count of the received IN data packet Device mode Indicates the byte count of the received data packet 3 0 CHEPNUM 0x0 R Ch...

Page 369: ...it RAM Start Address host only This field contains the memory start address for Non periodic Transmit FIFO RAM Programmed values must not exceed the reset value 15 6 19 USB_GNPTXSTS Non periodic Transmit FIFO Queue Status Register This register is used in host mode only This read only register contains the free space information for the Non periodic TxFIFO and the Nonperiodic Transmit Request Queu...

Page 370: ... Endpoint Info Base Address This field provides the start address of the EP info controller 15 0 GDFIFOCFG 0x0200 RW DFIFO Config This field is for dynamic programming of the DFIFO Size This value takes effect only when the application programs a non zero value to this register The core does not have any corrective logic if the FIFO sizes are programmed incorrectly 15 6 21 USB_HPTXFSIZ Host Period...

Page 371: ...um value is 512 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 0 INEPNTXFSTADDR 0x400 RW IN Endpoint FIFO 1 Transmit RAM Start Address This field contains the memory start address for IN endpoint Transmit FIFO 1 15 6 23 USB_DIEPTXF2 Device IN Endpoint Transmit FIFO 2 Size Register This register holds the size and memory star...

Page 372: ...P 0x200 RW IN Endpoint TxFIFO Depth This value is in terms of 32 bit words Minimum value is 16 Maximum value is 512 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 0 INEPNTXFSTADDR 0x800 RW IN Endpoint FIFO 3 Transmit RAM Start Address This field contains the memory start address for IN endpoint Transmit FIFO 3 15 6 25 USB_DI...

Page 373: ...ity with future devices always write bits to 0 More information in Section 2 1 p 3 25 16 INEPNTXFDEP 0x200 RW IN Endpoint TxFIFO Depth This value is in terms of 32 bit words Minimum value is 16 Maximum value is 512 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 0 INEPNTXFSTADDR 0xC00 RW IN Endpoint FIFO 5 Transmit RAM Start ...

Page 374: ...ith future devices always write bits to 0 More information in Section 2 1 p 3 15 8 RESVALID 0x00 RW Resume Validation Period This field is effective only when USB_HCFG ENA32KHZS is set It will control the resume period when the core resumes from suspend The core counts for RESVALID number of clock cycles to detect a valid resume when USB_HCFG ENA32KHZS is set 7 ENA32KHZS 0 RW Enable 32 KHz Suspend...

Page 375: ... to this register only after the Port Enable bit of the Host Port Control and Status register USB_HPRT PRTENA has been set If no value is programmed the core calculates the value based on the PHY clock specified in the FS LS PHY Clock Select field of the Host Configuration register USB_HCFG FSLSPCLKSEL Do not change the value of this field after the initial configuration Set to 48000 1 ms at 48 MH...

Page 376: ...d 11 Disable channel command Bit 0 Terminate last Entry for the selected channel endpoint 23 16 PTXQSPCAVAIL 0x08 R Periodic Transmit Request Queue Space Available Indicates the number of free locations available to be written in the Periodic Transmit Request Queue This queue holds both IN and OUT requests 15 0 PTXFSPCAVAIL 0x0200 R Periodic Transmit Data FIFO Space Available Indicates the number ...

Page 377: ...000 RW Channel Interrupt Mask for channel 0 13 Set bit n to unmask channel n interrupts 15 6 34 USB_HPRT Host Port Control and Status Register This register is available only in Host mode This register holds USB port related information such as USB reset enable suspend resume connect status and test mode for the port Some bits in this register can trigger an interrupt to the application through th...

Page 378: ...e port This bit is cleared by the core after a remote wakeup signal is detected or the application sets the Port Reset bit or Port Resume bit in this register or the Resume Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register USB_GINTSTS WKUPINT or USB_GINTSTS DISCONNINT respectively This bit is cleared by the core even if there is no device conn...

Page 379: ...ore the transfer for that channel is complete The application must wait for the Channel Disabled interrupt before treating the channel as disabled 29 ODDFRM 0 RW Odd Frame This field is set reset by the application to indicate that the OTG host must perform a transfer in an odd frame This field is applicable for only periodic isochronous and interrupt transactions 28 22 DEVADDR 0x00 RW Device Addr...

Page 380: ...LTD XFERCOMPL Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 DATATGLERR 0 RW1H Data Toggle Error This bit can be set only by the core and the application should write 1 to clear it 9 FRMOVRUN 0 RW1H Frame Overrun This bit can be set only by the core and the application should write 1 to clea...

Page 381: ...SK BBLERRMSK XACTERRMSK ACKMSK NAKMSK STALLMSK AHBERRMSK CHHLTDMSK XFERCOMPLMSK Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 DATATGLERRMSK 0 RW Data Toggle Error Mask Set to unmask DATATGLERR interrupt 9 FRMOVRUNMSK 0 RW Frame Overrun Mask Set to unmask FRMOVRUN interrupt 8 BBLERRMSK 0 RW ...

Page 382: ...ield is programmed by the application with the expected number of packets to be transmitted OUT or received IN The host decrements this count on every successful transmission or reception of an OUT IN packet Once this count reaches zero the application is interrupted to indicate normal completion 18 0 XFERSIZE 0x00000 RW Transfer Size For an OUT this field is the number of data bytes the host send...

Page 383: ...rame at which the application must be notified using the End Of Periodic Frame Interrupt This can be used to determine if all the isochronous traffic for that frame is complete Value Mode Description 0 80PCNT 80 of the frame interval 1 85PCNT 85 of the frame interval 2 90PCNT 90 of the frame interval 3 95PCNT 95 of the frame interval 10 4 DEVADDR 0x00 RW Device Address The application must program...

Page 384: ...bal OUT NAK A write to this field sets the Global OUT NAK The application uses this bit to send a NAK handshake on all OUT endpoints The application must set this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register USB_GINTSTS GOUTNAKEFF is cleared 8 CGNPINNAK 0 W1 Clear Global Non periodic IN NAK A write to this field clears the Global Non periodic IN N...

Page 385: ...ame number This field may return a non zero value if read immediately after power on reset In case the register bits reads non zero immediately after power on reset it does not indicate that SOF has been received from the host The read value of this interrupt is valid only after a valid connection between host and device is established 7 4 Reserved To ensure compatibility with future devices alway...

Page 386: ...y with future devices always write bits to 0 More information in Section 2 1 p 3 6 INEPNAKEFFMSK 0 RW IN Endpoint NAK Effective Mask Set to 1 to unmask INEPNAKEFF Interrupt 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 INTKNTXFEMPMSK 0 RW IN Token Received When TxFIFO Empty Mask Set to 1 to unmask INTKNTXFEMP Interrupt 3 TIMEOUT...

Page 387: ...rupt Applies to control OUT endpoints only 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 OUTTKNEPDISMSK 0 RW OUT Token Received when Endpoint Disabled Mask Set to 1 to unmask OUTTKNEPDIS Interrupt Applies to control OUT endpoints only 3 SETUPMSK 0 RW SETUP Phase Done Mask Set to 1 to unmask SETUP Interrupt Applies to control end...

Page 388: ... of the interrupt flags in USB_DOEP0_INT are set 16 OUTEPINT0 0 R OUT Endpoint 0 Interrupt Bit This bit is set when one or more of the interrupt flags in USB_DOEP0INT are set 15 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 INEPINT6 0 R IN Endpoint 6 Interrupt Bit This bit is set when one or more of the interrupt flags in USB_DI...

Page 389: ..._DAINT OUTEPINT3 18 OUTEPMSK2 0 RW OUT Endpoint 2 Interrupt mask Bit Set to 1 to unmask USB_DAINT OUTEPINT2 17 OUTEPMSK1 0 RW OUT Endpoint 1 Interrupt mask Bit Set to 1 to unmask USB_DAINT OUTEPINT1 16 OUTEPMSK0 0 RW OUT Endpoint 0 Interrupt mask Bit Set to 1 to unmask USB_DAINT OUTEPINT0 15 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2...

Page 390: ...your VBUS load this value can need adjustment 15 6 48 USB_DVBUSPULSE Device VBUS Pulsing Time Register This register specifies the VBUS pulsing time during SRP Offset Bit Position 0x3C82C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x5B8 Access RW Name DVBUSPULSE Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future dev...

Page 391: ...eset Access Description 31 EPENA 0 RW1H Endpoint Enable In DMA mode this bit indicates that data is ready to be transmitted on the endpoint The core clears this bit before setting the following interrupts on this endpoint Endpoint Disabled Transfer Completed 30 EPDIS 0 RW1H Endpoint Disable The application sets this bit to stop transmitting data on an endpoint even before the transfer for that end...

Page 392: ...application must program this field with the maximum packet size for the current logical endpoint Value Mode Description 0 64B 64 bytes 1 32B 32 bytes 2 16B 16 bytes 3 8B 8 bytes 15 6 51 USB_DIEP0INT Device IN Endpoint 0 Interrupt Register This register indicates the status of endpoint 0 with respect to USB and AHB related events The application must read this register when the IN Endpoints Interr...

Page 393: ...n was received 3 TIMEOUT 0 RW1H Timeout Condition Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint 2 AHBERR 0 RW1H AHB Error This is generated in DMA mode when there is an AHB error during an AHB read write The application can read the corresponding endpoint DMA address register to get the error address 1 EPDISBLD 0 RW1H Endpoint Disabled I...

Page 394: ...y for fetching endpoint data For control endpoints this field stores control OUT data packets as well as SETUP transaction data packets When more than three SETUP packets are received back to back the SETUP data packet in the memory is overwritten This register is incremented on every AHB transaction The application can give only a DWORD aligned address The data for this register field is stored i...

Page 395: ...s the Endpoint Data PID Even or Odd Frame DPIDEOF field to odd DATA1ODD 28 SETD0PIDEF 0 W1 Set DATA0 PID Even Frame For bulk and interrupt endpoints writing this field sets the Endpoint Data PID Even or Odd Frame DPIDEOF field in this register to DATA0EVEN For isochronous endpoints writing this field sets the Endpoint Data PID Even or Odd Frame DPIDEOF field to odd DATA0EVEN 27 SNAK 0 W1 Set NAK A...

Page 396: ...DD DATA1 PID Odd Frame 15 USBACTEP 0 RW USB Active Endpoint Indicates whether this endpoint is active in the current configuration and interface The core clears this bit for all endpoints after detecting a USB reset After receiving the SetConfiguration and SetInterface commands the application must program endpoint registers accordingly and set this bit 14 11 Reserved To ensure compatibility with ...

Page 397: ...p 3 4 INTKNTXFEMP 0 RW1H IN Token Received When TxFIFO is Empty Applies to non periodic IN endpoints only Indicates that an IN token was received when the associated TxFIFO periodic non periodic was empty This interrupt is asserted on the endpoint for which the IN token was received 3 TIMEOUT 0 RW1H Timeout Condition Applies only to Control IN endpoints Indicates that the core has detected a timeo...

Page 398: ...external memory is written to the TxFIFO 15 6 58 USB_DIEPx_DMAADDR Device IN Endpoint x 1 DMA Address Register Offset Bit Position 0x3C934 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RW Name DMAADDR Bit Name Reset Access Description 31 0 DMAADDR 0xXXXXXXXX RW DMA Address Holds the start address of the external memory for fetching en...

Page 399: ...r the endpoint Using this bit the application can control the transmission of NAK handshakes on an endpoint The core can also set bit on a Transfer Completed interrupt or after a SETUP is received on the endpoint 26 CNAK 0 W1 Clear NAK A write to this bit clears the NAK bit for the endpoint 25 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sectio...

Page 400: ... RW1H RW1H Name NAKINTRPT BBLEERR PKTDRPSTS BACK2BACKSETUP OUTTKNEPDIS SETUP AHBERR EPDISBLD XFERCOMPL Bit Name Reset Access Description 31 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 NAKINTRPT 0 RW1H NAK Interrupt The core generates this interrupt when a NAK is transmitted or received by the device In case of isochronous IN...

Page 401: ...A the core modifies this register The application can only read this register once the core has cleared the Endpoint Enable bit Offset Bit Position 0x3CB10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0x00 Access RW RW RW Name SUPCNT PKTCNT XFERSIZE Bit Name Reset Access Description 31 Reserved To ensure compatibility with future devices always ...

Page 402: ...ical endpoint other than endpoint 0 Offset Bit Position 0x3CB20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0x0 0 0 0 0x000 Access RW1H RW1H W1 W1 W1 W1 RW1H RW RW R R RW RW Name EPENA EPDIS SETD1PIDOF SETD0PIDEF SNAK CNAK STALL SNP EPTYPE NAKSTS DPIDEOF USBACTEP MPS Bit Name Reset Access Description 31 EPENA 0 RW1H Endpoint Enable In...

Page 403: ...ness of OUT packets before transferring them to application memory 19 18 EPTYPE 0x0 RW Endpoint Type This is the transfer type supported by this logical endpoint Value Mode Description 0 CONTROL Control Endpoint 1 ISO Isochronous Endpoint 2 BULK Bulk Endpoint 3 INT Interrupt Endpoint 17 NAKSTS 0 R NAK Status When this bit is 0 the core is transmitting non NAK handshakes based on the FIFO status Wh...

Page 404: ...dicates to the application that an ISO OUT packet has been dropped This bit does not have an associated mask bit and does not generate an interrupt 10 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 BACK2BACKSETUP 0 RW1H Back to Back SETUP Packets Received Applies to Control OUT endpoints only This bit indicates that the core has ...

Page 405: ...ices always write bits to 0 More information in Section 2 1 p 3 30 29 RXDPIDSUPCNT 0x0 R Receive Data PID SETUP Packet Count For isochronous OUT endpoints This is the data PID received in the last packet for this endpoint For control OUT Endpoints This field specifies the number of back to back SETUP data packets the endpoint can receive Value Mode Description 0 DATA0 DATA0 PID 1 DATA2 DATA2 PID 1...

Page 406: ...tures Offset Bit Position 0x3CE00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access R R RW RW RW RW Name RESETAFTERSUSP PHYSLEEP RSTPDWNMODULE PWRCLMP GATEHCLK STOPPCLK Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 RESETAFTERSUSP 0 ...

Page 407: ...vice EP 0 Host Channel 0 FIFO This register available in both Host and Device modes is used to read or write the FIFO space for endpoint 0 or channel 0 in a given direction If a host channel is of type IN the FIFO can only be read on the channel Similarly if a host channel is of type OUT the FIFO can only be written on the channel Offset Bit Position 0x3D000 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 408: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RW Name FIFO2D Bit Name Reset Access Description 31 0 FIFO2D 0xXXXXXXXX RW Device EP 2 Host Channel 2 FIFO FIFO 2 push pop region Used in slave mode 15 6 72 USB_FIFO3Dx Device EP 3 Host Channel 3 FIFO This register available in both Host and Device modes is used to read or write the FIFO space for endp...

Page 409: ...10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RW Name FIFO4D Bit Name Reset Access Description 31 0 FIFO4D 0xXXXXXXXX RW Device EP 4 Host Channel 4 FIFO FIFO 4 push pop region Used in slave mode 15 6 74 USB_FIFO5Dx Device EP 5 Host Channel 5 FIFO This register available in both Host and Device modes is used to read or write the FIFO space for endpoint 5 or channel 5 in a given direction If a host...

Page 410: ...pop region Used in slave mode 15 6 76 USB_FIFO7Dx Host Channel 7 FIFO This register available in Host mode is used to read or write the FIFO space for channel 7 in a given direction If a host channel is of type IN the FIFO can only be read on the channel Similarly if a host channel is of type OUT the FIFO can only be written on the channel Offset Bit Position 0x44000 31 30 29 28 27 26 25 24 23 22 ...

Page 411: ...a host channel is of type IN the FIFO can only be read on the channel Similarly if a host channel is of type OUT the FIFO can only be written on the channel Offset Bit Position 0x46000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RW Name FIFO9D Bit Name Reset Access Description 31 0 FIFO9D 0xXXXXXXXX RW Host Channel 9 FIFO FIFO 9 pus...

Page 412: ... a host channel is of type IN the FIFO can only be read on the channel Similarly if a host channel is of type OUT the FIFO can only be written on the channel Offset Bit Position 0x48000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RW Name FIFO11D Bit Name Reset Access Description 31 0 FIFO11D 0xXXXXXXXX RW Host Channel 11 FIFO FIFO 1...

Page 413: ... 15 6 82 USB_FIFO13Dx Host Channel 13 FIFO This register available in Host mode is used to read or write the FIFO space for channel 13 in a given direction If a host channel is of type IN the FIFO can only be read on the channel Similarly if a host channel is of type OUT the FIFO can only be written on the channel Offset Bit Position 0x4A000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 414: ...FORAMx Direct Access to Data FIFO RAM for Debugging 2 KB Offset Bit Position 0x5C000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0xXXXXXXXX Access RW Name FIFORAM Bit Name Reset Access Description 31 0 FIFORAM 0xXXXXXXXX RW FIFO RAM Direct Access to Data FIFO RAM for Debugging 2 KB ...

Page 415: ...and slave and supports multi master buses Standard mode fast mode and fast mode plus speeds are supported allowing transmission rates all the way from 10 kbit s up to 1 Mbit s Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system The interface provided to software by the I 2 C module allows both fine grained control of the transmission process and cl...

Page 416: ...cludes collision detection and arbitration to resolve situations where multiple masters transmit data at the same time without data loss Figure 16 2 I 2 C Bus Example I2C master 1 I2C master 2 I2C slave 1 I2C slave 2 I2C slave 3 SDA SCL VDD Rp Each device on the bus is addressable by a unique address and an I 2 C master can address all the devices on the bus including other masters Both the bus li...

Page 417: ...n in Figure 16 2 p 416 Figure 16 4 I 2 C Bit Transfer on I 2 C Bus SCL SDA Data stable Data change allowed Data change allowed 16 3 1 2 Bus Transfer When a master wants to initiate a transfer on the bus it waits until the bus is idle and transmits a START condition on the bus The master then transmits the address of the slave it wishes to interact with and a single R W bit telling whether it wishe...

Page 418: ... P Figure 16 7 I 2 C Single Byte Write then Repeated Start and Single Byte Read R Sr ADDR DATA A N P W S ADDR DATA A A 16 3 1 3 Addresses I 2 C supports both 7 bit and 10 bit addresses When using 7 bit addresses the first byte transmitted after the START condition contains the address of the slave that the master wants to contact In the 7 bit address space several addresses are reserved These addr...

Page 419: ...e repeated start matches its own address An example of this with one byte transmitted is shown in Figure 16 9 p 419 Figure 16 9 I 2 C Master Receiver Slave Transmitter with 10 bit Address R Sr DATA A N P W S A A ADDR 1st 7 bits Addr 2nd byte ADDR 1st 7 bits 16 3 1 5 Arbitration Clock Synchronization Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi master ...

Page 420: ...e Tlow and Thigh is the low and high periods of the clock signal respectively given below When the clock is not streched the low and high periods of the clock signal are I 2 C High and Low Cycles Equations Thigh Nhigh CLKDIV 1 fHFPERCLK Tlow Nlow CLKDIV 1 fHFPERCLK 16 3 Equation 16 3 p 420 and Equation 16 2 p 420 does not apply for low clock division factors 0 1 and 2 because of synchronization Fo...

Page 421: ...the sensed value is different than the value the I 2 C module tried to output it is interpreted as a simultaneous transmission by another device and that the I 2 C module has lost arbitration Whenever arbitration is lost the ARBLOST interrupt flag in I2Cn_IF is set any lines held are released and the I 2 C device goes idle If an I 2 C master loses arbitration during the transmission of an address ...

Page 422: ...it Otherwise the byte waits in the shift register until space becomes available in the buffer When a byte becomes available in the receive buffer the RXDATAV in I2Cn_STATUS and RXDATAV interrupt flag in I2Cn_IF are set The data can now be fetched from the buffer using I2Cn_RXDATA Reading from this register will pull a byte out of the buffer making room for a new byte and clearing RXDATAV in I2Cn_S...

Page 423: ...the state machine ending the operation or continuing with a new operation when arriving at the right side of the state machine Branches in the path through the state machine are the results of bus events and choices made by software either directly or indirectly The dotted lines show where I 2 C specific interrupt flags are set along the path and the full drawn circles show places where interactio...

Page 424: ...e possible from a given state the course of action using the highest priority interactions that first has everything it is waiting for is the one that is taken Table 16 4 I 2 C Interactions in Prioritized Order Interaction Priority Software action Automatically continues if STOP 1 Set the STOP command bit in I2Cn_CMD PSTOP is set STOP pending in I2Cn_STATUS ABORT 2 Set the ABORT command bit in I2C...

Page 425: ...uses with little activity the time before the I 2 C module detects that the bus is idle can be significant There are two ways of assuring that the I 2 C module gets out of the busy state Use the ABORT command in I2Cn_CMD When the ABORT command is issued the I 2 C module is instructed that the bus is idle The I 2 C module can then initiate master operations Use the Bus Idle Timeout When SCL has bee...

Page 426: ...n In this case the ARBLOST interrupt flag in I2Cn_IF is set If the arbitration was lost during the transfer of an address and SLAVE in I2Cn_CTRL is set the master then checks which address was transmitted If it was the address of the master then the master goes to slave mode After a master has transmitted a START and won any arbitration it owns the bus until it transmits a STOP After a STOP the bu...

Page 427: ... the data register thus has to contain the 7 bit slave address in the 7 most significant bits of the byte and have the least significant bit set When the address has been transmitted the master receives an ACK or a NACK If an ACK is received the ACK interrupt flag in I2Cn_IF is set and if space is available in the receive shift register reception of a byte from the slave begins If the receive buff...

Page 428: ...nt when bus becomes idle ADDR R transmitted TXBL interrupt flag TXC interrupt flag None RXDATA Start receiving STOP STOP will be sent and the bus released START Repeated START will be sent 0x93 ADDR R transmitted ACK received ACK interrupt flag BUSHOLD STOP START STOP will be sent and the bus released Then a START will be sent when the bus becomes idle CONT RXDATA Continue start receiving STOP STO...

Page 429: ...has been received ADDRACK 4 Address ACK NACK being transmitted or received DATA 5 Data being transmitted or received DATAACK 6 Data ACK NACK being transmitted or received Table 16 8 I 2 C Transmission Status Bit Description BUSY Set whenever there is activity on the bus Whether or not this module is responsible for the activity cannot be determined by this byte MASTER Set when operating as a maste...

Page 430: ... energy modes except EM4 The slave address i e the address which the I 2 C module should be addressed with is defined in the I2Cn_SADDR register In addition to the address a mask must be specified telling the address comparator which bits of an incoming address to compare with the address defined in I2Cn_SADDR The mask is defined in I2Cn_SADDRMASK and for every zero in the mask the corresponding b...

Page 431: ...CK command The slave will in that case go to an idle state and wait for the next start condition To continue the transmission the slave must make sure data is loaded into the transmit buffer and send an ACK The loaded data will then be transmitted to the master and an ACK or NACK will be received from the master Data transmission can also continue after a NACK if a CONT command is issued along wit...

Page 432: ...tion that the address transmitted by the master has the R W bit cleared W indicating that the master wishes to write to the slave The slave then goes into slave receiver mode To receive data from the master the slave should respond to the address with an ACK and make sure space is available in the receive buffer Transmission will then continue and the slave will receive a byte from the master If a...

Page 433: ...et up to complete transfers with a minimal amount of interaction 16 3 10 1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer When using DMA software is thus relieved of moving data to and from memory after each transferred byte 16 3 10 2 Automatic ACK When AUTOACK in I2Cn_CTRL is set an ACK is sent automatically whenever an ACK intera...

Page 434: ...ich can be set in I2Cn_CMD to help resolve bus errors When the bus for some reason is locked up and the I 2 C module is in the middle of a transmission it cannot get out of or for some other reason the I 2 C wants to abort a transmission the ABORT command can be used Setting the ABORT command will make the I 2 C module discard any data currently being transmitted or received release the SDA and SC...

Page 435: ... timeout BITO in I2Cn_CTRL can be used to detect situations where the bus goes idle in the middle of a transmission The timeout can be configured in BITO and when the bus has been idle for the given amount of time the BITO interrupt flag in I2Cn_IF is set The bus can also be set idle automatically on a bus idle timeout This is enabled by setting GIBITO in I2Cn_CTRL When the bus idle timer times ou...

Page 436: ...interrupts generated by the I 2 C module are combined into one interrupt vector I2C_INT If I 2 C interrupts are enabled an interrupt will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set 16 3 15 Wake up The I 2 C receive section can be active all the way down to energy mode EM3 and can wake up the CPU on address interrupt All address match m...

Page 437: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0x0 0x0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW Name CLTO GIBITO BITO CLHR GCAMEN ARBDIS AUTOSN AUTOSE AUTOACK SLAVE EN Bit Name Reset Access Description 31 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 18 16 CLTO 0x0 RW Clock Low ...

Page 438: ... bits to 0 More information in Section 2 1 p 3 9 8 CLHR 0x0 RW Clock Low High Ratio Determines the ratio between the low and high parts of the clock signal generated on SCL as master Value Mode Description 0 STANDARD The ratio between low period and high period counters Nlow Nhigh is 4 4 1 ASYMMETRIC The ratio between low period and high period counters Nlow Nhigh is 6 3 2 FAST The ratio between l...

Page 439: ...OP START Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CLEARPC 0 W1 Clear Pending Commands Set to clear pending commands 6 CLEARTX 0 W1 Clear TX Set to clear transmit buffer and shift register Will not abort ongoing transfer 5 ABORT 0 W1 Abort transmission Abort the current transmission makin...

Page 440: ...if the bus is currently being held by this I 2 C module 3 NACKED 0 R Nack Received Set if a NACK was received and STATE is ADDRACK or DATAACK 2 TRANSMITTER 0 R Transmitter Set when operating as a master transmitter or a slave transmitter When cleared the system may be operating as a master receiver a slave receiver or the current mode is not known 1 MASTER 0 R Master Set when operating as an I 2 C...

Page 441: ...nding and will be transmitted as soon as possible 2 PACK 0 R Pending ACK An acknowledge is pending and will be transmitted as soon as possible 1 PSTOP 0 R Pending STOP A stop condition is pending and will be transmitted as soon as possible 0 PSTART 0 R Pending START A start condition is pending and will be transmitted as soon as possible 16 5 5 I2Cn_CLKDIV Clock Division Register Offset Bit Positi...

Page 442: ...erved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 1 MASK 0x00 RW Slave Address Mask Specifies the significant bits of the slave address Setting the mask to 0x00 will match all addresses while setting it to 0x7F will only match the exact address specified by ADDR 0 Reserved To ensure compatibility with future devices always write bits to ...

Page 443: ...Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 TXDATA 0x00 W TX Data Use this register to write a byte to the transmit buffer 16 5 11 I2Cn_IF Interrupt Flag Register Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 444: ... 7 NACK 0 R Not Acknowledge Received Interrupt Flag Set when a NACK has been received 6 ACK 0 R Acknowledge Received Interrupt Flag Set when an ACK has been received 5 RXDATAV 0 R Receive Data Valid Interrupt Flag Set when data is available in the receive buffer Cleared automatically when the receive buffer is read 4 TXBL 1 R Transmit Buffer Level Interrupt Flag Set when the transmit buffer become...

Page 445: ... Set Not Acknowledge Received Interrupt Flag Write to 1 to set the NACK interrupt flag 6 ACK 0 W1 Set Acknowledge Received Interrupt Flag Write to 1 to set the ACK interrupt flag 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 TXC 0 W1 Set Transfer Completed Interrupt Flag Write to 1 to set the TXC interrupt flag 2 ADDR 0 W1 Set...

Page 446: ...errupt Flag Write to 1 to clear the NACK interrupt flag 6 ACK 0 W1 Clear Acknowledge Received Interrupt Flag Write to 1 to clear the ACK interrupt flag 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 TXC 0 W1 Clear Transfer Completed Interrupt Flag Write to 1 to clear the TXC interrupt flag 2 ADDR 0 W1 Clear Address Interrupt Fl...

Page 447: ...terrupt when not acknowledge is received 6 ACK 0 RW Acknowledge Received Interrupt Enable Enable interrupt on acknowledge received 5 RXDATAV 0 RW Receive Data Valid Interrupt Enable Enable interrupt on receive buffer full 4 TXBL 0 RW Transmit Buffer level Interrupt Enable Enable interrupt on transmit buffer level 3 TXC 0 RW Transfer Completed Interrupt Enable Enable interrupt on transfer completed...

Page 448: ...O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 6 LOC6 Location 6 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 SCLPEN 0 RW SCL Pin Enable When set the SCL pin of the I 2 C is enabled 0 SDAPEN 0 RW SDA Pin Enable When set the SDA pin of t...

Page 449: ...troduction The Universal Synchronous Asynchronous serial Receiver and Transmitter USART is a very flexible serial I O module It supports full duplex asynchronous UART communication as well as RS 485 SPI MicroWire and 3 wire It can also interface with ISO7816 SmartCards and IrDA devices 17 2 Features Asynchronous and synchronous SPI communication Full duplex and half duplex Separate TX RX enable Se...

Page 450: ...eripheral Bus Baud rate generator USn_CLK Pin ctrl USn_CS U S n_RX IrDA modulator IrDA demodulator RXBLOCK PRS inputs 17 3 1 Modes of Operation The USART operates in either asynchronous or synchronous mode In synchronous mode a separate clock signal is transmitted with the data This clock signal is generated by the bus master and both the master and slave sample and transmit data according to this...

Page 451: ... 0 Data in Data out Clock in Slave select 1 0 1 Data out Data in Clock out Auto slave select 1 1 0 Data out in Clock in Slave select 1 1 1 Data out in Clock out Auto slave select 17 3 2 Asynchronous Operation 17 3 2 1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking A frame ...

Page 452: ...be inverted by setting TXINV in USARTn_CTRL and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL These bits affect the entire frame not only the data bits An inverted frame has a low idle state a high start bit inverted data and parity bits and low stop bits 17 3 2 1 1 Parity bit Calculation and Handling When parity bits are enabled hardware automatically calcula...

Page 453: ...llow the USART clock to be controlled more accurately than what is possible with a standard integral divider The clock divider used in the USART is a 15 bit value with a 13 bit integral part and a 2 bit fractional part The fractional part is configured in the two LSBs of DIV in USART_CLKDIV The lowest achievable baud rate at 32 MHz is about 244 bauds sec Fractional clock division is implemented by...

Page 454: ...e to become available Transmission is enabled through the command register USARTn_CMD by setting TXEN and disabled by setting TXDIS in the same command register When the transmitter is disabled using TXDIS any ongoing transmission is aborted and any frame currently being transmitted is discarded When disabled the TX output goes to an idle state which by default is a high value Whether or not the t...

Page 455: ...mpty Both the TXBL status flag and the TXBL interrupt flag are cleared automatically when their condition becomes false The transmit buffer including the transmit shift register can be cleared by setting CLEARTX in USARTn_CMD This will prevent the USART from transmitting the data in the buffer and shift register and will make them available for new data Any frame currently being transmitted will n...

Page 456: ...fer the RXDATAV flag in USARTn_STATUS and the RXDATAV interrupt flag in USARTn_IF are set and when the buffer becomes full RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set The status flags RXDATAV and RXFULL are automatically cleared by hardware when their condition is no longer true This also goes for the RXDATAV interrupt flag but the RXFULL interrupt flag must be clear...

Page 457: ...buffer RXBLOCK must be cleared in the instant a frame is fully received by the receiver RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by setting RXBLOCKDIS also in USARTn_CMD There is one exception where data is loaded into the receive buffer even when RXBLOCK is set This is when an address frame is received when operating in multi processor mode See Section 17 3 2 8 p 463 for mor...

Page 458: ...7 5 p 458 Majority vote can be disabled by setting MVDIS in USARTn_CTRL If the value of the start bit is found to be high the reception of the frame is aborted filtering out false start bits possibly generated by noise on the input Figure 17 5 USART Sampling of Start and Data Bits 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 Idle Start bit Bit 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 ...

Page 459: ..._RXDOUBLEX or USARTn_RXDOUBLEXP registers If ERRSTX in USARTn_CTRL is set the transmitter is disabled on received parity and framing errors If ERRSRX in USARTn_CTRL is set the receiver is disabled on parity and framing errors 17 3 2 4 5 Framing Error and Break Detection A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0 This can be the result of n...

Page 460: ...DIS also in USARTn_CMD must be set to enable transmitter output again Whether or not the output is tristated at a given time can be read from TXTRI in USARTn_STATUS If TXTRI is set when transmitting data the data is shifted out of the shift register but is not put out on U S n_TX When operating a half duplex data bus it is common to have a bus master which first transmits a request to one of the b...

Page 461: ...also be used for automatic chip slave select when in synchronous mode e g SPI 17 3 2 6 3 Two Data links Some limited devices only support half duplex communication even though two data links are available In this case software is responsible for making sure data is not transmitted when incoming data is expected 17 3 2 7 Large Frames As each frame in the transmit and receive buffers holds a maximum...

Page 462: ...ripheral Bus 2 1 0 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 0 1 2 Figure 17 10 p 462 illustrates the order of the transmitted bits when an 11 bit frame is transmitted with MSBF set If MSBF is set and the frame is smaller than 10 bits only the contents of transmit buffer 0 will be transmitted When receiving a large frame BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the ...

Page 463: ...SARTn_STATUS Multi processor mode is enabled by setting MPM in USARTn_CTRL and the value of the 9th bit in address frames can be set in MPAB Note that the receiver must be enabled for address frames to be detected The receiver can be blocked however preventing data from being loaded into the receive buffer while looking for address frames Example 17 1 p 463 explains basic usage of the multi proces...

Page 464: ... supports the ISO 7816 I O line T0 mode With exception of the stop bits guard time the 7816 data frame is equal to the regular asynchronous frame In this mode the receiver pulls the line low for one baud half a baud into the guard time to indicate a parity error This NAK can for instance be used by the transmitter to re transmit the frame SmartCard mode is a half duplex asynchronous mode so the tr...

Page 465: ... a NACK ed frame The transmitter will retransmit the frame until it is ACK ed by the receiver This only works when the number of databits in a frame is configured to 8 Set SKIPPERRF in USARTn_CTRL to make the receiver discard frames with parity errors The PERR interrupt flag in USARTn_IF is set when a frame is discarded because of a parity error Figure 17 14 USART SmartCard Stop Bit Sampling 13 14...

Page 466: ...a 2 bit fractional part USART Synchronous Mode Bit Rate br fHFPERCLK 2 x 1 USARTn_CLKDIV 256 17 3 Given a desired baud rate brdesired the clock divider USARTn_CLKDIV can be calculated using Equation 17 4 p 466 USART Synchronous Mode Clock Division Factor USARTn_CLKDIV 256 x fHFPERCLK 2 x brdesired 1 17 4 When the USART operates in master mode the highest possible bit rate is half the peripheral cl...

Page 467: ...ister using the internal clock When there are no more frames in the transmit buffer and the transmit shift register is empty the clock stops and communication ends When the receiver is enabled it samples data using the internal clock when the transmitter transmits data Operation of the RX and TX buffers is as in asynchronous mode 17 3 3 3 1 Operation of USn_CS Pin When operating in master mode the...

Page 468: ...nderflow interrupt flag TXUF in USARTn_IF will be set if no data is available for transmission to the master If the slave needs to control its own chip select signal this can be achieved by clearing CSPEN in the ROUTE register The internal chip select signal can then be controlled through CSINV in the CTRL register The chip select signal will be CSINV inverted i e if CSINV is cleared the chip sele...

Page 469: ...s 17 3 3 6 2 Major Modes The USART supports a set of different I2S formats as shown in Table 17 9 p 469 but it is not limited to these modes MONO JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format MONO enables mono mode i e one data stream instead of two which is the default JUSTIFY aligns data within a word on the I2S bus either left or right which can be...

Page 470: ...s directly after the edge on the word select signal in contradiction to the regular I2S waveform where it comes one bit period after Figure 17 18 USART Left justified I2S waveform USn_CLK USn_CS word select USn_TX USn_RX MSB Left channel Right channel Right channel LSB MSB A right justified stream is shown in Figure 17 19 p 470 The left and right justified streams are equal when the data size is e...

Page 471: ... USARTn_I2SCTRL In both master and slave mode the USART always starts transmitting on the LEFT channel after being enabled In master mode the transmission will stop if TX becomes empty In that case TXC is set Continuing the transmission in this case will make the data stream continue where it left off To make the USART start on the LEFT channel after going empty disable and re enable TX 17 3 4 PRS...

Page 472: ... room for more data Transmit buffer has room for RIGHT I2S data Only used in I2S mode Even though there are two sources for write requests to the DMA only one should be used at a time since the requests from both sources are cleared even though only one of the requests are used In some cases it may be sensible to temporarily stop DMA access to the USART when an error such as a framing error has oc...

Page 473: ...ut signal is demodulated before it enters the actual USART module The modulator is only available on USART0 and implements the original Rev 1 0 physical layer and one high speed extension which supports speeds from 2 4 kbps to 1 152 Mbps The data from and to the USART is represented in a NRZ Non Return to Zero format where the signal value is at the same level through the entire bit period For IrD...

Page 474: ...ed an incoming pulse has to last for 4 consecutive clock cycles to be detected by the IrDA demodulator Note that by default the idle value of the USART data signal is high This means that the IrDA modulator generates negative pulses and the IrDA demodulator expects negative pulses To make the IrDA module use RZI signalling both TXINV and RXINV in USARTn_CTRL must be set The IrDA module can also mo...

Page 475: ...er 0x03C USARTn_TXDOUBLE W TX Buffer Double Data Register 0x040 USARTn_IF R Interrupt Flag Register 0x044 USARTn_IFS W1 Interrupt Flag Set Register 0x048 USARTn_IFC W1 Interrupt Flag Clear Register 0x04C USARTn_IEN RW Interrupt Enable Register 0x050 USARTn_IRCTRL RW IrDA Control Register 0x054 USARTn_ROUTE RW I O Routing Register 0x058 USARTn_INPUT RW USART Input Register 0x05C USARTn_I2SCTRL RW I...

Page 476: ...ng and parity errors have no effect on receiver 1 Framing and parity errors disable the receiver 22 ERRSDMA 0 RW Halt DMA On Error When set DMA requests will be cleared on framing and parity errors asynchronous mode only Value Description 0 Framing and parity errors have no effect on DMA requests from the USART 1 DMA requests from the USART are blocked while the PERR or FERR interrupt flags are se...

Page 477: ... register determines the action to be performed when slave select is configured as an input and driven low while in master mode Value Mode Description 0 NOACTION No action taken 1 GOTOSLAVEMODE Go to slave mode 10 MSBF 0 RW Most Significant Bit First Decides whether data is sent with the least significant bit first or the most significant bit first Value Description 0 Data is sent with the least s...

Page 478: ...llision check is enabled The receiver must be enabled for the check to be performed 1 LOOPBK 0 RW Loopback Enable Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication Value Description 0 The receiver is connected to and receives data from U S n_RX 1 The receiver is connected to and receives data from U S n_TX 0 SYNC 0 RW USART Synchronous...

Page 479: ...contains 7 data bits 5 EIGHT Each frame contains 8 data bits 6 NINE Each frame contains 9 data bits 7 TEN Each frame contains 10 data bits 8 ELEVEN Each frame contains 11 data bits 9 TWELVE Each frame contains 12 data bits 10 THIRTEEN Each frame contains 13 data bits 11 FOURTEEN Each frame contains 14 data bits 12 FIFTEEN Each frame contains 15 data bits 13 SIXTEEN Each frame contains 16 data bits...

Page 480: ...1 CLEARRX 0 W1 Clear RX Set to clear receive buffer and the RX shift register 10 CLEARTX 0 W1 Clear TX Set to clear transmit buffer and the TX shift register 9 TXTRIDIS 0 W1 Transmitter Tristate Disable Disables tristating of the transmitter output 8 TXTRIEN 0 W1 Transmitter Tristate Enable Tristates the transmitter output 7 RXBLOCKDIS 0 W1 Receiver Block Disable Set to clear RXBLOCK resulting in ...

Page 481: ...ect a single right data or left data Only used in I2S mode 8 RXFULL 0 R RX FIFO Full Set when the RXFIFO is full Cleared when the receive buffer is no longer full When this bit is set there is still room for one more frame in the receive shift register 7 RXDATAV 0 R RX Data Valid Set when data is available in the receive buffer Cleared when the receive buffer is empty 6 TXBL 1 R TX Buffer Level In...

Page 482: ...vices always write bits to 0 More information in Section 2 1 p 3 17 5 7 USARTn_RXDATAX RX Buffer Data Extended Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERR PERR RXDATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 M...

Page 483: ... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 0 0 0x000 Access R R R R R R Name FERR1 PERR1 RXDATA1 FERR0 PERR0 RXDATA0 Bit Name Reset Access Description 31 FERR1 0 R Data Framing Error 1 Set if data in buffer has a framing error Can be the result of a break condition 30 PERR1 0 R Data Parity Error 1 Set if data in buffer has a parity error asynchronous mode only 29 25 Reserved To ensu...

Page 484: ...7 5 11 USARTn_RXDATAXP RX Buffer Data Extended Peek Register Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 Access R R R Name FERRP PERRP RXDATAP Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 FERRP 0 R Data Fra...

Page 485: ...R RX Data 1 Peek Second frame read from FIFO 15 FERRP0 0 R Data Framing Error 0 Peek Set if data in buffer has a framing error Can be the result of a break condition 14 PERRP0 0 R Data Parity Error 0 Peek Set if data in buffer has a parity error asynchronous mode only 13 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 RXDATAP0 0...

Page 486: ...tiated at the first opportunity 17 5 14 USARTn_TXDATA TX Buffer Data Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 TXDATA 0x00 W TX Data T...

Page 487: ...ion Set to disable transmitter and release data bus directly after transmission 13 TXBREAK0 0 W Transmit Data As Break Set to send data as a break Recipient will see a framing error or a break condition depending on its configuration and the value of TXDATA 12 TXTRIAT0 0 W Set TXTRI After Transmission Set to tristate transmitter by setting TXTRI after transmission 11 UBRXAT0 0 W Unblock RX After T...

Page 488: ...0 R Parity Error Interrupt Flag Set when a frame with a parity error asynchronous mode only is received while RXBLOCK is cleared 7 TXUF 0 R TX Underflow Interrupt Flag Set when operating as a synchronous slave no data is available in the transmit buffer when the master starts transmission of a new frame 6 TXOF 0 R TX Overflow Interrupt Flag Set when a write is done to the transmit buffer while it ...

Page 489: ...ng Error Interrupt Flag Write to 1 to set the FERR interrupt flag 8 PERR 0 W1 Set Parity Error Interrupt Flag Write to 1 to set the PERR interrupt flag 7 TXUF 0 W1 Set TX Underflow Interrupt Flag Write to 1 to set the TXUF interrupt flag 6 TXOF 0 W1 Set TX Overflow Interrupt Flag Write to 1 to set the TXOF interrupt flag 5 RXUF 0 W1 Set RX Underflow Interrupt Flag Write to 1 to set the RXUF interr...

Page 490: ...rrupt flag 4 RXOF 0 W1 Clear RX Overflow Interrupt Flag Write to 1 to clear the RXOF interrupt flag 3 RXFULL 0 W1 Clear RX Buffer Full Interrupt Flag Write to 1 to clear the RXFULL interrupt flag 2 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 TXC 0 W1 Clear TX Complete Interrupt Flag Write to 1 to clear the TXC interrupt flag 1...

Page 491: ... TX Complete Interrupt Enable Enable interrupt on TX complete 17 5 21 USARTn_IRCTRL IrDA Control Register Offset Bit Position 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 0 0x0 0 Access RW RW RW RW RW Name IRPRSEN IRPRSSEL IRFILT IRPW IREN Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always wr...

Page 492: ... it 17 5 22 USARTn_ROUTE I O Routing Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 0 Access RW RW RW RW RW Name LOCATION CLKPEN CSPEN TXPEN RXPEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATI...

Page 493: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x0 Access RW RW Name RXPRS RXPRSSEL Bit Name Reset Access Description 31 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 RXPRS 0 RW PRS RX Enable When set the PRS channel selected as input to RX 3 0 RXPRSSEL 0x0 RW RX PRS Channel Select Select PRS channel as input to RX Value Mode Desc...

Page 494: ...ord 24 bit data 3 W32D16 32 bit word 16 bit data 4 W32D8 32 bit word 8 bit data 5 W16D16 16 bit word 16 bit data 6 W16D8 16 bit word 8 bit data 7 W8D8 8 bit word 8 bit data 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 DELAY 0 RW Delay on I2S data Set to add a one cycle delay between a transition on the word clock and the star...

Page 495: ...in EM1 18 1 Introduction The Universal Asynchronous serial Receiver and Transmitter UART is a very flexible serial I O module It supports full and half duplex asynchronous UART communication 18 2 Features Full duplex and half duplex Separate TX RX enable Separate receive transmit 2 level buffers with additional separate shift registers Programmable baud rate generated as an fractional division fro...

Page 496: ...OL and CPHA in USARTn_CTRL and MASTEREN in USARTn_STATUS are always 0 Transmission direction Always LSB first MSBF in USARTn_CTRL is always 0 Chip select Not available AUTOCS in USARTn_CTRL is always 0 SmartCard mode Not available SCMODE in USARTn_CTRL is always 0 Frame size Limited to 8 9 databits Other configurations of DATABITS in USARTn_FRAME are not possible IrDA Not available IREN in USARTn_...

Page 497: ...in low energy mode EM2 with most core functionality turned off the LEUART can wait for an incoming UART frame while having an extremely low energy consumption When a UART frame is completely received the CPU can quickly be woken up Alternatively multiple frames can be transferred via the Direct Memory Access DMA module into RAM memory before waking up the CPU Received data can optionally be blocke...

Page 498: ...automatically IrDA modulator pulse generator pulse extender Multi processor mode Loopback mode Half duplex communication Communication debugging PRS RX input 19 3 Functional Description An overview of the LEUART module is shown in Figure 19 1 p 498 Figure 19 1 LEUART Overview TX Buffer TX Shift Register Signal frame interrupt RX Buffer RX Shift Register LEUn_RX UART Control and status Peripheral B...

Page 499: ...op bits INV should only be changed while the receiver is disabled 19 3 1 1 Parity Bit Calculation and Handling Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming frames The possible parity modes are defined in Table 19 1 p 499 When even parity is chosen a parity bit is inserted to make the number of high bits data parity even If odd parity is cho...

Page 500: ...w data a frame from the transmit buffer is loaded into the shift register and if the transmitter is enabled transmission begins When the frame has been transmitted a new frame is loaded into the shift register if available and transmission continues If the transmit buffer is empty the transmitter goes to an idle state waiting for a new frame to become available Transmission is enabled through the ...

Page 501: ...trol d0 d2 d4 d6 d8 d7 d5 d3 d1 control TXDATA TXDATAX BIT8DV Transmit buffer 0 19 3 4 2 Frame Transmission Control The transmission control bits which can be written using LEUARTn_TXDATAX affect the transmission of the written frame The following options are available Generate break By setting WBREAK the output will be held low during the first stop bit period to generate a framing error A receiv...

Page 502: ...indicate the buffer overflow The receiver can be disabled by setting the command bit RXDIS in LEUARTn_CMD Any frame currently being received when the receiver is disabled is discarded Whether or not the receiver is enabled at a given time can be read out from RXENS in LEUARTn_STATUS 19 3 5 1 Receive Buffer Operation When data becomes available in the receive buffer the RXDATAV flag in LEUARTn_STAT...

Page 503: ...K is set The first is when an address frame is received when in operating in multi processor mode as shown in Section 19 3 5 8 p 505 The other case is when receiving a start frame when SFUBRX in LEUARTn_CTRL is set see Section 19 3 5 6 p 504 Frames received containing framing or parity errors will not result in the FERR and PERR interrupt flags in LEUARTn_IF being set while RXBLOCK is set Hardware...

Page 504: ... result of noise and baud rate errors but can also be the result of a break generated by the transmitter on purpose When a framing error is detected the framing error bit FERR in the received frame is set The interrupt flag FERR in LEUARTn_IF is also set Frames with framing errors are loaded into the receive buffer like regular frames FERR can be accessed by reading the frame from the receive buff...

Page 505: ...n multiple processors and maintain compatibility with the USART the LEUART supports a multi processor mode In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address When multi processor mode is enabled an incoming 9 bit frame with the 9th bit equal to the value of MPAB in LEUARTn_CTRL is identified as an address frame When an ...

Page 506: ...set the LEUART automatically tristates LEUn_TX whenever the transmitter is inactive It is then the responsibility of the software protocol to make sure the transmitter is not transmitting data whenever incoming data is expected The transmitter can also be tristated from software by configuring the GPIO pin as an input and disabling the LEUART output on LEUn_TX Note Another way to tristate the tran...

Page 507: ...ite to the transmit buffer using the registers LEUARTn_TXDATA and LEUARTn_TXDATAX and it can read from receive buffer using the registers LEUARTn_RXDATA and LEUARTn_RXDATAX This enables single byte transfers and 9 bit data control status bits transfers both to and from the LEUART The DMA will start up the HFRCO and run from this when it is waken by the LEUART in EM2 The HFRCO is disabled once the ...

Page 508: ...red using PULSEW in LEUARTn_PULSECTRL The generated pulse width is PULSEW 1 cycles of the 32 768 kHz clock which makes pulse width from 31 25µs to 500µs possible Since the incoming signal is only sampled on positive clock edges the width of the incoming pulses must be at least two 32 768 kHz clock periods wide for reliable detection by the LEUART receiver They must also be shorter than half a UART...

Page 509: ...ister 0x03C LEUARTn_PULSECTRL RW Pulse Control Register 0x040 LEUARTn_FREEZE RW Freeze Register 0x044 LEUARTn_SYNCBUSY R Synchronization Busy Register 0x054 LEUARTn_ROUTE RW I O Routing Register 0x0AC LEUARTn_INPUT RW LEUART Input Register 19 5 Register Description 19 5 1 LEUARTn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bi...

Page 510: ... the frame as a multi processor address frame 9 MPM 0 RW Multi Processor Mode Set to enable multi processor mode Value Description 0 The 9th bit of incoming frames have no special function 1 An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 8 SFUBRX 0 RW Start Frame UnBlock RX Clears RX...

Page 511: ... held high when the transmitter is inactive INV inverts the inactive state 1 LEUn_TX is tristated when the transmitter is inactive 19 5 2 LEUARTn_CMD Command Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W...

Page 512: ...receive buffer is empty 4 TXBL 1 R TX Buffer Level Indicates the level of the transmit buffer Set when the transmit buffer is empty and cleared when it is full 3 TXC 0 R TX Complete Set when a transmission has completed and no more data is available in the transmit buffer Cleared when a new transmission starts 2 RXBLOCK 0 R Block Incoming Data When set the receiver discards incoming frames An inco...

Page 513: ...cess RW Name STARTFRAME Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 STARTFRAME 0x000 RW Start Frame When a frame matching STARTFRAME is detected by the receiver STARTF interrupt flag is set and if SFUBRX is set RXBLOCK is cleared The start frame is be loaded into the RX buffer 19 5 6 LEUA...

Page 514: ...14 PERR 0 R Receive Data Parity Error Set if data in buffer has a parity error 13 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 RXDATA 0x000 R RX Data Use this register to access data read from the LEUART Buffer is cleared on read access 19 5 8 LEUARTn_RXDATA Receive Buffer Data Register Offset Bit Position 0x01C 31 30 29 28 2...

Page 515: ...ture devices always write bits to 0 More information in Section 2 1 p 3 8 0 RXDATAP 0x000 R RX Data Peek Use this register to access data read from the LEUART 19 5 10 LEUARTn_TXDATAX Transmit Buffer Data Extended Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 516: ...ata Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 ...

Page 517: ... the transmit buffer for a new frame 0 TXC 0 R TX Complete Interrupt Flag Set after a transmission when both the TX buffer and shift register are empty 19 5 13 LEUARTn_IFS Interrupt Flag Set Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 Name SIGF STARTF MPAF FERR PER...

Page 518: ...More information in Section 2 1 p 3 10 SIGF 0 W1 Clear Signal Frame Interrupt Flag Write to 1 to clear the SIGF interrupt flag 9 STARTF 0 W1 Clear Start Frame Interrupt Flag Write to 1 to clear the STARTF interrupt flag 8 MPAF 0 W1 Clear Multi Processor Address Frame Interrupt Flag Write to 1 to clear the MPAF interrupt flag 7 FERR 0 W1 Clear Framing Error Interrupt Flag Write to 1 to clear the FE...

Page 519: ...able Enable interrupt on multi processor address frame 7 FERR 0 RW Framing Error Interrupt Enable Enable interrupt on framing error 6 PERR 0 RW Parity Error Interrupt Enable Enable interrupt on parity error 5 TXOF 0 RW TX Overflow Interrupt Enable Enable interrupt on TX overflow 4 RXUF 0 RW RX Underflow Interrupt Enable Enable interrupt on RX underflow 3 RXOF 0 RW RX Overflow Interrupt Enable Enab...

Page 520: ... 5 4 3 2 1 0 Reset 0 Access RW Name REGFREEZE Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 REGFREEZE 0 RW Register Update Freeze When set the update of the LEUART is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Ea...

Page 521: ...ed 19 5 19 LEUARTn_ROUTE I O Routing Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 Access RW RW RW Name LOCATION TXPEN RXPEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATION 0x0 RW I O Location ...

Page 522: ...write bits to 0 More information in Section 2 1 p 3 4 RXPRS 0 RW PRS RX Enable When set the PRS channel selected as input to RX 3 0 RXPRSSEL 0x0 RW RX PRS Channel Select Select PRS channel as input to RX Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS ...

Page 523: ...rator The Timer can also count events and control other peripherals through the PRS which offloads the CPU and reduce energy consumption 20 1 Introduction The 16 bit general purpose Timer has 3 compare capture channels for input capture and compare Pulse Width Modulation PWM output TIMER0 also includes a Dead Time Insertion module suitable for motor control applications 20 2 Features 16 bit auto r...

Page 524: ...tem Debug mode Configurable to either run or stop when processor is stopped break Interrupts PRS output and or DMA request Underflow Overflow Compare Capture event Dead Time Insertion Unit TIMER0 only Complementary PWM outputs with programmable dead time Dead time is specified independently for rising and falling edge 10 bit prescaler 6 bit time value Outputs have configurable polarity Outputs can...

Page 525: ...s counting up again 4 Quadrature Decoder Two input channels where one determines the count direction while the other pin triggers a clock event In addition to the TIMER modes listed above the TIMER also supports a 2x Count Mode In this mode the counter increments decrements by 2 The 2x Count Mode intended use is to generate 2x PWM frequency when the Compare Capture channel is put in PWM mode The 2...

Page 526: ...he counter value can be read or written by software through the CNT field in TIMERn_CNT In Up Down Count mode the count direction will be set to up if the CNT value is written by software Figure 20 2 TIMER Hardware Timer Counter Control Counter Controlled by TIMERn_CTRL Compare Capture channel 0 Controlled by TIMERn_CC0_CTRL TIMn_CC0 PRS channels PRSSEL INSEL Filter FILT ICEDGE Input Capture 0 Cou...

Page 527: ...lower numbered neighbouring timers to form a 32 bit or 48 bit timer Note that all timers must be set to same count direction and less significant timer s can only be set to count up or down Figure 20 4 TIMER Connections TIMER0 TIMER1 TIMER2 Overflow Overflow Underflow Underflow 20 3 1 4 One Shot Mode By default the counter counts continuously until it is stopped If the OSMEN bit is set in the TIME...

Page 528: ...e phase relation between the two inputs The Quadrature Decoder Mode supports two channels but if a third channel Z terminal is available this can be connected to an external interrupt and trigger a counter reset from the interrupt service routine By connecting a periodic signal from another timer as input capture on Compare Capture Channel 2 it is also possible to calculate speed and acceleration ...

Page 529: ...6 7 8 3 4 5 6 7 2 8 20 3 1 6 2 X4 Decoding Mode In X4 Decoding mode the counter increments or decrements on every edge of Channel A and Channel B see Figure 20 9 p 529 and Table 20 2 p 529 Table 20 2 TIMER Counter Response in X4 Decoding Mode Channel A Channel B Opposite Channel Rising Falling Rising Falling Channel A 0 Decrement Increment Channel A 1 Increment Decrement Channel B 0 Increment Decr...

Page 530: ... x stands for the channel number Since the Compare Capture channels serve three functions input capture compare PWM the behavior of the Compare Capture registers TIMERn_CCx_CCV and buffer registers TIMERn_CCx_CCVB change depending on the mode the channel is set in 20 3 2 2 1 Input Capture mode When running in Input Capture mode TIMERn_CCx_CCV and TIMERn_CCx_CCVB form a FIFO buffer and new capture ...

Page 531: ...STATUS indicates whether the TIMERn_CCx_CCVB register contains data that have not yet been written to the TIMERn_CCx_CCV register Note that when writing 0 to TIMERn_CCx_CCVB the CCV value is updated when the timer counts from 0 to 1 Thus the compare match for the next period will not happen until the timer reaches 0 again on the way down Figure 20 12 TIMER Output Compare PWM Buffer Functionality C...

Page 532: ...channel should be set to capture on a falling edge of the input signal To start the measuring period on either a falling edge or measure the low pulse width of a signal opposite polarities should be chosen Figure 20 14 TIMER Period and or Pulse width Capture 0 Input CNT Clear Start Input Capture frequency capture Input Capture pulse width capture 20 3 2 4 Compare Each Compare Capture channel conta...

Page 533: ...ch and the result is found in the CCPOL bits in TIMERn_STATUS It is also possible to configure the CCPOL to always track the inputs by setting ATI in TIMERn_CTRL The COIST bit in TIMERn_CCx_CTRL is the initial state of the compare PWM output The COIST bit can also be used as an initial value to the compare outputs on a reload start when RSSCOIST is set in TIMERn_CTRL Also the resulting output can ...

Page 534: ...Single slope PWM If the counter is set to up count and the Compare Capture channel is put in PWM mode single slope PWM output will be generated see Figure 20 18 p 534 In up count mode the PWM period is TOP 1 cycles and the PWM output will be high for a number of cycles equal to TIMERn_CCx_CCV This means that a constant high output is achieved by setting TIMER_CCx to TOP 1 or higher The PWM resolut...

Page 535: ... the 2x mode is to generate 2x PWM frequency when the Compare Capture channel is put in PWM mode Since the PWM output is updated on both edges of the clock frequency prescaling will result in incorrect result in this mode The PWM resolution in bits is then given by Equation 20 6 p 535 TIMER 2x PWM Resolution Equation RPWM2xmode log TOP 2 1 log 2 20 6 The PWM frequency is given by Equation 20 7 p 5...

Page 536: ... Timer is set in 2x mode the TIMER will count up down by two This will in effect make any odd Top value be rounded down to the closest even number Similarly any odd CC value will generate a match on the closest lower even value as shown in Figure 20 21 p 536 Figure 20 21 TIMER CC out in 2x mode 2 4 2 0 2 0 Clock CC Out 4 2 4 2 0 2 0 4 Top 5 CC 1 Top 5 CC 2 The mode is enabled by setting the X2CNT ...

Page 537: ...Cx Complementary output TIM0_CDTIx Fault sources When used for motor control the PWM outputs TIM0_CC0 TIM0_CC1 and TIM0_CC2 are often connected to the high side transistors of a triple half bridge setup UH VH and WH and the complementary outputs connected to the respective low side transistors UL VL WL shown in Figure 20 23 p 537 Transistors used in such a bridge often do not open close instantane...

Page 538: ...nnels of the DTI unit A single prescaler value is provided for the DTI unit meaning that both the rising and falling edge dead times share prescaler value The prescaler divides the HFPERCLKTIMERn by a configurable factor between 1 and 1024 which is set in the DTPRESC field in TIMER0_DTTIME The rising and falling edge dead times are configured in DTRISET and DTFALLT in TIMER0_DTTIME to any number b...

Page 539: ...y be used as input to the DTI module instead of the PWM output from the timer Setting DTPRSEN in TIMER0_DTCTRL will override the source of the first DTI channel driving TIM0_CC0 and TIM0_CDTI0 with the value on the PRS channel The rest of the DTI channels will continue to be driven by the PWM output from the timer The PRS channel to use is chosen by configuring DTPRSSEL in TIMER0_DTCTRL Note that ...

Page 540: ...rce s can be read out of TIMER0_DTFS TIMER0_DTFS is organized in the same way as DTFSEN with one bit for each source 20 3 3 3 2 Exiting Fault State When a fault is triggered by the PRS system software intervention is required to re enable the outputs of the DTI unit This is done by manually clearing TIMER0_DTFS If the fault cause determined by TIMER0_DTFS is the debugger alone the outputs can opti...

Page 541: ... outputs Each of the events will also set a DMA request when they occur The different DMA requests are cleared when certain acknowledge conditions are met see Table 20 3 p 541 If DMACLRACT is set in TIMERn_CTRL the DMA request is cleared when the triggered DMA channel is active without having to access any timer registers Table 20 3 TIMER Events Event Acknowledge Underflow Overflow Read or write t...

Page 542: ...l Control Register 0x034 TIMERn_CC0_CCV RWH CC Channel Value Register 0x038 TIMERn_CC0_CCVP R CC Channel Value Peek Register 0x03C TIMERn_CC0_CCVB RWH CC Channel Buffer Register 0x040 TIMERn_CC1_CTRL RW CC Channel Control Register 0x044 TIMERn_CC1_CCV RWH CC Channel Value Register 0x048 TIMERn_CC1_CCVP R CC Channel Value Peek Register 0x04C TIMERn_CC1_CCVB RWH CC Channel Buffer Register 0x050 TIME...

Page 543: ... divided by 4 3 DIV8 The HFPERCLK is divided by 8 4 DIV16 The HFPERCLK is divided by 16 5 DIV32 The HFPERCLK is divided by 32 6 DIV64 The HFPERCLK is divided by 64 7 DIV128 The HFPERCLK is divided by 128 8 DIV256 The HFPERCLK is divided by 256 9 DIV512 The HFPERCLK is divided by 512 10 DIV1024 The HFPERCLK is divided by 1024 23 18 Reserved To ensure compatibility with future devices always write b...

Page 544: ... Value Description 0 Timer is frozen in debug mode 1 Timer is running in debug mode 5 QDM 0 RW Quadrature Decoder Mode Selection This bit sets the mode for the quadrature decoder Value Mode Description 0 X2 X2 mode selected 1 X4 X4 mode selected 4 OSMEN 0 RW One shot Mode Enable Enable disable one shot mode 3 SYNC 0 RW Timer Start Stop Reload Synchronization When this bit is set the Timer is start...

Page 545: ...on 2 1 p 3 26 CCPOL2 0 R CC2 Polarity In Input Capture mode this bit indicates the polarity of the edge that triggered capture in TIMERn_CC2_CCV In Compare PWM mode this bit indicates the polarity of the selected input to CC channel 2 These bits are cleared when CCMODE is written to 0b00 Off Value Mode Description 0 LOWRISE CC2 polarity low level rising edge 1 HIGHFALL CC2 polarity high level fall...

Page 546: ...MERn_CC2_CCVB registers contain data which have not been written to TIMERn_CC2_CCV These bits are only used in output compare pwm mode and are cleared when CCMODE is written to 0b00 Off Value Description 0 TIMERn_CC2_CCVB does not contain valid data 1 TIMERn_CC2_CCVB contains valid data which will be written to TIMERn_CC2_CCV on the next update event 9 CCVBV1 0 R CC1 CCVB Valid This field indicate...

Page 547: ...sable Compare Capture ch 1 input capture buffer overflow interrupt 8 ICBOF0 0 RW CC Channel 0 Input Capture Buffer Overflow Interrupt Enable Enable disable Compare Capture ch 0 input capture buffer overflow interrupt 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 CC2 0 RW CC Channel 2 Interrupt Enable Enable disable Compare Captu...

Page 548: ...are Capture channel 0 3 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 UF 0 R Underflow Interrupt Flag This bit indicates that there has been an underflow 0 OF 0 R Overflow Interrupt Flag This bit indicates that there has been an overflow 20 5 6 TIMERn_IFS Interrupt Flag Set Register Offset Bit Position 0x014 31 30 29 28 27 26 25...

Page 549: ...ut Capture Buffer Overflow Interrupt Flag Clear Writing a 1 to this bit will clear Compare Capture channel 2 input capture buffer overflow interrupt flag 9 ICBOF1 0 W1 CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear Writing a 1 to this bit will clear Compare Capture channel 1 input capture buffer overflow interrupt flag 8 ICBOF0 0 W1 CC Channel 0 Input Capture Buffer Overflow Inter...

Page 550: ...unter Top Value These bits hold the TOP value for the counter 20 5 9 TIMERn_TOPB Counter Top Value Buffer Register Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name TOPB Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sect...

Page 551: ...ion 1 2 LOC2 Location 2 3 LOC3 Location 3 4 LOC4 Location 4 5 LOC5 Location 5 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 CDTI2PEN 0 RW CC Channel 2 Complementary Dead Time Insertion Pin Enable Enable disable CC channel 2 complementary dead time insertion output connection to pin 9 CDTI1PEN 0 RW CC Channel 1 Complementary...

Page 552: ...equest set on falling edge only if ICEDGE BOTH 25 24 ICEDGE 0x0 RW Input Capture Edge Select These bits control which edges the edge detector triggers on The output is used for input capture and external clock input Value Mode Description 0 RISING Rising edges detected 1 FALLING Falling edges detected 2 BOTH Both edges detected 3 NONE No edge detection signal is left as it is 23 22 Reserved To ens...

Page 553: ...ction on compare match Value Mode Description 0 NONE No action on compare match 1 TOGGLE Toggle output on compare match 2 CLEAR Clear output on compare match 3 SET Set output on compare match 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 COIST 0 RW Compare Output Initial State This bit is only used in Output Compare and PWM mo...

Page 554: ...ntents of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle In compare mode this fields holds the compare value 20 5 14 TIMERn_CCx_CCVP CC Channel Value Peek Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access R Name CCVP Bit Name Reset Access Description 31 16 Reserved To ensure...

Page 555: ... Section 2 1 p 3 24 DTPRSEN 0 RW DTI PRS Source Enable Enable disable PRS as DTI input 23 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 4 DTPRSSEL 0x0 RW DTI PRS Source Channel Select Select which PRS channel to listen to Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 P...

Page 556: ...r the rising edge Value Description DTRISET Rise time of DTRISET 1 prescaled HFPERCLK cycles 7 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 0 DTPRESC 0x0 RW DTI Prescaler Setting Select prescaler for DTI Value Mode Description 0 DIV1 The HFPERCLK is undivided 1 DIV2 The HFPERCLK is divided by 2 2 DIV4 The HFPERCLK is divided by...

Page 557: ...eserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 DTPRS1FSEL 0x0 RW DTI PRS Fault Source 1 Select Select PRS channel for fault source 1 Value Mode Description 0 PRSCH0 PRS Channel 0 selected as fault source 1 1 PRSCH1 PRS Channel 1 selected as fault source 1 2 PRSCH2 PRS Channel 2 selected as fault source 1 3 PRSCH3 PRS Channel 3 se...

Page 558: ...nables disables output generation for the CC2 output from the DTI 1 DTOGCC1EN 0 RW DTI CC1 Output Generation Enable This bit enables disables output generation for the CC1 output from the DTI 0 DTOGCC0EN 0 RW DTI CC0 Output Generation Enable This bit enables disables output generation for the CC0 output from the DTI 20 5 20 TIMERn_DTFAULT DTI Fault Register Offset Bit Position 0x080 31 30 29 28 27...

Page 559: ...ckup fault 2 DTDBGFC 0 W1 DTI Debugger Fault Clear Write 1 to this bit to clear debugger fault 1 DTPRS1FC 0 W1 DTI PRS1 Fault Clear Write 1 to this bit to clear PRS 1 fault 0 DTPRS0FC 0 W1 DTI PRS0 Fault Clear Write 1 to this bit to clear PRS 0 fault 20 5 22 TIMERn_DTLOCK DTI Configuration Lock Register Offset Bit Position 0x088 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 560: ...ndly microcontrollers 2016 04 28 Giant Gecko Family d0053_Rev1 20 560 www silabs com Bit Name Reset Access Description Mode Value Description Write Operation LOCK 0 Lock TIMER DTI registers UNLOCK 0xCE80 Unlock TIMER DTI registers ...

Page 561: ...r and is clocked either by a 32 768 Hz crystal oscillator a 32 768 Hz RC oscillator or a 1 kHz RC oscillator In addition to energy modes EM0 and EM1 the RTC is also available in EM2 This makes it ideal for keeping track of time since the RTC is enabled in EM2 where most of the device is powered down Using the 1 kHz ULFRCO as input clock the RTC can be used for timekeeping all the way down to EM3 T...

Page 562: ...enabled and will on an overflow simply wrap around and continue counting The RTC is cleared when it is disabled The timer value is both readable and writable and the RTC always starts counting from 0 when enabled The value of the counter can be read or modified using the RTC_CNT register 21 3 1 1 Clock Source The RTC clock source and its prescaler value are defined in the Register Description sect...

Page 563: ...ue for the RTC and the timer is cleared on a compare match with compare channel 0 If using the COMP0TOP setting make sure to set this bit prior to or at the same time the EN bit is set Setting COMP0TOP after the EN bit is set may cause unintended operation i e if CNT COMP0 21 3 2 1 LETIMER Triggers A compare event on either of the compare channels can start the LETIMER See the LETIMER documentatio...

Page 564: ...ULFRCO as clock source This is done by clearing CMU_LFCLKSEL_LFA and setting CMU_LFCLKSEL_LFAE to 1 This will make the RTC use the internal 1 kHz ultra low frequency RC oscillator ULFRCO consuming very little energy Please note that the ULFRCO is not accurate over temperature and voltage and it should be verified that the ULFRCO fulfills the timekeeping needs of the application before using this i...

Page 565: ...on about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access RW RW RW Name COMP0TOP DEBUGRUN EN Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP0TOP 0 RW Compare...

Page 566: ...pare Value Register 0 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000000 Access RW Name COMP0 Bit Name Reset Access Description 31 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sectio...

Page 567: ...able as a PRS signal 21 5 5 RTC_IF Interrupt Flag Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name COMP1 COMP0 OF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP1 0 R Compare Match 1 Inter...

Page 568: ... Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP1 0 W1 Clear Compare match 1 Interrupt Flag Write to 1 to clear the COMP1 interrupt flag 1 COMP0 0 W1 Clear Compare match 0 Interrupt Flag Write to 1 to clear the COMP0 interrupt flag 0 OF 0 W1 Clear Overflow Interrupt Flag Write to 1 to clear the OF interrupt fla...

Page 569: ...multaneously Value Mode Description 0 UPDATE Each write access to an RTC register is updated into the Low Frequency domain as soon as possible 1 FREEZE The RTC is not updated with the new written value until the freeze bit is cleared 21 5 10 RTC_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res...

Page 570: ... Introduction The Backup Real Time Counter BURTC contains a 32 bit counter and is clocked either by a 32 768 kHz crystal oscillator a 32 768 kHz RC oscillator a 2kHz RC oscillator or a 1kHz RC oscillator A variety of prescaler settings are also available for the 32 768 kHz oscillators The Backup RTC is available in all energy modes making it ideal for time keeping with minimal energy consumption T...

Page 571: ...in the control register A system reset will not clear the counter The counter value can be read through the CNT register 22 3 2 Clock source The Backup RTC is clocked by LFXO LFRCO or ULFRCO depending on the configuration of CLKSEL in BURTC_CTRL The PRESC bit field in BURTC_CTRL controls the clock prescaling factor Prescaler is only available for LFXO and LFRCO When using the ULFRCO as clock sourc...

Page 572: ...er mode a configurable number of the LSBs of COMP0 are ignored for compare match evaluation The number of bits ignored is configured in the LPCOMP bit field in the BURTC_CTRL register Equation 22 2 p 572 is used to calculate compare match resolution in low power mode In low power mode the Backup RTC will decrease its frequency by a factor of 2 LPCOMP and start incrementing with 2 LPCOMP instead of...

Page 573: ... is enabled by setting BUMODETSEN in BURTC_CTRL When a timestamp is stored the BUMODETS bit in BUCTRL_STATUS is set To prevent uncontrolled time stamping when entering and exiting backup mode this status bit has to be cleared before a new timestamp can be stored by writing a 1 to CLRSTATUS in BURTC_CMD Note that upon clearing this bit the data in BURTC_TIMESTAMP is no longer valid 22 3 10 LFXO fai...

Page 574: ... the world s most energy friendly microcontrollers 2016 04 28 Giant Gecko Family d0053_Rev1 20 574 www silabs com ...

Page 575: ... Flag Clear Register 0x034 BURTC_IEN RW Interrupt Enable Register 0x038 BURTC_FREEZE RW Freeze Register 0x03C BURTC_SYNCBUSY R Synchronization Busy Register 0x100 RET0_REG RW Retention Register RETx_REG RW Retention Register 0x2FC RET127_REG RW Retention Register 22 5 Register Description 22 5 1 BURTC_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1...

Page 576: ...IGN3LSB The three LSBs of the counter are ignored for compare match evaluation 4 IGN4LSB The four LSBs of the counter are ignored for compare match evaluation 5 IGN5LSB The five LSBs of the counter are ignored for compare match evaluation 6 IGN6LSB The six LSBs of the counter are ignored for compare match evaluation 7 IGN7LSB The seven LSBs of the counter are ignored for compare match evaluation 4...

Page 577: ... LPMODE 0x0 RW Low power mode configuration Value Mode Description 0 DISABLE Low power mode is disabled 1 ENABLE Low power mode always enabled 2 BUEN Low power mode enabled in backup mode 22 5 3 BURTC_CNT Counter Value Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name CNT Bit Name Reset Access Des...

Page 578: ... access to the BURTC compare value 22 5 5 BURTC_TIMESTAMP Backup mode timestamp Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name TIMESTAMP Bit Name Reset Access Description 31 0 TIMESTAMP 0x00000000 R Backup mode timestamp Contains the timestamp stored upon backup mode entry 22 5 6 BURTC_LFXOFDET LFXO Off...

Page 579: ...ter Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name RAMWERR BUMODETS LPMODEACT Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 RAMWERR 0 R RAM write error Set if backup mode is entered during a write t...

Page 580: ...fset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 LOCKKEY 0x0000 RW Configuration Lock Key Write any other value than the unlock code to lock BURTC...

Page 581: ...P0 0 R Compare match Interrupt Flag Set on BURTC compare match 0 OF 0 R Overflow Interrupt Flag Set on BURTC overflow 22 5 12 BURTC_IFS Interrupt Flag Set Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access W1 W1 W1 Name LFXOFAIL COMP0 OF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility w...

Page 582: ...rrupt flag 1 COMP0 0 W1 Clear compare match Interrupt Flag Write to 1 to clear the COMP0 interrupt flag 0 OF 0 W1 Clear Overflow Interrupt Flag Write to 1 to clear the OF interrupt flag 22 5 14 BURTC_IEN Interrupt Enable Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access RW RW RW Name LFXOFAIL COMP0 OF Bit Nam...

Page 583: ...ister is updated into the Low Frequency domain as soon as possible 1 FREEZE The BURTC is not updated with the new written value until the freeze bit is cleared 22 5 16 BURTC_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access R R Name COMP0 LPMODE Bit Name Reset Access Description 31...

Page 584: ...he world s most energy friendly microcontrollers 2016 04 28 Giant Gecko Family d0053_Rev1 20 584 www silabs com Bit Name Reset Access Description 31 0 REG 0xXXXXXXXX RW General Purpose Retention Register ...

Page 585: ...EM2 and EM3 23 1 Introduction The unique LETIMER TM the Low Energy Timer is a 16 bit timer that is available in energy mode EM2 and EM3 in addition to EM1 and EM0 Because of this it can be used for timing and output generation when most of the device is powered down allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum The LETIMER can be use...

Page 586: ... REP0 Repeat REP1 Repeat Buffer 1 LETIMER Control and Status Reload Update Update Stop 0 LFACLKLETIMERn Start RTC event SW pin ctrl LETn_O0 Pulse Control Underflow UF interrupt flag REP0 Zero REP0 interrupt flag Buffer Written Repeat load logic pin ctrl LETn_O1 Pulse Control Top load logic 1 REP1 Zero REP1 interrupt flag COMP1 Match COMP1 interrupt flag COMP0 Match COMP0 interrupt flag PRS CH1 PRS...

Page 587: ...an for instance be used in conjunction with the buffered repeat mode to generate continually changing output waveforms Write operations to LETIMERn_COMP0 have priority over buffer loads 23 3 3 2 Repeat Modes By default the timer wraps around to the top value or 0xFFFF on each underflow and continues counting The repeat counters can be used to get more control of the operation of the timer includin...

Page 588: ...t to 0 and an underflow event will not be generated when LETIMERn_CNT wraps around to the top value or 0xFFFF Since no underflow event is generated no output action is performed LETIMERn_REP0 LETIMERn_REP1 LETIMERn_COMP0 and LETIMERn_COMP1 are also left untouched 23 3 3 2 2 One shot Mode The one shot repeat mode is the most basic repeat mode In this mode the repeat register LETIMERn_REP0 is decrem...

Page 589: ... as long as LETIMERn_REP1 is updated with a nonzero value before LETIMERn_REP0 is finished counting down If the timer is started when both LETIMERn_CNT and LETIMERn_REP0 are zero but LETIMERn_REP1 is non zero LETIMERn_REP1 is loaded into LETIMERn_REP0 and the counter counts the loaded number of times The state machine for the one shot repeat mode is shown in Figure 23 3 p 589 Used in conjunction w...

Page 590: ...much like the one shot repeat mode The difference is that where the one shot mode counts as long as LETIMERn_REP0 is larger than 0 the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0 As an example say LETIMERn_REP0 is 3 and LETIMERn_REP1 is 10 when the timer is started If no further interaction is done with the timer LETIMERn_REP0 will now be decremented 3 time...

Page 591: ... fLFACKL_LETIMERn 32 768 2 LETIMERn 23 1 where the exponent LETIMERn is a 4 bit value in the CMU_LFAPRESC0 register To use this module the LE interface clock must be enabled in CMU_HFCORECLKEN0 in addition to the module clock 23 3 3 4 RTC Trigger The LETIMER can be configured to start on compare match events from the Real Time Counter RTC If RTCC0TEN in LETIMERn_CTRL is set the LETIMER will start ...

Page 592: ...UFOA0 and UFOA1 in LETIMERn_CTRL UFOA0 defines the action on output 0 and is connected to LETIMERn_REP0 while UFOA1 defines the action on output 1 and is connected to LETIMERn_REP1 The possible actions are defined in Table 23 2 p 592 Table 23 2 LETIMER Underflow Output Actions UF0A0 UF0A1 Mode Description 00 Idle The output is held at its idle value 01 Toggle The output is toggled on LETIMERn_CNT ...

Page 593: ...n LETn_O0 UFOA0 01 LETn_O0 UFOA0 10 LETn_O0 UFOA0 00 3 0 UFIF 3 0 For the example in Figure 23 7 p 593 the One shot repeat mode has been selected and LETIMERn_REP0 has been written to 3 The resulting behavior is pretty similar to that shown in Figure 6 but in this case the timer stops after counting to zero LETIMERn_REP0 times By using LETIMERn_REP0 the user has full control of the number of pulse...

Page 594: ... 3 START 23 3 5 PRS Output The LETIMER outputs can be routed out onto the PRS system LETn_O0 can be routed to PRS channel 0 and LETn_1O can be routed to PRS channel 1 Enabling the RRS connection can be done by setting SOURCESEL to LETIMERx and SIGSEL to LETIMERxCHn in PRS_CHx_CTRL The PRS register description can be found in Section 13 5 p 169 23 3 6 Examples This section presents a couple of usag...

Page 595: ...e can update LETIMERn_COMP1 and LETIMERn_REP1 to change the number of pulses and pulse period in each train but if changes are not required software does not have to update the registers between each pulse train For the example in Figure 23 9 p 595 the initial values cause the LETIMER to generate two pulses with 3 cycle periods or a single pulse 3 cycles wide every time the LETIMER is started Afte...

Page 596: ...P0IF UFIF UFIF UFIF UFIF Int flags set Stop final values Write COMP1 2 REP1 2 UFIF UFIF UFIF REP0IF 4 4 4 4 4u 4u 4u 2 2 2u 2u 2u 2u 2 2 1 1 2 2 0 1 2u 2u REP0IF LFACLKLETIMERn LETn_O0 UFOA0 01 LETn_O1 UFOA0 10 Pulse Seq 1 Pulse Seq 2 Pulse Seq 3 4 4 4 4 4 4 2 2 2 2 2 0 0 2u The first two sequences are loaded into the LETIMER before the timer is started LETIMERn_COMP0 is set to 2 cycles 1 and LETI...

Page 597: ...eral ways of generating PWM output with the LETIMER but the most straight forward way is using the PWM output mode This mode is enabled by setting UFOA0 or OFUA1 in LETIMERn_CTRL to 3 In PWM mode the output is set idle on timer underflow and active on LETIMERn_COMP1 match so if for instance COMP0TOP 1 and OPOL0 0 in LETIMERn_CTRL LETIMERn_COMP0 determines the PWM period and LETIMERn_LETIMERn_COMP1...

Page 598: ...This will make the RTC use the internal 1 kHz ultra low frequency RC oscillator ULFRCO consuming very little energy Please note that the ULFRCO is not accurate over temperature and voltage and it should be verified that the ULFRCO fulfills the timekeeping needs of the application before using this in the design 23 3 8 Register access This module is a Low Energy Peripheral and supports immediate sy...

Page 599: ...0x034 LETIMERn_SYNCBUSY R Synchronization Busy Register 0x040 LETIMERn_ROUTE RW I O Routing Register 23 5 Register Description 23 5 1 LETIMERn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0x0 0x0 0x0 Acc...

Page 600: ...n 1 Defines the action on LETn_O1 on a LETIMER underflow Value Mode Description 0 NONE LETn_O1 is held at its idle value as defined by OPOL1 1 TOGGLE LETn_O1 is toggled on CNT underflow 2 PULSE LETn_O1 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow The output then returns to its idle value as defined by OPOL1 3 PWM LETn_O1 is set idle on CNT underflow and active on compare matc...

Page 601: ...TO1 0 W1 Clear Toggle Output 1 Set to drive toggle output 1 to its idle value 3 CTO0 0 W1 Clear Toggle Output 0 Set to drive toggle output 0 to its idle value 2 CLEAR 0 W1 Clear LETIMER Set to clear LETIMER 1 STOP 0 W1 Stop LETIMER Set to stop LETIMER 0 START 0 W1 Start LETIMER Set to start LETIMER 23 5 3 LETIMERn_STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20...

Page 602: ...e to read the current value of the LETIMER 23 5 5 LETIMERn_COMP0 Compare Value Register 0 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name COMP0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility wit...

Page 603: ...s please see Section 5 3 p 20 Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name REP0 Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 REP0 0x00 RW Repeat Counter 0 Optional repeat counter 23 5 8 LETIMERn_RE...

Page 604: ...hes zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag 2 UF 0 R Underflow Interrupt Flag Set on LETIMER underflow 1 COMP1 0 R Compare Match 1 Interrupt Flag Set when LETIMER reaches the value of COMP1 0 COMP0 0 R Compare Match 0 Interrupt Flag Set when LETIMER reaches the value of COMP0 23 5 10 LETIMERn_IFS Interrupt Flag Set Register Offset Bit Position 0x024 31 30 29 28 ...

Page 605: ...1 to clear the REP1 interrupt flag 3 REP0 0 W1 Clear Repeat Counter 0 Interrupt Flag Write to 1 to clear the REP0 interrupt flag 2 UF 0 W1 Clear Underflow Interrupt Flag Write to 1 to clear the UF interrupt flag 1 COMP1 0 W1 Clear Compare Match 1 Interrupt Flag Write to 1 to clear the COMP1 interrupt flag 0 COMP0 0 W1 Clear Compare Match 0 Interrupt Flag Write to 1 to clear the COMP0 interrupt fla...

Page 606: ...ter Update Freeze With the immediate write synchronization scheme the REGFREEZE register is no longer used Value Mode Description 0 UPDATE Each write access to a LETIMER register is updated into the Low Frequency domain as soon as possible 1 FREEZE The LETIMER is not updated with the new written value 23 5 14 LETIMERn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x034 31 30 29 28 27 ...

Page 607: ...TION OUT1PEN OUT0PEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATION 0x0 RW I O Location Decides the location of the LETIMER I O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 7 2 Reserved To ensure compatibility with future devi...

Page 608: ...rotations 24 1 Introduction The Pulse Counter PCNT can be used for counting incoming pulses on a single input or to decode quadrature encoded inputs It can run from the internal LFACLK EM0 EM2 while counting pulses on the PCNTn_S0IN pin or using this pin as an external clock source EM0 EM3 that runs both the PCNT counter and register access 24 2 Features 16 8 bit counter with reload register Auxil...

Page 609: ...CTRL register Additionally the PCNTn_S0IN input may be inverted so that falling edges are counted by setting the EDGE bit in the PCNTn_CTRL register If S1CDIR is cleared PCNTn_S0IN is the only observed input in this mode The PCNTn_S0IN input is sampled by the LFACLK and the number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT The counter may be configured to count down ...

Page 610: ...tion of a rotating shaft as illustrated by Figure 24 2 p 610 hence the direction of the counter register PCNTn_CNT is controlled automatically Figure 24 2 PCNT Quadrature Coding X X 1 cycle sector 4 states 01 11 10 00 X X 1 cycle sector 4 states 00 10 11 01 X sensor position Clockwise direction Counter clockwise direction PCNTn_S0IN PCNTn_S1IN PCNTn_S0IN PCNTn_S1IN PCNTn_CNT Reset 0 0 1 2 PCNTn_CN...

Page 611: ...ter will always wrap to TOP 2 on underflows and overflows This takes the counter away from the area where it might overflow or underflow removing the problem Given a starting value of 0 for the counter the absolute count value when hysteresis is enabled can be calculated with the equations Equation 24 1 p 611 or Equation 24 2 p 611 depending on whether the TOP value is even or odd Absolute positio...

Page 612: ...Peripherals Note PCNTn_TOP and PCNTn_CNT are read only registers When writing to PCNTn_TOPB make sure that the counter value PCNTn_CNT can not exceed the value written to PCNTn_TOPB within two clock cycles 24 3 5 Clock Sources The 32 kHz LFACLK is one of two possible clock sources The clock select register is described in Chapter 11 p 126 The default clock source is the LFACLK This PCNT module may...

Page 613: ...lag UF is set when the counter counts down from 0 I e when the value of the counter is 0 and a new pulse is received The PCNTn_CNT register is loaded with the PCNTn_TOP value after this event The overflow interrupt flag OF is set when the counter counts up from the PCNTn_TOP reload value I e if PCNTn_CNT PCNTn_TOP and a new pulse is received The PCNTn_CNT register is loaded with the value 0 after ...

Page 614: ...on 24 5 1 PCNTn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0 0 0 0 0 0 0x0 Access RW RW RW RW RW RW RW RW RW Name AUXCNTEV CNTEV S1CDIR HYST RSTEN FILT EDGE CNTDIR MODE Bit Name Reset Access Description 31 1...

Page 615: ...lter is only available in OVSSINGLE mode 3 EDGE 0 RW Edge Select Determines the polarity of the incoming edges This bit should be written when PCNT is in DISABLE mode otherwise the behavior is unpredictable This bit is ignored in EXTCLKSINGLE mode Value Mode Description 0 POS Positive edges on the PCNTn_S0IN inputs are counted in OVSSINGLE mode 1 NEG Negative edges on the PCNTn_S0IN inputs are cou...

Page 616: ...Reset 0 Access R Name DIR Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 DIR 0 R Current Counter Direction Current direction status of the counter This bit is valid in EXTCLKQUAD mode only Value Mode Description 0 UP Up counter mode clockwise in EXTCLKQUAD mode with the NEDGE bit in PCNTn_CTRL...

Page 617: ...is written to the PCNTn_CNT register when counting past this value 24 5 6 PCNTn_TOPB Top Value Buffer Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00FF Access RW Name TOPB Bit Name Reset Access Description 31 16 Reserved To ensu...

Page 618: ... Access W1 W1 W1 W1 Name AUXOF DIRCNG OF UF Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 AUXOF 0 W1 Auxiliary Overflow Interrupt Set Write to 1 to set the auxiliary overflow interrupt flag 2 DIRCNG 0 W1 Direction Change Detect Interrupt Set Write to 1 to set the direction change interrupt fl...

Page 619: ...scription 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 AUXOF 0 RW Auxiliary Overflow Interrupt Enable Enable the auxiliary overflow interrupt 2 DIRCNG 0 RW Direction Change Detect Interrupt Enable Enable the direction change detect interrupt 1 OF 0 RW Overflow Interrupt Enable Enable the overflow interrupt 0 UF 0 RW Underflo...

Page 620: ... the PCNT clock domain is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to a PCNT register is updated into the Low Frequency domain as soon as possible 1 FREEZE The PCNT clock domain is not updated with the new written value 24 5 13 PCNTn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x030 ...

Page 621: ...t 0 0x0 0 0x0 Access RW RW RW RW Name S1PRSEN S1PRSSEL S0PRSEN S0PRSSEL Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 S1PRSEN 0 RW S1IN PRS Enable When set the PRS channel is selected as input to S1IN 9 6 S1PRSSEL 0x0 RW S1IN PRS Channel Select Select PRS channel as input to S1IN Value Mode...

Page 622: ...Channel Select Select PRS channel as input to S0IN Value Mode Description 0 PRSCH0 PRS Channel 0 selected 1 PRSCH1 PRS Channel 1 selected 2 PRSCH2 PRS Channel 2 selected 3 PRSCH3 PRS Channel 3 selected 4 PRSCH4 PRS Channel 4 selected 5 PRSCH5 PRS Channel 5 selected 6 PRSCH6 PRS Channel 6 selected 7 PRSCH7 PRS Channel 7 selected 8 PRSCH8 PRS Channel 8 selected 9 PRSCH9 PRS Channel 9 selected 10 PRS...

Page 623: ...oder is capable of processing sensor data without CPU intervention A large result buffer allows the chip to remain in EM2 for long periods of time while autonomously collecting data 25 1 Introduction LESENSE is a low energy sensor interface which utilizes on chip peripherals to perform measurement of a configurable set of sensors The results from sensor measurements can be processed by the LESENSE...

Page 624: ...k is used for storage of configuration and measurement results This allows LESENSE to have a relatively large result buffer enabling the chip to remain in a low energy mode for long periods of time while collecting sensor data Figure 25 1 LESENSE block diagram LESENSE Counter Compare Decoder PRS input DAC0 AUXHFRCO ACMP1 ACMP1_CHn LES_ALTEXn Register bitfields overridden by LESENSE Scaler 1 25 V 2...

Page 625: ...wing the decoder state to define which configuration to use enables easy implementation of for instance hysteresis as different threshold values can be used for the same channel depending on the state of the application Table 25 1 p 625 summarizes how channel configuration is selected for different setting of SCANCONF Table 25 1 LESENSE scan configuration selection SCANCONF DIRMAP INVMAP TOGGLE DE...

Page 626: ...E and a high frequency timer running on AUXHFRCO Timing of the excite phase is done using these timers and can be either a number of prescaled AUXHFRCO cycles or a number of prescaled LFACLKLESENSE cycles depending on which one is selected in EXCLK The prescaling can be done by configuring LFPRESC in TIMCTRL for the low frequency timer and the high frequency timer prescaling factor is configured i...

Page 627: ... to perform sensor excitation on another pin than the one to be measured When ALTEX in CHx_INTERACT is set the excitation will occur on the alternative excite pin associated with the given channel All LESENSE channels mapped to ACMP0 have their alternative channel mapped to the corresponding channel on ACMP1 and vice versa Alternatively the alternative excite pins can be routed to the LES_ALTEX pi...

Page 628: ... channel and alternative excite pin in the IDLECONF and ALTEXCONF registers The modes available are the same as the modes available in the excitation phase In the measure phase the pin mode on the active channel is always disabled analog input To enable LESENSE to control GPIO the pin has to be enabled in the ROUTE register In addition the given pin must be configured as push pull IDLECONF configu...

Page 629: ...nd many other decoding schemes can be described as a finite state machine To support this type of decoding without CPU intervention LESENSE includes a highly configurable decoder capable of decoding input from up to four sensors The decoder is implemented as a programmable state machine with up to 16 states When doing a sensor scan the results from the sensors are placed in the decoder input regis...

Page 630: ...based on these PRS outputs If SETIF is set the DECODER interrupt flag will be set when the transition occurs If INTMAP in DECCTRL and SETIF is set a transition from state x will set the CHx interrupt flag in addition to the DECODER flag Setting CHAIN in STx_TCONFA enables the decoder to evaluate more than two possible transitions for each state If none of the transitions defined in STx_TCONFA or S...

Page 631: ...SKAi 1 Y N SENSORSTATE MASKBi 1 COMPBi 1 MASKBi 1 Y N SENSORSTATE changed ERRCHK 1 Y N CHAINi 1 1 Y N Note If only one transition from a state is used STx_TCONFA and STx_TCONFB should be configured equally To prevent unnecessary interrupt requests or PRS outputs when the decoder toggles back and forth between two states a hysteresis option is available The hysteresis function is triggered if a typ...

Page 632: ... data read from the result read register BUFDATA is the oldest unread result The location pointers are available in PTR The result buffer has three status flags BUFDATAV BUFHALFFULL and BUFFULL The flags indicate when new data is available when the buffer is half full and when it is full respectively The interrupt flag BUFDATAV is set when data is available in the buffer BUFLEVEL is set when the b...

Page 633: ...L The DAC interface runs on AUXHFRCO and will enable this when it is needed The DACPRESC bit field in PERCTRL is used to prescale the AUXHFRCO to achieve wanted clock frequency for the LESENSE DAC interface The frequency should not exceed 500kHz i e DACPRESC has to be set to at least 1 The prescaler may also be used to tune how long the DAC should drive its outputs in sample off mode Bias configur...

Page 634: ...et to DONTTOUCH LESENSE will not control the bias module 25 3 11 DMA requests LESENSE issues a DMA request when the result buffer is either full or half full depending on the configuration of BUFIDL in CTRL The request is cleared when the buffer level drops below the threshold defined in BUFIDL A single DMA request is also set whenever there is unread data in the buffer DMAWU in CTRL configures at...

Page 635: ...PLEDLY LFACLKLESENSE seconds MEASUREDLY should be set to 0 5 Set CTRTHRESHOLD to an appropriate value An interrupt will be issued if the counter value for a sensor is below this threshold after the measurement phase 6 Enable interrupts on channels 0 through 3 7 Start scan sequence by writing a 1 to START in CMD In a capacitive sense application it might be required to calibrate the threshold value...

Page 636: ... to damp the oscillations 4 Configure the ACMP to use scaled Vdd as negative input refer to ACMP chapter for details 5 Enable and configure PCNT and asynchronous PRS 6 Configure the GPIOs used as PUSHPULL 7 Configure the following bit fields in CHx_CONF for channels 0 through 3 a Set EXCLK to AUXHFRCO AUXHFRCO is needed to achieve short excitation time b Set EXTIME to an appropriate value Excitati...

Page 637: ...ed by the decoder b Configure the remaining bit fields in STx_TCONFA and STx_TCONFB as described in Table 25 3 p 637 Table 25 3 LESENSE decoder configuration Register TCONFA_NEXTSTATE TCONFA_COMP TCONFA_PRSACT TCONFB_NEXTSTATE TCONFB_COMP TCONFB_PRSACT ST0 1 0b001 UP 7 0b100 DOWN ST1 2 0b011 UP 0 0b000 DOWN ST2 3 0b010 UP 1 0b001 DOWN ST3 4 0b110 UP 2 0b011 DOWN ST4 5 0b111 UP 3 0b010 DOWN ST5 6 0...

Page 638: ... 6 0b0010 0b1000 ST2_TCONFA 8 0b1000 0b0111 1 ST2_TCONFB 4 0b0011 0b1000 ST3_TCONFA 0 0b0000 0b1000 0 ST3_TCONFB 0 0b0000 0b1000 ST4_TCONFA 8 0b1000 0b0111 1 ST4_TCONFB 6 0b0010 0b1000 ST5_TCONFA 2 0b0001 0b1000 0 ST5_TCONFB 2 0b0001 0b1000 ST6_TCONFA 8 0b1000 0b0111 1 ST6_TCONFB 0 0b0000 0b1000 ST7_TCONFA 4 0b0011 0b1000 0 ST7_TCONFB 4 0b0011 0b1000 2 To initialize the decoder run one scan and re...

Page 639: ...iguration 0x040 LESENSE_IF R Interrupt Flag Register 0x044 LESENSE_IFC W1 Interrupt Flag Clear Register 0x048 LESENSE_IFS W1 Interrupt Flag Set Register 0x04C LESENSE_IEN RW Interrupt Enable Register 0x050 LESENSE_SYNCBUSY R Synchronization Busy Register 0x054 LESENSE_ROUTE RW I O Routing Register 0x058 LESENSE_POWERDOWN RW LESENSE RAM power down register 0x200 LESENSE_ST0_TCONFA RW State transiti...

Page 640: ...WU 0x0 RW DMA wake up from EM2 Value Mode Description 0 DISABLE No DMA wake up from EM2 1 BUFDATAV DMA wake up from EM2 when data is valid in the result buffer 2 BUFLEVEL DMA wake up from EM2 when the result buffer is full half full depending on BUFIDL configuration 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 18 BUFIDL 0 RW Res...

Page 641: ...CHX_CONF and CHX 8_CONF when channel x triggers 3 DECDEF The decoder state defines the CONF registers to be used 5 2 PRSSEL 0x0 RW Scan start PRS select Select PRS source for scan start if SCANMODE is set to PRS Value Mode Description 0 PRSCH0 PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4...

Page 642: ... counter clock frequency is LFACLKLESENSE 8 4 DIV16 The period counter clock frequency is LFACLKLESENSE 16 5 DIV32 The period counter clock frequency is LFACLKLESENSE 32 6 DIV64 The period counter clock frequency is LFACLKLESENSE 64 7 DIV128 The period counter clock frequency is LFACLKLESENSE 128 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sect...

Page 643: ...o ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 23 22 ACMP1MODE 0x0 RW ACMP1 mode Configure how LESENSE controls ACMP1 Value Mode Description 0 DISABLE LESENSE does not control ACMP1 1 MUX LESENSE controls the input mux POSSEL of ACMP1 2 MUXTHRES LESENSE controls the input mux and the threshold value VDDLEVEL of ACMP1 21 20 ACMP0MODE 0x0 RW ACM...

Page 644: ...iven in sample off mode 3 2 DACCH0CONV 0x0 RW DAC channel 0 conversion mode Value Mode Description 0 DISABLE LESENSE does not control DAC CH0 1 CONTINUOUS DAC channel 0 is driven in continuous mode 2 SAMPLEHOLD DAC channel 0 is driven in sample hold mode 3 SAMPLEOFF DAC channel 0 is driven in sample off mode 1 DACCH1DATA 0 RW DAC CH1 data selection Configure DAC data control Value Mode Description...

Page 645: ...t 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 8 PRSCH8 PRS Channel 8 selected as input 9 PRSCH9 PRS Channel 9 selected as input 10 PRSCH10 PRS Channel 10 selected as input 11 PRSCH11 PRS Channel 11 ...

Page 646: ...teresis is enabled in the decoder suppressing interrupt requests 5 HYSTPRS2 0 RW Enable decoder hysteresis on PRS2 output When set hysteresis is enabled in the decoder suppressing changes on PRS channel 2 4 HYSTPRS1 0 RW Enable decoder hysteresis on PRS1 output When set hysteresis is enabled in the decoder suppressing changes on PRS channel 1 3 HYSTPRS0 0 RW Enable decoder hysteresis on PRS0 outpu...

Page 647: ...ess Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 CLEARBUF 0 W1 Clear result buffer 2 DECODE 0 W1 Start decoder 1 STOP 0 W1 Stop scanning of sensors If issued during a scan the command will take effect after scan completion 0 START 0 W1 Start scanning of sensors 25 5 7 LESENSE_CHEN Channel enable Register Async Re...

Page 648: ... results Bit X will be set depending on channel X evaluation 25 5 9 LESENSE_STATUS Status Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access R R R R R R Name DACACTIVE SCANACTIVE RUNNING BUFFULL BUFHALFFULL BUFDATAV B...

Page 649: ...n to Incremented when LESENSE writes to result buffer 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 0 RD 0x0 R Result buffer read pointer These bits show the index of the oldest unread data in the result buffer Incremented on read from BUFDATA 25 5 11 LESENSE_BUFDATA Result buffer data register Async Reg For more information abo...

Page 650: ... 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access RWH Name DECSTATE Bit Name Reset Access Description 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 0 DECSTATE 0x0 RWH Shows the current decoder state 25 5 14 LESENSE_SENSORSTATE Decoder input register Async Reg For more information abou...

Page 651: ...Value Mode Description 0 DISABLE CH14 output is disabled in idle phase 1 HIGH CH14 output is high in idle phase 2 LOW CH14 output is low in idle phase 3 DACCH1 CH14 output is connected to DAC CH1 output in idle phase 27 26 CH13 0x0 RW Channel 13 idle phase configuration Value Mode Description 0 DISABLE CH13 output is disabled in idle phase 1 HIGH CH13 output is high in idle phase 2 LOW CH13 output...

Page 652: ...n idle phase 2 LOW CH7 output is low in idle phase 13 12 CH6 0x0 RW Channel 6 idle phase configuration Value Mode Description 0 DISABLE CH6 output is disabled in idle phase 1 HIGH CH6 output is high in idle phase 2 LOW CH6 output is low in idle phase 11 10 CH5 0x0 RW Channel 5 idle phase configuration Value Mode Description 0 DISABLE CH5 output is disabled in idle phase 1 HIGH CH5 output is high i...

Page 653: ...CH0 output is low in idle phase 3 DACCH0 CH0 output is connected to DAC CH0 output in idle phase 25 5 16 LESENSE_ALTEXCONF Alternative excite pin configuration Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0x0 0x...

Page 654: ...ase 1 HIGH ALTEX5 output is high in idle phase 2 LOW ALTEX5 output is low in idle phase 9 8 IDLECONF4 0x0 RW ALTEX4 idle phase configuration Value Mode Description 0 DISABLE ALTEX4 output is disabled in idle phase 1 HIGH ALTEX4 output is high in idle phase 2 LOW ALTEX4 output is low in idle phase 7 6 IDLECONF3 0x0 RW ALTEX3 idle phase configuration Value Mode Description 0 DISABLE ALTEX3 output is...

Page 655: ...H8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Bit Name Reset Access Description 31 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 CNTOF 0 R Set when the LESENSE counter overflows 21 BUFOF 0 R Set when the result buffer overflows 20 BUFLEVEL 0 R Set when the data buffer is full 19 BUFDATAV 0 R Set when data is available in the result buffe...

Page 656: ... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name CNTOF BUFOF BUFLEVEL BUFDATAV DECERR DEC SCANCOMPLETE CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Bit Name Reset Access Description 31 23 Reserved To ensure compatibility with future devices always w...

Page 657: ...7 CH7 0 W1 Write to 1 to clear CH7 interrupt flag 6 CH6 0 W1 Write to 1 to clear CH6 interrupt flag 5 CH5 0 W1 Write to 1 to clear CH5 interrupt flag 4 CH4 0 W1 Write to 1 to clear CH4 interrupt flag 3 CH3 0 W1 Write to 1 to clear CH3 interrupt flag 2 CH2 0 W1 Write to 1 to clear CH2 interrupt flag 1 CH1 0 W1 Write to 1 to clear CH1 interrupt flag 0 CH0 0 W1 Write to 1 to clear CH0 interrupt flag ...

Page 658: ...te to 1 to set the SCANCOMPLETE interrupt flag 15 CH15 0 W1 Write to 1 to set the CH15 interrupt flag 14 CH14 0 W1 Write to 1 to set the CH14 interrupt flag 13 CH13 0 W1 Write to 1 to set the CH13 interrupt flag 12 CH12 0 W1 Write to 1 to set the CH12 interrupt flag 11 CH11 0 W1 Write to 1 to set the CH11 interrupt flag 10 CH10 0 W1 Write to 1 to set the CH10 interrupt flag 9 CH9 0 W1 Write to 1 t...

Page 659: ...ction 2 1 p 3 22 CNTOF 0 RW Set to enable interrupt on the CNTOF interrupt flag 21 BUFOF 0 RW Set to enable interrupt on the BUFOF interrupt flag 20 BUFLEVEL 0 RW Set to enable interrupt on the BUFLEVEL interrupt flag 19 BUFDATAV 0 RW Set to enable interrupt on the BUFDATAV interrupt flag 18 DECERR 0 RW Set to enable interrupt on the DECERR interrupt flag 17 DEC 0 RW Set to enable interrupt on the...

Page 660: ...ROUTE ALTEXCONF IDLECONF SENSORSTATE DECSTATE CURCH BUFDATA PTR STATUS SCANRES CHEN CMD BIASCTRL DECCTRL PERCTRL TIMCTRL CTRL Bit Name Reset Access Description 31 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 26 EVAL 0 R LESENSE_CHx_EVAL Register Busy Set when the value written to LESENSE_CHx_EVAL is being synchronized 25 INTERAC...

Page 661: ... Set when the value written to LESENSE_SCANRES is being synchronized 6 CHEN 0 R LESENSE_CHEN Register Busy Set when the value written to LESENSE_CHEN is being synchronized 5 CMD 0 R LESENSE_CMD Register Busy Set when the value written to LESENSE_CMD is being synchronized 4 BIASCTRL 0 R LESENSE_BIASCTRL Register Busy Set when the value written to LESENSE_BIASCTRL is being synchronized 3 DECCTRL 0 R...

Page 662: ... RW ALTEX4 Pin Enable 19 ALTEX3PEN 0 RW ALTEX3 Pin Enable 18 ALTEX2PEN 0 RW ALTEX2 Pin Enable 17 ALTEX1PEN 0 RW ALTEX1 Pin Enable 16 ALTEX0PEN 0 RW ALTEX0 Pin Enable 15 CH15PEN 0 RW CH15 Pin Enable 14 CH14PEN 0 RW CH14 Pin Enable 13 CH13PEN 0 RW CH13 Pin Enable 12 CH12PEN 0 RW CH12 Pin Enable 11 CH11PEN 0 RW CH11 Pin Enable 10 CH10PEN 0 RW CH10 Pin Enable 9 CH9PEN 0 RW CH9 Pin Enable 8 CH8PEN 0 RW...

Page 663: ...o the LESENSE RAM Once it is powered down it cannot be powered up again 25 5 24 LESENSE_STx_TCONFA State transition configuration A Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset X X 0xX 0xX 0xX 0xX Access RW RW RW RW RW RW Name CHAIN SETIF ...

Page 664: ...own and generate pulse on LESPRS2 11 8 NEXTSTATE 0xX RW Next state index Index of next state to be entered if the sensor state equals COMP 7 4 MASK 0xX RW Sensor mask Set bit X to exclude sensor X from evaluation 3 0 COMP 0xX RW Sensor compare value State transition is triggered when sensor state equals COMP 25 5 25 LESENSE_STx_TCONFB State transition configuration B Async Reg For more information...

Page 665: ...2 11 8 NEXTSTATE 0xX RW Next state index Index of next state to be entered if the sensor state equals COMP 7 4 MASK 0xX RW Sensor mask Set bit X to exclude sensor X from evaluation 3 0 COMP 0xX RW Sensor compare value State transition is triggered when sensor state equals COMP 25 5 26 LESENSE_BUFx_DATA Scan results Async Reg For more information about Asynchronous Registers please see Section 5 3 ...

Page 666: ...l last EXTIME 1 EXCLK cycles 25 5 28 LESENSE_CHx_INTERACT Scan configuration Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x2C4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset X X X 0xX 0xX X 0xXXX Access RW RW RW RW RW RW RW Name ALTEX SAMPLECLK EXCLK EXMODE SETIF SAMPLE ACMPTHRES Bit Name R...

Page 667: ...n Value Mode Description 0 COUNTER Counter output will be used in comparison 1 ACMP ACMP output will be used in comparison 11 0 ACMPTHRES 0xXXX RW Set ACMP threshold Select ACMP threshold 25 5 29 LESENSE_CHx_EVAL Scan configuration Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x2C8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 ...

Page 668: ...e Description LESS 0 Comparison evaluates to 1 if counter value is less than COMPTHRES GE 1 Comparison evaluates to 1 if counter value is greater than or equal to COMPTHRES CH_INTERACT_SAMPLE ACMP LESS 0 Comparison evaluates to 1 if the ACMP output is 0 GE 1 Comparison evaluates to 1 if the ACMP output is 1 15 0 COMPTHRES 0xXXXX RW Decision threshold for counter Set counter threshold ...

Page 669: ...ernal reference 26 1 Introduction The Analog Comparator is used to compare the voltage of two analog inputs with a digital output indicating which input voltage is higher Inputs can either be one of the selectable internal references or from external pins Response time and thereby also the current consumption can be configured by altering the current supply to the comparator 26 2 Features 8 select...

Page 670: ...han the voltage on the negative input the digital output is high and vice versa The output of the comparator can be read in the ACMPOUT bit in ACMPn_STATUS It is possible to switch inputs while the comparator is enabled but all other configuration should only be changed while the comparator is disabled 26 3 1 Warm up Time The analog comparator is enabled by setting the EN bit in ACMPn_CTRL When th...

Page 671: ...le 26 1 Bias Configuration Bias Current µA HYSTSEL 0 BIASPROG FULLBIAS 0 HALFBIAS 1 FULLBIAS 0 HALFBIAS 0 FULLBIAS 1 HALFBIAS 1 FULLBIAS 1 HALFBIAS 0 0b0000 0 05 0 1 3 3 6 5 0b0001 0 1 0 2 6 5 13 0b0010 0 2 0 4 13 26 0b0011 0 3 0 6 20 39 0b0100 0 4 0 8 26 52 0b0101 0 5 1 0 33 65 0b0110 0 6 1 2 39 78 0b0111 0 7 1 4 46 91 0b1000 1 0 2 0 65 130 0b1001 1 1 2 2 72 143 0b1010 1 2 2 4 78 156 0b1011 1 3 2...

Page 672: ... on the mux inputs when the EN bit is toggled 26 3 5 Capacitive Sense Mode The analog comparator includes specialized hardware for capacitive sensing of passive push buttons Such buttons are traces on PCB laid out in a way that creates a parasitic capacitor between the button and the ground node Because a human finger will have a small intrinsic capacitance to ground the capacitance of the button ...

Page 673: ...through the EDGE bit in ACMPn_IEN The edge interrupt can also be used to wake up the device from EM3 EM1 The analog comparator also includes an interrupt flag WARMUP in ACMPn_IF which is set when a warm up sequence has finished An interrupt request will be sent if the WARMUP interrupt flag in ACMPn_IF is set and enabled through the WARMUP bit in ACMPn_IEN The comparator output is also available as...

Page 674: ...as current in accordance with Table 26 1 p 671 30 HALFBIAS 1 RW Half Bias Current Set this bit to 1 to halve the bias current in accordance with Table 26 1 p 671 29 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 27 24 BIASPROG 0x7 RW Bias Configuration These bits control the bias current level in accordance with Table 26 1 p 671 2...

Page 675: ...T6 50 mV hysteresis 7 HYST7 57 mV hysteresis 3 GPIOINV 0 RW Comparator GPIO Output Invert Set this bit to 1 to invert the comparator alternate function output to GPIO Value Mode Description 0 NOTINV The comparator output to GPIO is not inverted 1 INV The comparator output to GPIO is inverted 2 INACTVAL 0 RW Inactive Value The value of this bit is used as the comparator output when the comparator i...

Page 676: ...abled 1 Low power mode enabled 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 8 VDDLEVEL 0x00 RW VDD Reference Level Select scaling factor for VDD reference level VDD_SCALED VDD VDDLEVEL 63 7 4 NEGSEL 0x8 RW Negative Input Select Select negative input Value Mode Description 0 CH0 Channel 0 as negative input 1 CH1 Channel 1 a...

Page 677: ...mparator Active Analog comparator active status 26 5 4 ACMPn_IEN Interrupt Enable Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name WARMUP EDGE Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARM...

Page 678: ...P EDGE Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARMUP 0 W1 Warm up Interrupt Flag Set Write to 1 to set warm up finished interrupt flag 0 EDGE 0 W1 Edge Triggered Interrupt Flag Set Write to 1 to set edge triggered interrupt flag 26 5 7 ACMPn_IFC Interrupt Flag Clear Register Offset Bit...

Page 679: ...PPEN Bit Name Reset Access Description 31 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 LOCATION 0x0 RW I O Location Decides the location of the ACMP I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 7 1 Reserved To ensure compatibility with future devices always write bits to 0 More inform...

Page 680: ...parator is used to monitor the supply voltage from software An interrupt can be generated when the supply falls below or rises above a programmable threshold Note Note that VCMP comes in addition to the Power on Reset and Brown out Detector peripherals that both generate reset signals when the voltage supply is insufficient for reliable operation VCMP does not generate reset only interrupt Also no...

Page 681: ...iod is called the warm up time The warm up time is a configurable number of HFPERCLK cycles set in WARMTIME which should be set to at least 10 µs When the comparator is enabled and warmed up the VCMPACT bit in VCMP_STATUS will be set to indicate that the comparator is active As long as the comparator is not enabled or not warmed up VCMPACT will be cleared and the comparator output value is set to ...

Page 682: ...ut uninteresting input fluctuations around zero and only show changes that are big enough to breach the hysteresis threshold Figure 27 2 VCMP 20 mV Hysteresis Enabled InNEG VCMPOUT with hysteresis InNEG 20mV InNEG 20mV VCMPOUT without hysteresis Time InPOS 27 3 4 Input Selection The positive comparator input is always connected to the scaled power supply input The negative comparator input is conn...

Page 683: ... comparator output respectively An interrupt request will be sent if the EDGE interrupt flag in VCMP_IF is set and enabled through the EDGE bit in VCMPn_IEN The edge interrupt can also be used to wake up the device from EM3 EM1 VCMP also includes an interrupt flag WARMUP in VCMP_IF which is set when a warm up sequence has finished An interrupt request will be sent if the WARMUP interrupt flag in V...

Page 684: ...More information in Section 2 1 p 3 30 HALFBIAS 1 RW Half Bias Current Set this bit to 1 to halve the bias current Table 27 1 p 681 29 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 27 24 BIASPROG 0x7 RW VCMP Bias Programming Value These bits control the bias current level Table 27 1 p 681 23 18 Reserved To ensure compatibility wi...

Page 685: ...disable voltage supply comparator 27 5 2 VCMP_INPUTSEL Input Selection Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access RW RW Name LPREF TRIGLEVEL Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 LPREF 0 ...

Page 686: ...e Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARMUP 0 RW Warm up Interrupt Enable Enable disable interrupt on finished warm up 0 EDGE 0 RW Edge Trigger Interrupt Enable Enable disable edge triggered interrupt 27 5 5 VCMP_IF Interrupt Flag Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 2...

Page 687: ...Flag Set Write to 1 to set warm up finished interrupt flag 0 EDGE 0 W1 Edge Triggered Interrupt Flag Set Write to 1 to set edge triggered interrupt flag 27 5 7 VCMP_IFC Interrupt Flag Clear Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access W1 W1 Name WARMUP EDGE Bit Name Reset Access Description 31 2 Reserved T...

Page 688: ... duty cycled to reduce the energy consumption 28 1 Introduction The ADC is a Successive Approximation Register SAR architecture with a resolution of up to 12 bits at up to one million samples per second The integrated input mux can select inputs from 8 external pins and 6 internal signals 28 2 Features Programmable resolution 6 8 12 bit 13 prescaled clock ADC_CLK cycles per conversion Maximum 1 MS...

Page 689: ...upt flag set when overwriting unread results Hardware oversampling support 1st order accumulate and dump filter From 2 to 4096 oversampling ratio OSR Results in 16 bit representation Enabled individually for scan sequence and single sample mode Common OSR select Individually selectable voltage reference for scan and single mode Internal 1 25V reference Internal 2 5V reference VDD Internal 5 V diff...

Page 690: ...tion during the approximation phase The acquisition time can be configured independently for scan and single conversions see Section 28 3 7 p 694 by setting AT in ADCn_SINGLECTRL ADCn_SCANCTRL The acquisition times can be set to any integer power of 2 from 1 to 256 ADC_CLK cycles Note For high impedance sources the acquisition time should be adjusted to allow enough time for the internal sample ca...

Page 691: ...cted for scan mode can be kept warm If a different bandgap reference is selected for single mode the warm up time still applies NORMAL ADC and references are shut off when there are no samples waiting a in Figure 28 3 p 692 shows this mode used with an internal bandgap reference Figure d shows this mode when using VDD or an external reference FASTBG Bandgap warm up is eliminated but with reduced r...

Page 692: ..._SINGLECTRL and ADCn_SCANCTRL For offset calibration purposes it is possible to internally short the differential ADC inputs and thereby measure a 0 V differential Differential 0 V is selected by writing the DIFF bit to 1 and INPUTSEL to 4 in ADCn_SINGLECTRL Calibration is described in detail in Section 28 3 10 p 697 Note When VDD 3 is sampled the acquisition time should be above a lower limit The...

Page 693: ... for the device 28 3 5 Reference Selection The reference voltage can be selected from these sources 1 25 V internal bandgap 2 5 V internal bandgap VDD 5 V internal differential bandgap External single ended input from Ch 6 Differential input 2x Ch 6 Ch 7 Unbuffered 2xVDD The 2 5 V reference needs a supply voltage higher than 2 5 V The differential 5 V reference needs a supply voltage higher than 2...

Page 694: ...scan samples 28 3 7 1 Single Sample Mode The single sample mode can be used to convert a single sample either once per trigger or repetitively The configuration of the single sample mode is done in the ADCn_SINGLECTRL register and the results are found in the ADCn_SINGLEDATA register The SINGLEDV bit in ADCn_STATUS is set high when there is valid data in the result register and is cleared when the...

Page 695: ... cleared The SINGLEACT and SCANACT bits in ADCn_STATUS are set high when the modes are actively converting or have pending conversions It is also possible to trigger conversions from PRS signals The system requires one HFPERCLK cycle pulses to trigger conversions Setting PRSEN in ADCn_SINGLECTRL ADCn_SCANCTRL enables triggering from PRS input Which PRS channel to listen to is defined by PRSSEL in ...

Page 696: ... individually for each mode Set RES in ADCn_SINGLECTRL ADCn_SCANCTRL to 0x3 The oversampling rate OVSRSEL in ADCn_CTRL can be set to any integer power of 2 from 2 to 4096 and the configuration is shared between the scan and single sample mode OVSRSEL field in ADCn_CTRL With oversampling each selected input is sampled a number given by the OVSR of times and the results are filtered by a first order...

Page 697: ...des have separate interrupt flags indicating finished conversions Setting one of these flags will result in an ADC interrupt if the corresponding interrupt enable bit is set in ADCn_IEN In addition to the finished conversion flags there is a scan and single sample result overflow flag which signalizes that a result from a scan sequence or single sample has been overwritten before being read A fini...

Page 698: ...of the ADCn_SINGLECTRL register to 16CYCLES 3 Set the INPUTSEL bitfield of the ADCn_SINGLECTRL register to DIFF0 and set the DIFF bitfield to 1 for enabling differential input Since the input voltage is 0 the expected ADC output is the half of the ADC code range as it is in differential mode 4 A binary search is used to find the offset calibration value Set the SINGLESTART bit in the ADCn_CMD regi...

Page 699: ...RW Calibration Register 0x03C ADCn_BIASPROG RW Bias Programming Register 28 5 Register Description 28 5 1 ADCn_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x1F 0x00 0x0 0 0x0 Access RW RW RW RW RW RW Name OVSRSEL TIMEBASE PRESC LPFMODE TAILGATE WARMUPMODE Bit Name Reset Access Description 31 28 Rese...

Page 700: ... bits to 0 More information in Section 2 1 p 3 5 4 LPFMODE 0x0 RW Low Pass Filter Mode These bits control the filtering of the ADC input Details on the filter characteristics can be found in the device datasheets Value Mode Description 0 BYPASS No filter or decoupling capacitor 1 DECAP On chip decoupling capacitor selected 2 RCFILT On chip RC filter selected 3 TAILGATE 0 RW Conversion Tailgating E...

Page 701: ...inates Value Mode Description 0 CH0 Single ended mode SCANDATA result originates from ADCn_CH0 Differential mode SCANDATA result originates from ADCn_CH0 ADCn_CH1 1 CH1 Single ended mode SCANDATA result originates from ADCn_CH1 Differential mode SCANDATA result originates from ADCn_CH2_ADCn_CH3 2 CH2 Single ended mode SCANDATA result originates from ADCn_CH2 Differential mode SCANDATA result origi...

Page 702: ...e Description 0 PRSCH0 PRS ch 0 triggers single sample 1 PRSCH1 PRS ch 1 triggers single sample 2 PRSCH2 PRS ch 2 triggers single sample 3 PRSCH3 PRS ch 3 triggers single sample 4 PRSCH4 PRS ch 4 triggers single sample 5 PRSCH5 PRS ch 5 triggers single sample 6 PRSCH6 PRS ch 6 triggers single sample 7 PRSCH7 PRS ch 7 triggers single sample 8 PRSCH8 PRS ch 8 triggers single sample 9 PRSCH9 PRS ch 9...

Page 703: ...Unbuffered 2xVDD 15 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 8 INPUTSEL 0x0 RW Single Sample Input Selection Select input to ADC single sample mode in either single ended mode or differential mode DIFF 0 Mode Value Description CH0 0 ADCn_CH0 CH1 1 ADCn_CH1 CH2 2 ADCn_CH2 CH3 3 ADCn_CH3 CH4 4 ADCn_CH4 CH5 5 ADCn_CH5 CH6 6 ...

Page 704: ... is written 28 5 5 ADCn_SCANCTRL Scan Control Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0x0 0x0 0x00 0x0 0 0 0 Access RW RW RW RW RW RW RW RW RW Name PRSSEL PRSEN AT REF INPUTMASK RES ADJ DIFF REP Bit Name Reset Access Description 31 28 PRSSEL 0x0 RW Scan Sequence PRS Trigger Select Select PRS trigger for sc...

Page 705: ...to ADC scan sequence Value Mode Description 0 1V25 Internal 1 25 V reference 1 2V5 Internal 2 5 V reference 2 VDD VDD 3 5VDIFF Internal differential 5 V reference 4 EXTSINGLE Single ended external reference from ADCn_CH6 5 2XEXTDIFF Differential external reference 2x ADCn_CH6 ADCn_CH7 6 2XVDD Unbuffered 2xVDD 15 8 INPUTMASK 0x00 RW Scan Sequence Input Mask Set one or more bits in this mask to sele...

Page 706: ...uence Value Description 0 Scan conversion mode is deactivated after one sequence 1 Scan conversion mode is converting continuously until SCANSTOP is written 28 5 6 ADCn_IEN Interrupt Enable Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access RW RW RW RW Name SCANOF SINGLEOF SCAN SINGLE Bit Name Reset Access D...

Page 707: ...plete when this bit is set 0 SINGLE 0 R Single Conversion Complete Interrupt Flag Indicates single conversion complete when this bit is set 28 5 8 ADCn_IFS Interrupt Flag Set Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access W1 W1 W1 W1 Name SCANOF SINGLEOF SCAN SINGLE Bit Name Reset Access Description 31 1...

Page 708: ...t Flag Clear Write to 1 to clear single result overflow interrupt flag 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 SCAN 0 W1 Scan Conversion Complete Interrupt Flag Clear Write to 1 to clear scan conversion complete interrupt flag 0 SINGLE 0 W1 Single Conversion Complete Interrupt Flag Clear Write to 1 to clear single conver...

Page 709: ...lt Data The register holds the results from the last scan conversion Reading this field clears the SCANDV bit in the ADCn_STATUS register 28 5 12 ADCn_SINGLEDATAP Single Conversion Result Data Peek Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATAP Bit Name Reset Access Description 31 0 DATAP...

Page 710: ... value for the 1V25 internal reference during reset hence the reset value might differ from device to device The field is unsigned Higher values lead to higher ADC results 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 16 SCANOFFSET 0x00 RW Scan Mode Offset Calibration Value This register contains the offset calibration value u...

Page 711: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x7 1 0x7 Access RW RW RW Name COMPBIAS HALFBIAS BIASPROG Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 8 COMPBIAS 0x7 RW Comparator Bias Value These bits are used to adjust the bias current to the ADC Comparator 7 Reserv...

Page 712: ...n convert a digital value to an analog output voltage The DAC is fully differential rail to rail with 12 bit resolution It has two single ended output buffers which can be combined into one differential output The DAC may be used for a number of different applications such as sensor interfaces or sound output 29 2 Features 500 ksamples s operation Two single ended output channels Can be combined i...

Page 713: ...e Hold Mode In sample hold mode the DAC core converts data on a triggered conversion and then holds the output in a sample hold element When not converting the DAC core is turned off between samples which reduces the power consumption Because of output voltage drift the sample hold element will only hold the output for a certain period without a refresh conversion The reader is referred to the ele...

Page 714: ... a prescaler setting higher than 0 there will be an unpredictable delay from the time the conversion was triggered to the time the actual conversion takes place This is because the conversions is controlled by the prescaled clock and the conversion can arrive at any time during a prescaled clock DAC_CLK period However if the CH0PRESCRST bit in DACn_CTRL is set the prescaler will be reset every tim...

Page 715: ...ingle Ended Output When operating in single ended mode the channel 0 output is on DACn_OUT0 and the channel 1 output is on DACn_OUT1 The output voltage can be calculated using Equation 29 2 p 715 DAC Single Ended Output Voltage VOUT VDACn_OUTx VSS Vref x CHxDATA 4095 29 2 where CHxDATA is a 12 bit unsigned integer 29 3 4 2 Differential Output When operating in differential mode both DAC outputs ar...

Page 716: ...at new data can be written to the data registers Setting one of these flags will result in a DAC interrupt if the corresponding interrupt enable bit is set in DACn_IEN All generated interrupts from the DAC will activate the same interrupt vector when enabled The DAC has two PRS outputs which will carry a one cycle HFPERCLK high pulse when the corresponding channel has finished a conversion 29 3 7 ...

Page 717: ...through the CHxOFFSET bit fields Gain is calibrated in one common register field GAIN The gain calibration is linked to the reference and when the reference is changed the gain must be re calibrated Gain and offset for the 1V25 2V5 and VDD references are calibrated during production and the calibration values for these can be found in the Device Information page During reset the gain and offset ca...

Page 718: ...OPA0MUX RW Operational Amplifier Mux Configuration Register 0x060 DACn_OPA1MUX RW Operational Amplifier Mux Configuration Register 0x064 DACn_OPA2MUX RW Operational Amplifier Mux Configuration Register 29 5 Register Description 29 5 1 DACn_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0 0 0x1 ...

Page 719: ...start Value Description 0 Prescaler not reset on channel 0 start 1 Prescaler reset on channel 0 start 6 OUTENPRS 0 RW PRS Controlled Output Enable Enable PRS Control of DAC output enable Value Description 0 DAC output enable always on 1 DAC output enable controlled by PRS signal selected for CH1 5 4 OUTMODE 0x1 RW Output Mode Select output mode Value Mode Description 0 DISABLE DAC output to pin an...

Page 720: ...SEN REFREN EN Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 4 PRSSEL 0x0 RW Channel 0 PRS Trigger Select Select Channel 0 PRS input channel Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 0 conversion 1 PRSCH1 PRS ch 1 triggers channel 0 conversion 2 PRSCH2 PRS ch 2 triggers channel...

Page 721: ...el Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 1 conversion 1 PRSCH1 PRS ch 1 triggers channel 1 conversion 2 PRSCH2 PRS ch 2 triggers channel 1 conversion 3 PRSCH3 PRS ch 3 triggers channel 1 conversion 4 PRSCH4 PRS ch 4 triggers channel 1 conversion 5 PRSCH5 PRS ch 5 triggers channel 1 conversion 6 PRSCH6 PRS ch 6 triggers channel 1 conversion 7 PRSCH7 PRS ch 7 triggers channel 1 c...

Page 722: ...in Section 2 1 p 3 1 CH1 0 RW Channel 1 Conversion Complete Interrupt Enable Enable disable channel 1 conversion complete interrupt 0 CH0 0 RW Channel 0 Conversion Complete Interrupt Enable Enable disable channel 0 conversion complete interrupt 29 5 6 DACn_IF Interrupt Flag Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rese...

Page 723: ...omplete Interrupt Flag Set Write to 1 to set channel 1 conversion complete interrupt flag 0 CH0 0 W1 Channel 0 Conversion Complete Interrupt Flag Set Write to 1 to set channel 0 conversion complete interrupt flag 29 5 8 DACn_IFC Interrupt Flag Clear Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access W1 W1 W1...

Page 724: ...hannel 1 Data Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 Access RW Name DATA Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 0 DATA 0x000 RW Channel 1 Data This register contains the value which will be ...

Page 725: ... future devices always write bits to 0 More information in Section 2 1 p 3 13 8 CH1OFFSET 0x00 RW Channel 1 Offset Calibration Value This register contains the offset calibration value used with channel 1 conversions This field is set to the production channel 1 offset calibration value for the 1V25 internal reference during reset hence the reset value might differ from device to device The field ...

Page 726: ...me Reset Access Description 31 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 24 OPA2SHORT 0 RW Short the non inverting and inverting input Set to short the non inverting and inverting input 23 OPA1SHORT 0 RW Short the non inverting and inverting input Set to short the non inverting and inverting input 22 OPA0SHORT 0 RW Short the ...

Page 727: ... input while output still remains rail to rail The input voltage to the opamp while HCM is disabled is restricted between VSS and VDD 1 2V 5 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 OPA2EN 0 RW OPA2 Enable Set to enable OPA2 clear to disable 1 OPA1EN 0 RW OPA1 Enable Set to enable OPA1 clear to disable CH1EN in DAC_CH1CTRL ...

Page 728: ...7 8 7 RES7 R2 15 x R1 15 16 27 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 26 NEXTOUT 0 RW OPA0 Next Enable Makes output of OPA0 available to OPA1 25 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 23 22 OUTMODE 0x1 RW Output Select Select output channel Value Mode...

Page 729: ...ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 0 POSSEL 0x0 RW OPA0 non inverting Input Mux These bits selects the source for the non inverting input on OPA0 Value Mode Description 0 DISABLE Input disabled 1 DAC DAC as input 2 POSPAD POS PAD as input 3 OPA0INP OPA0 as input 4 OPATAP OPA0 Resistor ladder as input 29 5 17 DACn_OPA1MUX Operationa...

Page 730: ... to enable output clear to disable output OUT ENABLE VALUE Description OUT0 xxxx1 Alternate Output 0 OUT1 xxx1x Alternate Output 1 OUT2 xx1xx Alternate Output 2 OUT3 x1xxx Alternate Output 3 OUT4 1xxxx Alternate Output 4 13 NPEN 0 RW OPA1 Negative Pad Input Enable Connects pad to the negative input mux 12 PPEN 0 RW OPA1 Positive Pad Input Enable Connects pad to the positive input mux 11 Reserved T...

Page 731: ...ation in Section 2 1 p 3 30 28 RESSEL 0x0 RW OPA2 Resistor Ladder Select Configures the resistor ladder tap for OPA2 Value Mode Resistor Value Inverting Mode Gain R2 R1 Non inverting Mode Gain 1 R2 R1 0 RES0 R2 1 3 x R1 1 3 1 1 3 1 RES1 R2 R1 1 2 2 RES2 R2 1 2 3 x R1 1 2 3 2 2 3 3 RES3 R2 2 x R1 2 1 5 3 1 5 4 RES4 R2 3 x R1 3 4 5 RES5 R2 4 1 3 x R1 4 1 3 5 1 3 6 RES6 R2 7 x R1 7 8 7 RES7 R2 15 x R...

Page 732: ...AD NEG PAD connected 3 POSPAD POS PAD connected 4 VSS VSS connected 7 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 4 NEGSEL 0x0 RW OPA2 inverting Input Mux These bits selects the source for the inverting input on OPA2 Value Mode Description 0 DISABLE Input disabled 1 UG Unity Gain feedback path 2 OPATAP OPA2 Resistor ladder as ...

Page 733: ...d and differential to differential driver modes The opamps can also be configured as a one two or three step cascaded PGA and for all of the built in modes no external components are necessary 30 1 Introduction The opamps are highly configurable general purpose opamps suitable for simple filters and buffer applications The three opamps can be configured to support various operational amplifier fun...

Page 734: ...ew OPA0 DAC OPA0 Alternative outputs OPA0 Main output OPA0NEXT OPA1 OPA1 Alternative outputs OPA1 Main output OPA1NEXT OPA2 OPA2 Main outputs ADC CH5 input mux POS0 NEG0 POS1 NEG1 POS2 NEG2 ADC CH0 input mux ADC CH1 input mux ADC CH0 input mux A more detailed view of the three opamps including the mux network is shown in Figure 30 2 p 735 There is a set of input muxes for each opamp making it poss...

Page 735: ...n_OPACTRL 30 3 1 1 Input Configuration The inputs to the opamps are controlled through a set of input muxes The mux connected to the positive input is configured by the POSSEL bit field in the DACn_OPAxMUX register Similarly the mux connected to the negative input is configured by setting the NEGSEL bit field in DACn_OPAxMUX To connect the pins to the input muxes the pin switches must also be enab...

Page 736: ...two main outputs can be connected to ADC input mux CH0 and ADC input mux CH5 respectively when enabled See Section 28 3 4 p 692 in the ADC chapter for information on how to configure the ADC input mux 30 3 1 3 Gain Programming The feedback path of each mux includes a resistor ladder which can be used to select a set of gain values The gain can be selected by the RESSEL bit field located in DACn_OP...

Page 737: ...ailable are described in the following sections 30 3 2 1 General Opamp Mode In this mode the resistor ladder is isolated from the feedback path and input signal routing is defined by OPAxPOSSEL and OPAxNEGSEL in DACn_OPAxMUX The output signal routing is defined by OUTPEN in DACn_OPAxMUX Table 30 1 General Opamp Mode Configuration OPA bit fields OPA Configuration OPAx POSSEL POSPADx OPAx NEGSEL OPA...

Page 738: ...OS R1 R2 POS VIN Table 30 3 Inverting input PGA Configuration OPA bit fields OPA Configuration OPAx POSSEL POSPADx OPAx NEGSEL OPATAP OPAx RESINMUX NEXTOUT NEGPADx POSPADx 30 3 2 4 Non inverting PGA Figure 30 6 p 738 shows the non inverting input configuration In this mode the negative input is connected to the resistor ladder by setting the OPAxNEGSEL bit field to OPATAP in DACn_OPAxMUX This sett...

Page 739: ...gure 30 7 Cascaded Inverting PGA Overview R1 R2 VIN POS0 VOUT1 VIN POS0 x R2 R1 POS0 VOUT2 VOUT1 POS1 x R2 R1 POS1 VOUT3 VOUT2 POS3 x R2 R1 POS3 R1 R2 POS1 R1 R2 POS2 Table 30 5 Cascaded Inverting PGA Configuration OPA OPA bit fields OPA Configuration OPA0 POSSEL POSPAD0 OPA0 NEGSEL OPA0TAP OPA0 RESINMUX NEGPAD0 OPA0 NEXTOUT 1 OPA1 POSSEL POSPAD1 OPA1 NEGSEL OPATAP OPA1 RESINMUX OPA0INP OPA1 NEXTO...

Page 740: ...y input by configuring the OPA0POSSEL bit field in DACn_OPA0MUX The OPA0 feedback path must be configured to unity gain by setting the OPA0NEGSEL bit field to UG in DACn_OPA0MUX In addition the OPA0RESINMUX bit field must be set to DISABLED The OPA0OUT must be connected to OPA1 by setting NEXTOUT in DACn_OPA0MUX and OPA1RESINMUX to OPA0INP The positive input on OPA1 can be set by configuring OPA1P...

Page 741: ...elds OPA Configuration OPA1 POSSEL POSPAD1 OPA1 NEGSEL UG OPA1 RESINMUX DISABLE OPA1 NEXTOUT 1 OPA2 POSSEL POSPAD1 OPA2 NEGSEL OPATAP OPA2 RESINMUX OPA1INP 30 3 2 8 Three Opamp Differential Amplifier This mode enables the three opamps to be internally configured to form a three opamp differential amplifier as shown in Figure 30 10 p 742 Both OPA0 and OPA1 can be configured in the same unity gain m...

Page 742: ...erent gain values available 1 3 1 and 3 can be programmed as shown in the table below Table 30 9 Three Opamp Differential Amplifier Gain Programming Gain OPA0 RESSEL OPA2 RESSEL 1 3 4 0 1 1 1 3 0 4 Table 30 10 Three Opamp Differential Amplifier Configuration OPA OPA bit fields OPA Configuration OPA0 POSSEL POSPAD OPA0 NEGSEL UG OPA0 RESINMUX DISABLE OPA1 POSSEL POSPAD OPA1 NEGSEL UG OPA1 RESINMUX ...

Page 743: ...it is not possible to use both DAC channels and all three opamps at the same time If both DAC channels are used only OPA2 is available out of the 3 opamps However it is possible to use one of the DAC channels in combination with OPA0 OPA1 OPA1 is available when DAC channel 0 is in use and OPA0 is available when DAC channel 1 is used When using the opamp DAC combination the DAC CONVMODE can only be...

Page 744: ...with 256 bit keys The AES module is an AHB slave which enables efficient access to the data and key registers All write accesses to the AES module must be 32 bit operations i e 8 or 16 bit operations are not supported 31 2 Features AES hardware encryption decryption 128 bit key 54 HFCORECLK cycles 256 bit key 75 HFCORECLK cycles Efficient CPU DMA support Interrupt on finished encryption decryption...

Page 745: ...able byte ordering which is configured in BYTEORDER in AES_CTRL Figure 31 2 p 745 illustrates how data written to the AES registers is mapped to the key and state defined in the Advanced Encryption Standard FIPS 197 The figure presents the key byte order for 256 bit keys In 128 bit mode with BYTEORDER cleared a16 represents the first byte of the 128 bit key When BYTEORDER is set a0 represents the ...

Page 746: ...e the contents of the key registers will be turned into the CipherKey during the encryption The opposite applies when decrypting where you have to re supply the CipherKey between each block However in AES128 mode KEY4 KEY7 can be used as a buffer register to hold an extra copy of the KEY3 KEY0 registers When KEYBUFEN is set in AES_CTRL the contents of KEY7 KEY4 are copied to KEY3 KEY0 when an encr...

Page 747: ...rform Cipher Block Chaining with 128 bit keys Example 31 1 AES Cipher Block Chaining 1 Configure module to encryption key buffer enabled and XORSTART in AES_CTRL 2 Write 128 bit initialization vector to AES_DATA starting with least significant word 3 Write PlainKey to AES_KEYHn starting with least significant word 4 Write PlainText to AES_XORDATA starting with least significant word Encryption wil...

Page 748: ...ister 0x04C AES_KEYHD RW KEY High Register 31 5 Register Description 31 5 1 AES_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access RW RW RW RW RW RW Name BYTEORDER XORSTART DATASTART KEYBUFEN AES256 DECRYPT Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future d...

Page 749: ... Reset 0 0 Access W1 W1 Name STOP START Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 STOP 0 W1 Encryption Decryption Stop Set to stop encryption decryption 0 START 0 W1 Encryption Decryption Start Set to start encryption decryption 31 5 3 AES_STATUS Status Register Offset Bit Position 0x008 ...

Page 750: ...010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name DONE Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 DONE 0 R Encryption Decryption Done Interrupt Flag Set when an encryption decryption has finished 31 5 6 AES_IFS Interrupt Flag Se...

Page 751: ...nformation in Section 2 1 p 3 0 DONE 0 W1 Encryption Decryption Done Interrupt Flag Clear Write to 1 to clear encryption decryption done interrupt flag 31 5 8 AES_DATA DATA Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name DATA Bit Name Reset Access Description 31 0 DATA 0x00000000 RW Data Access...

Page 752: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYLA Bit Name Reset Access Description 31 0 KEYLA 0x00000000 RW Key Low Access A Access the low key words through this register 31 5 11 AES_KEYLB KEY Low Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Nam...

Page 753: ... Key Low Access C Access the low key words through this register 31 5 13 AES_KEYLD KEY Low Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYLD Bit Name Reset Access Description 31 0 KEYLD 0x00000000 RW Key Low Access D Access the low key words through this register 31 5 14 AES_KEYHA KEY High ...

Page 754: ...2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYHB Bit Name Reset Access Description 31 0 KEYHB 0x00000000 RW Key High Access B Access the high key words through this register 31 5 16 AES_KEYHC KEY High Register Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name...

Page 755: ...om 31 5 17 AES_KEYHD KEY High Register Offset Bit Position 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYHD Bit Name Reset Access Description 31 0 KEYHD 0x00000000 RW Key High Access D Access the high key words through this register ...

Page 756: ...ent locations thus solving congestion issues that may arise with multiple functions on the same pin Fully asynchronous interrupts can also be generated from any pin 32 1 Introduction In the EFM32GG devices the General Purpose Input Output GPIO pins are organized into ports with up to 16 pins each These pins can individually be configured as either an output or input More advanced configurations li...

Page 757: ...GPIO pin is called Pxn where x indicates the port A B C and n indicates the pin number 0 1 15 Fewer than 16 bits may be available on some ports depending on the total number of I O pins on the package After a reset both input and output is disabled for all pins on the device except for debug pins To use a pin the port GPIO_Px_MODEL GPIO_Px_MODEH registers must be configured for the pin to make it ...

Page 758: ...er outputs or inputs the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations GPIO_Px_MODEL contains 8 bit fields named MODEn n 0 1 7 which control pins 0 7 while GPIO_Px_MODEH contains 8 bit fields named MODEn n 8 9 15 which control pins 8 15 In some modes GPIO_Px_DOUT is also used for extra configurations like pull up down and glitch suppression filter enable Ta...

Page 759: ...nd filter MODEn determines which mode the pin is in at a given time Setting MODEn to 0b0000 disables the pin reducing power consumption to a minimum When the output driver is disabled the pin can be used as a connection for an analog module e g ADC Input is enabled by setting MODEn to any value other than 0b0000 The pull up pull down and filter function can optionally be applied to the input see F...

Page 760: ...ck GPIO_Px_MODEL GPIO_Px_MODEH GPIO_Px_CTRL GPIO_Px_PINLOCKN GPIO_EXTIPSELL GPIO_EXTIPSELH GPIO_INSENSE and GPIO_ROUTE can be locked by writing any other value than 0xA534 to GPIO_LOCK Writing the value 0xA534 to the GPIOx_LOCK register unlocks the configuration registers In addition to configuration lock GPIO_Px_MODEL GPIO_Px_MODEH GPIO_Px_DOUT GPIO_Px_DOUTSET GPIO_Px_DOUTCLR and GPIO_Px_DOUTTGL ...

Page 761: ...61 Table 32 2 EM4 WU Register bits to pin mapping Wake up Registers Bits Pin bit 0 A0 bit 1 A6 bit 2 C9 bit 3 F1 bit 4 F2 bit 5 E13 32 3 3 EM4 Retention It is possible to enable retention of output enable output value pull enable and pull direction when in EM4 EM4 retention also makes it possible to wake up from EM4 on pin reset as described in Section 32 3 2 p 760 EM4 retention can be enabled by ...

Page 762: ...The Serial Wire Viewer Output pin SWO can be enabled by setting the SWOPEN bit in GPIO_ROUTE This bit can also be routed to alternate locations by configuring the LOCATION bitfield in GPIO_ROUTE 32 3 4 2 ETM Trace Ports There are five trace pins available on the device One trace clock which can be enabled by setting the TCLKPEN bitfield in GPIO_ROUTE The four data pins can be enabled individually ...

Page 763: ... C If EXT 3 in GPIO_IEN is set as well a interrupt request will be sent on IRQ_GPIO_ODD 32 3 6 Output to PRS All pins with the same pin number n are grouped together to form one PRS producer output giving a total of 16 outputs to the PRS The port on which the output n should be taken is selected by the EXTIPSELn 3 0 bits in the GPIO_EXTIPSELL or the GPIO_EXTIPSELH registers 32 3 7 Synchronization ...

Page 764: ... Data Out Toggle Register 0x040 GPIO_PB_DIN R Port Data In Register 0x044 GPIO_PB_PINLOCKN RW Port Unlocked Pins Register 0x048 GPIO_PC_CTRL RW Port Control Register 0x04C GPIO_PC_MODEL RW Port Pin Mode Low Register 0x050 GPIO_PC_MODEH RW Port Pin Mode High Register 0x054 GPIO_PC_DOUT RW Port Data Out Register 0x058 GPIO_PC_DOUTSET W1 Port Data Out Set Register 0x05C GPIO_PC_DOUTCLR W1 Port Data O...

Page 765: ...ster 0x100 GPIO_EXTIPSELL RW External Interrupt Port Select Low Register 0x104 GPIO_EXTIPSELH RW External Interrupt Port Select High Register 0x108 GPIO_EXTIRISE RW External Interrupt Rising Edge Trigger Register 0x10C GPIO_EXTIFALL RW External Interrupt Falling Edge Trigger Register 0x110 GPIO_IEN RW Interrupt Enable Register 0x114 GPIO_IF R Interrupt Flag Register 0x118 GPIO_IFS W1 Interrupt Fla...

Page 766: ...eration is equal to MODE0 23 20 MODE5 0x0 RW Pin 5 Mode Configure mode for pin 5 Enumeration is equal to MODE0 19 16 MODE4 0x0 RW Pin 4 Mode Configure mode for pin 4 Enumeration is equal to MODE0 15 12 MODE3 0x0 RW Pin 3 Mode Configure mode for pin 3 Enumeration is equal to MODE0 11 8 MODE2 0x0 RW Pin 2 Mode Configure mode for pin 2 Enumeration is equal to MODE0 7 4 MODE1 0x0 RW Pin 1 Mode Configu...

Page 767: ...umeration is equal to MODE8 15 12 MODE11 0x0 RW Pin 11 Mode Configure mode for pin 11 Enumeration is equal to MODE8 11 8 MODE10 0x0 RW Pin 10 Mode Configure mode for pin 10 Enumeration is equal to MODE8 7 4 MODE9 0x0 RW Pin 9 Mode Configure mode for pin 9 Enumeration is equal to MODE8 3 0 MODE8 0x0 RW Pin 8 Mode Configure mode for pin 8 Value Mode Description 0 DISABLED Input disabled Pullup if DO...

Page 768: ...put on port 32 5 5 GPIO_Px_DOUTSET Port Data Out Set Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name DOUTSET Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DOUTSET 0x0000 W1 Data Out Set Wr...

Page 769: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name DOUTTGL Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DOUTTGL 0x0000 W1 Data Out Toggle Write bits to 1 to toggle corresponding bits in GPIO_Px_DOUT Bits written to 0 will have no effect 32 5 8 GPIO_Px_DIN Port Data In Register ...

Page 770: ...cess Description 31 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 EXTIPSEL7 0x0 RW External Interrupt 7 Port Select Select input port for external interrupt 7 Value Mode Description 0 PORTA Port A pin 7 selected for external interrupt 7 1 PORTB Port B pin 7 selected for external interrupt 7 2 PORTC Port C pin 7 selected for ex...

Page 771: ...More information in Section 2 1 p 3 14 12 EXTIPSEL3 0x0 RW External Interrupt 3 Port Select Select input port for external interrupt 3 Value Mode Description 0 PORTA Port A pin 3 selected for external interrupt 3 1 PORTB Port B pin 3 selected for external interrupt 3 2 PORTC Port C pin 3 selected for external interrupt 3 3 PORTD Port D pin 3 selected for external interrupt 3 4 PORTE Port E pin 3 s...

Page 772: ...rved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 EXTIPSEL15 0x0 RW External Interrupt 15 Port Select Select input port for external interrupt 15 Value Mode Description 0 PORTA Port A pin 15 selected for external interrupt 15 1 PORTB Port B pin 15 selected for external interrupt 15 2 PORTC Port C pin 15 selected for external interrupt...

Page 773: ...PORTB Port B pin 11 selected for external interrupt 11 2 PORTC Port C pin 11 selected for external interrupt 11 3 PORTD Port D pin 11 selected for external interrupt 11 4 PORTE Port E pin 11 selected for external interrupt 11 5 PORTF Port F pin 11 selected for external interrupt 11 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10...

Page 774: ...11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name EXTIRISE Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 EXTIRISE 0x0000 RW External Interrupt n Rising Edge Trigger Enable Set bit n to enable triggering of external interrupt n on rising edge Value Description EXTIRISE n 0 Rising edge ...

Page 775: ...re compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 EXT 0x0000 RW External Interrupt n Enable Set bit n to enable external interrupt from pin n Value Description EXT n 0 Pin n external interrupt disabled EXT n 1 Pin n external interrupt enabled 32 5 15 GPIO_IF Interrupt Flag Register Offset Bit Position 0x114 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 776: ...5 0 EXT 0x0000 W1 External Interrupt Flag n Set Write bit n to 1 to set interrupt flag n Value Description EXT n 0 Pin n external interrupt flag unchanged EXT n 1 Pin n external interrupt flag set 32 5 17 GPIO_IFC Interrupt Flag Clear Register Offset Bit Position 0x11C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name EXT Bit Name Res...

Page 777: ...RW ETM Trace Data Pin Enable Enable ETM Trace Data Output 1 connection to pin 13 TD0PEN 0 RW ETM Trace Data Pin Enable Enable ETM Trace Data Output 0 connection to pin 12 TCLKPEN 0 RW ETM Trace Clock Pin Enable Enable ETM Trace Clock Output connection to pin 11 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 8 SWLOCATION 0x0 RW I...

Page 778: ...ure devices always write bits to 0 More information in Section 2 1 p 3 1 PRS 1 RW PRS Sense Enable Set this bit to enable input sensing for PRS 0 INT 1 RW Interrupt Sense Enable Set this bit to enable input sensing for interrupts 32 5 20 GPIO_LOCK Configuration Lock Register Offset Bit Position 0x128 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000...

Page 779: ...osition 0x130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name EM4WUCLR Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 EM4WUCLR 0 W1 EM4 Wake up clear Write 1 to clear all wake up requests 32 5 23 GPIO_EM4WUEN EM4 Wake up Enable Regis...

Page 780: ...always write bits to 0 More information in Section 2 1 p 3 5 0 EM4WUPOL 0x00 RW EM4 Wake up Polarity Write bit n to 1 for high wake up request Write bit n to 0 for low wake up request Value Mode Description 0x01 A0 Determines polarity on pin A0 0x02 A6 Determines polarity on pin A6 0x04 C9 Determines polarity on pin C9 0x08 F1 Determines polarity on pin F1 0x10 F2 Determines polarity on pin F2 0x2...

Page 781: ...cates an em4 wake up request occurred on pin A0 0x02 A6 This bit indicates an em4 wake up request occurred on pin A6 0x04 C9 This bit indicates an em4 wake up request occurred on pin C9 0x08 F1 This bit indicates an em4 wake up request occurred on pin F1 0x10 F2 This bit indicates an em4 wake up request occurred on pin F2 0x20 E13 This bit indicates an em4 wake up request occurred on pin E13 ...

Page 782: ...ice for battery driven systems with LCD panels 33 1 Introduction The LCD driver is capable of driving a segmented LCD display combination of 1x40 2x40 3x40 4x40 6x38 or 8x36 segments A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device In addition an animation feature can run custom animations on the LCD display without any CPU i...

Page 783: ...n be enabled or disabled individually to prevent the LCD driver from occupying more I O resources than required Figure 33 1 LCD Block Diagram LCD voltage generator VINT VEXT VBOOST VLC1 VLC0 VLC1 VLC0 Disable SEG out Disable COM out LCD_SEGx LCD_COMx VLCDSEL LCD control and status LCD segment data register LCD animation registers LCD sequence generator Contrast and bias setting Mux and framerate s...

Page 784: ...OM5 are used making 38 segments available located in SEG0 SEG19 and SEG22 SEG39 Finally when octaplex multiplexing is selected LCD_COM0 LCD_COM3 together with SEG20 SEG23 as LCD_COM4 LCD_COM7 are used making the 36 segments available located in SEG0 SEG19 and SEG24 SEG39 See Section 33 3 3 p 785 for waveforms for the different bias and multiplexing settings The waveforms generated by the LCD contr...

Page 785: ...2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End 33 3 3 Waveform Examples The numbers on the illustration s y axes in the following sections only indicate different voltage levels All examples are shown with low power waveforms 33 3 3 1 Waveforms with Static Bias and Multiplexing With static bias and multiplexing each segment line can be connected to LCD_COM0 When the segment line has the same ...

Page 786: ...re 33 6 LCD 1 2 Bias and Duplex Multiplexing LCD_COM1 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End 1 2 bias and duplex multiplexing LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the LCD_COM lines in order to turn on and off LCD pixels As illustrated in the figures below this waveform will turn ON pixels ...

Page 787: ...plexing LCD_SEG0 LCD_COM1 DC voltage 0 over one frame VRMS 0 35 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform Figure 33 10 LCD 1 2 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM1 VLC0 VLCD VLC3 VSS VLC0 VLCD Frame Start Frame End VLC1 1 2VLCD VLC1 1 2VLCD 33 3 3 3 Waveforms with 1 3 Bias and Duplex Multiplexing In this mode each frame is di...

Page 788: ...h the COM lines in order to turn on and off LCD pixels As illustrated in the figures below this waveform will turn ON pixels connected to LCD_COM0 while pixels connected to LCD_COM1 will be turned OFF Figure 33 13 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 VLC0 VLCD VLC3 VSS Frame Start Frame End VLC1 2 3VLCD VLC2 1 3VLCD Figure 33 14 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 Connection com...

Page 789: ...F with this waveform Figure 33 16 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM1 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 33 3 3 4 Waveforms with 1 2 Bias and Triplex Multiplexing In this mode each frame is divided into 6 periods LCD_COM 2 0 lines can be multiplexed with all segment lines Figures show 1 2 bias and triplex multip...

Page 790: ...es below this waveform will turn ON pixels connected to LCD_COM1 while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF Figure 33 20 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End Figure 33 21 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 Connection com1 com2 com0 seg0 1 2 bias and triplex multiplexing LCD_SEG0 LCD_COM0 DC voltage ...

Page 791: ...plexing LCD_SEG0 LCD_COM2 DC voltage 0 over one frame VRMS 0 4 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 33 24 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM2 VLC0 VLCD VLC3 VSS VLC0 VLCD VLC1 1 2VLCD VLC1 1 2VLCD Frame Start Frame End 33 3 3 5 Waveforms with 1 3 Bias and Triplex Multiplexing In this mode each frame is d...

Page 792: ...ment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels As illustrated in the figures below this waveform will turn ON pixels connected to LCD_COM1 while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF Figure 33 28 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 VLC0 VLCD VLC3 VSS VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End Figure 33 29 LCD 1 3 B...

Page 793: ... LCD_SEG0 LCD_COM1 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and triplex multiplexing LCD_SEG0 LCD_COM2 DC voltage 0 over one frame VRMS 0 33 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 33 32 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM2 VLC3 VSS VLC0 ...

Page 794: ...x Multiplexing LCD_COM2 VLC0 VLCD VLC1 2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End Figure 33 36 LCD 1 3 Bias and Quadruplex Multiplexing LCD_COM3 VLC0 VLCD VLC1 2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM li...

Page 795: ... quadruplex multiplexing LCD_SEG0 LCD_COM0 DC voltage 0 over one frame VRMS 0 58 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform Figure 33 39 LCD 1 3 Bias and Quadruplex Multiplexing LCD_SEG0 LCD_COM0 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD...

Page 796: ...ultiplexing LCD_SEG0 LCD_COM2 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD_SEG0 LCD_COM2 DC voltage 0 over one frame VRMS 0 33 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM3 will be OFF with this waveform Figure 33 42 LCD 1 3 Bias and Quadruplex Multiplexing LCD_SEG0 LCD_CO...

Page 797: ... Range 00 00000 11111 VLCD_OUT VLCD x 0 61 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 61VLCD CONLEV 31 VLCD_OUT VLCD 01 00000 11111 VLCD_OUT VLCD x 0 53 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 53VLCD CONLEV 31 VLCD_OUT VLCD 10 00000 11111 VLCD_OUT VLCD x 0 61 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 61VLCD CONLEV 31 VLCD_OUT VLCD 11 00000 11111 VLCD_OUT VLCD x 0 61 x 1 CONLEV 2 5 1 CONLEV 0 VLCD_OUT 0 61VLCD C...

Page 798: ...2 Rx VLCD_OUT VLCD R3 VLC4 VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD Rx VLCD_OUT R3 VLC4 VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD VLCD_OUT R3 VLC4 1 3 bias VLC0 VLC1 VLC2 VLC3 R0 R1 R2 Rx VLCD_OUT VLCD VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD Rx VLCD_OUT VLC0 VLC1 VLC2 VLC3 R0 R1 R2 VLCD VLCD_OUT 1 2 bias VLC0 VLC1 VLC3 VLCD R0 R1 Rx VLCD_OUT VLC0 VLC1 VLC3 VLCD R0 R1 Rx VLCD_OUT VLC0 VLC1 VLC3 VLCD R0 R1 VLCD_OUT Stat...

Page 799: ...e booster should be disabled Table 33 7 LCD VLCD VLCDSEL Mode VLCD 0 VDD VDD same as main external power 1 VBOOST Voltage booster External VDD 33 3 6 VBOOST Control The boost voltage is configurable By programming the VBLEV bits in LCD_DISPCTRL the boost voltage level can be adjusted between 3 0V and 3 6V The boost circuit will use an update frequency given by the VBFDIV bits in CMU_LCDCTRL see Ta...

Page 800: ...Max Min Max Min Max Static LFACLKLCD 2 128 1024 64 512 32 256 16 128 Duplex LFACLKLCD 4 64 512 32 256 16 128 8 64 Triplex LFACLKLCD 6 43 341 21 171 11 85 5 43 Quadruplex LFACLKLCD 8 32 256 16 128 8 64 4 32 Sextaplex LFACLKLCD 12 21 33 170 67 10 67 85 33 5 33 42 67 2 67 21 33 Octaplex LFACLKLCD 16 16 128 8 64 4 32 2 16 Table settings Min FDIV 7 Max FDIV 0 33 3 8 Data Update The LCD Driver logic tha...

Page 801: ...s bias levels can be set in SEGD0 SEGD3 while the COM line bias levels can be set in SEGD4 To represent the different bias levels 2 bits per SEG lines are needed For example SEG0 s bias levels can be set using SEGD0 1 0 and SEG1 can be controlled through SEGD0 3 2 etc Bias level encoding is shown in Table 33 11 p 801 Table 33 11 DSC BIAS Encoding SEGD Mode Bias setting 00 Static Static 2 levels 01...

Page 802: ...4Hz and the LCD event frequency should be set up to 2 seconds Example 33 1 LCD Event Frequency Example Write FCPRESC to 3 CLKFC 8Hz 0 125 seconds Write FCTOP to 15 CLKEVENT 0 5Hz 2 seconds If higher resolution is required configure a lower prescaler value and increase the FCPRESC in LCD_BACTRL accordingly e g FCPRESC 2 FCTOP 31 Figure 33 43 LCD Clock System in LCD Driver LFXO LFRCO Counter FDIV 2 ...

Page 803: ...6 states The shift operations applied to the shift registers are controlled by AREGASC and AREGBSC in LCD_BACTRL as shown in the table below Note also that the FC must be on for animation to work as it is the FC event that drives the animation state machine Table 33 13 LCD Animation Shift Register AREGnSC n A or B Mode Description 00 NOSHIFT No Shift operation 01 SHIFTLEFT Animation register is sh...

Page 804: ...0011000 00011000 7 00001100 00011000 00011100 8 00001100 00001100 00001100 9 00000110 00001100 00001110 10 00000110 00000110 00000110 11 00000011 00000110 00000111 12 00000011 00000011 00000011 13 10000001 00000011 10000011 14 10000001 10000001 10000001 15 11000000 10000001 11000001 In the table AREGASC 10 AREGBSC 10 ALOGSEL 1 and the resulting data is to be displayed on segment lines 7 0 or 15 8 ...

Page 805: ...tion State machine changes state In the interrupt handler read back the current state ASTATE Knowing the current state of the Animation State Machine makes it possible to calculate what data that is currently output Modify data as required Data will be updated at the next Frame Counter Event It is important that new data is written before the next Frame Counter Event 33 3 13 LCD in Low Energy Mode...

Page 806: ... LCD_SEGD1L RW Segment Data Low Register 1 0x048 LCD_SEGD2L RW Segment Data Low Register 2 0x04C LCD_SEGD3L RW Segment Data Low Register 3 0x050 LCD_SEGD0H RW Segment Data High Register 0 0x054 LCD_SEGD1H RW Segment Data High Register 1 0x058 LCD_SEGD2H RW Segment Data High Register 2 0x05C LCD_SEGD3H RW Segment Data High Register 3 0x060 LCD_FREEZE RW Freeze Register 0x064 LCD_SYNCBUSY R Synchron...

Page 807: ...e at the next event triggered by the Frame Counter 2 FRAMESTART The data transfer is done continuously at every LCD frame start 0 EN 0 RW LCD Enable When this bit is set the LCD driver is enabled and the driver will start outputting waveforms on the com segment lines 33 5 2 LCD_DISPCTRL Display Control Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 808: ...s write bits to 0 More information in Section 2 1 p 3 12 8 CONLEV 0x1F RW Contrast Level These bits control the contrast setting according to this formula VLCD_OUT VLCD 0 5 1 CONLEV 31 Value Mode Description 0 MIN Minimum contrast 31 MAX Maximum contrast 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 WAVE 0 RW Waveform Selectio...

Page 809: ...vidually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration 33 5 4 LCD_BACTRL Blink and Animation Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 0x0 0 0 0x0 0x0 0 0 0 Access RW ...

Page 810: ...egister B Value Mode Description 0 NOSHIFT No Shift operation on Animation Register B 1 SHIFTLEFT Animation Register B is shifted left 2 SHIFTRIGHT Animation Register B is shifted right 4 3 AREGASC 0x0 RW Animate Register A Shift Control These bits controls the shift operation that is performed on Animation register A Value Mode Description 0 NOSHIFT No Shift operation on Animation Register A 1 SH...

Page 811: ... 5 3 p 20 Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name AREGA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 AREGA 0x00 RW Animation Register A Data This register contains the A data for generating an...

Page 812: ...ion 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name FC Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 FC 0 W1 Frame Counter Interrupt Flag Set Write to 1 to set FC interrupt flag 33 5 10 LCD_IFC Interrupt Flag Clear Register Of...

Page 813: ...Frame Counter Interrupt Enable Set to enable interrupt on frame counter interrupt flag 33 5 12 LCD_SEGD0L Segment Data Low Register 0 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name SEGD0L Bit Name Reset Access Descr...

Page 814: ...nt lines 0 31 for COM1 33 5 14 LCD_SEGD2L Segment Data Low Register 2 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name SEGD2L Bit Name Reset Access Description 31 0 SEGD2L 0x00000000 RW COM2 Segment Data Low This regi...

Page 815: ...ters please see Section 5 3 p 20 Offset Bit Position 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name SEGD0H Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 SEGD0H 0x00 RW COM0 Segment Data High This register contains segmen...

Page 816: ...0x00 Access RW Name SEGD2H Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 SEGD2H 0x00 RW COM2 Segment Data High This register contains segment data for segment lines 32 39 for COM2 33 5 19 LCD_SEGD3H Segment Data High Register 3 Async Reg For more information about Asynchronous Registers ple...

Page 817: ...6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R R R R R R R R R R R R R R R R R R R R Name SEGD7L SEGD6L SEGD5L SEGD4L SEGD7H SEGD6H SEGD5H SEGD4H SEGD3H SEGD2H SEGD1H SEGD0H SEGD3L SEGD2L SEGD1L SEGD0L AREGB AREGA BACTRL CTRL Bit Name Reset Access Description 31 20 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 ...

Page 818: ...SEGD0L is being synchronized 3 AREGB 0 R AREGB Register Busy Set when the value written to AREGB is being synchronized 2 AREGA 0 R AREGA Register Busy Set when the value written to AREGA is being synchronized 1 BACTRL 0 R BACTRL Register Busy Set when the value written to BACTRL is being synchronized 0 CTRL 0 R CTRL Register Busy Set when the value written to CTRL is being synchronized 33 5 22 LCD...

Page 819: ... 5 3 p 20 Offset Bit Position 0x0BC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name SEGD6H Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 SEGD6H 0x00 RW COM2 Segment Data High This register contains segment data for segment line...

Page 820: ...s RW Name SEGD4L Bit Name Reset Access Description 31 0 SEGD4L 0x00000000 RW COM4 Segment Data This register contains segment data for segment lines 0 23 for COM4 33 5 27 LCD_SEGD5L Segment Data Low Register 5 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x0D0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 ...

Page 821: ...0 RW COM6 Segment Data This register contains segment data for segment lines 0 23 for COM6 33 5 29 LCD_SEGD7L Segment Data Low Register 7 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x0D8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name SEGD7L Bit Name Reset Access D...

Page 822: ...the DMA Controller section Updated EMU Backup power domain section Updated the register description of LEUARTn_CTRL Corrected the DAC fsine equation Added and modified notes in the WDOG Clock Source and Register Access sections Modified a note in the PCNT Clock Sources section Updated the register description of MSC_WDATA Updated the register description of LESENSE_BIASCTRL Updated the register de...

Page 823: ...w register access type RW1H Updated RMU Reset Cause Register Interpretation table Updated the register description of CMU_CTRL Updated CMU_CALCNT description Updated DMA_CHENC register description Updated description of number of wait states for Immediate Synchronization Updated description of the Excite Phase timing in LESENSE Updated the LETIMER PRS description Updated OPAMP description Updated ...

Page 824: ... location to CMU_ROUTE register Corrected number of locations in ROUTE register for PRS Corrected description of the SHIFTDCLKEN and DCLKPERIOD bitfields of the EBI Added note on changed timing setting defaults of the EBI Corrected description of the EBI page mode read operation for D16A16ALE addressing mode Improved explanation of EBI bus turn around and idle cycles Corrected RMU Reset Cause Regi...

Page 825: ... the world s most energy friendly microcontrollers 2016 04 28 Giant Gecko Family d0053_Rev1 20 825 www silabs com Initial preliminary revision ...

Page 826: ...AUXHFRCO Auxiliary High Frequency RC Oscillator CC Compare Capture CLK Clock CMD Command CMU Clock Management Unit CTRL Control DAC Digital to Analog Converter DBG Debug DMA Direct Memory Access DRD Dual Role Device DTI Dead Time Insertion EBI External Bus Interface EFM Energy Friendly Microcontroller EM Energy Mode EM0 Energy Mode 0 also called active mode EM1 to EM4 Energy Mode 1 to Energy Mode ...

Page 827: ...lifier OSR Oversampling Ratio OTG On the go PCNT Pulse Counter PGA Programmable Gain Array PHY Physical Layer PRS Peripheral Reflex System PSRR Power Supply Rejection Ratio PWM Pulse Width Modulation RC Resistance and Capacitance RMU Reset Management Unit RTC Real Time Clock SAR Successive Approximation Register SOF Start of Frame SPI Serial Peripheral Interface SW Software THD Total Harmonic Dist...

Page 828: ...r to design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are gen...

Page 829: ...53_Rev1 20 829 www silabs com C Contact Information Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 Please visit the Silicon Labs Technical Support web page http www silabs com support pages contacttechnicalsupport aspx and register to submit a technical support request ...

Page 830: ...6 6 5 Register Map 28 6 6 Register Description 28 7 MSC Memory System Controller 30 7 1 Introduction 30 7 2 Features 31 7 3 Functional Description 31 7 4 Register Map 38 7 5 Register Description 38 8 DMA DMA Controller 48 8 1 Introduction 48 8 2 Features 48 8 3 Block Diagram 49 8 4 Functional Description 50 8 5 Examples 70 8 6 Register Map 71 8 7 Register Description 72 9 RMU Reset Management Unit...

Page 831: ...mitter 495 18 1 Introduction 495 18 2 Features 495 18 3 Functional Description 496 18 4 Register Description 496 18 5 Register Map 496 19 LEUART Low Energy Universal Asynchronous Receiver Transmitter 497 19 1 Introduction 497 19 2 Features 497 19 3 Functional Description 498 19 4 Register Map 509 19 5 Register Description 509 20 TIMER Timer Counter 523 20 1 Introduction 523 20 2 Features 523 20 3 ...

Page 832: ... Register Description 718 30 OPAMP Operational Amplifier 733 30 1 Introduction 733 30 2 Features 733 30 3 Functional Description 734 30 4 Register Description 743 30 5 Register Map 743 31 AES Advanced Encryption Standard Accelerator 744 31 1 Introduction 744 31 2 Features 744 31 3 Functional Description 744 31 4 Register Map 748 31 5 Register Description 748 32 GPIO General Purpose Input Output 75...

Page 833: ...EBI Overview 177 14 2 EBI Non multiplexed 8 bit Data 8 bit Address Read Operation 178 14 3 EBI Non multiplexed 8 bit Data 8 bit Address Write Operation 178 14 4 EBI Address Latch Setup 179 14 5 EBI Multiplexed 16 bit Data 16 bit Address Read Operation 179 14 6 EBI Multiplexed 16 bit Data 16 bit Address Write Operation 179 14 7 EBI Multiplexed 8 bit Data 24 bit Address Read Operation 180 14 8 EBI M...

Page 834: ... Two Stage Control Transfer 294 15 21 Receive FIFO Packet Read in Slave Mode 295 15 22 Slave Mode Bulk OUT Transaction 299 15 23 ISOC OUT Application Flow for Periodic Transfer Interrupt Feature 304 15 24 Isochronous OUT Core Internal Flow for Periodic Transfer Interrupt Feature 305 15 25 Bulk IN Stall 309 15 26 USBTRDTIM Max Timing Case ERROR wrong image 312 15 27 Slave Mode Bulk IN Transaction 3...

Page 835: ...t Frequency Generation 534 20 18 TIMER Up count PWM Generation 534 20 19 TIMER CC out in 2x mode 535 20 20 TIMER Up Down count PWM Generation 536 20 21 TIMER CC out in 2x mode 536 20 22 TIMER Dead Time Insertion Unit Overview 537 20 23 TIMER Triple Half Bridge 537 20 24 TIMER Overview of Dead Time Insertion Block for a Single PWM channel 538 20 25 TIMER Polarity of Both Signals are Set as Active H...

Page 836: ...ltiplexing LCD_SEG0 LCD_COM1 787 33 11 LCD 1 3 Bias and Duplex Multiplexing LCD_COM0 787 33 12 LCD 1 3 Bias and Duplex Multiplexing LCD_COM1 788 33 13 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 788 33 14 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 Connection 788 33 15 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM0 789 33 16 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM1 789 33...

Page 837: ... the world s most energy friendly microcontrollers 2016 04 28 Giant Gecko Family d0053_Rev1 20 837 www silabs com 33 44 LCD Block Diagram of the Animation Circuit 804 ...

Page 838: ...oducers 166 13 2 Reflex Consumers 167 14 1 EBI Intrapage hit condition for read on address Addr non mentioned Addr bits are unchanged 182 14 2 EBI Enabling EBI_ADDR lines for transaction with address Addr and data Data 185 14 3 EBI Mapping of AHB Transactions to External Device Transactions 188 14 4 EBI NAND Flash Register Select 193 14 5 EBI NAND Flash Write Timing 195 14 6 EBI NAND Flash Read Ti...

Page 839: ...0 3 Inverting input PGA Configuration 738 30 4 Non inverting PGA Configuration 738 30 5 Cascaded Inverting PGA Configuration 739 30 6 Cascaded Non inverting PGA Configuration 740 30 7 OPA0 OPA1 Differential Amplifier Configuration 741 30 8 OPA1 OPA2 Differential Amplifier Configuration 741 30 9 Three Opamp Differential Amplifier Gain Programming 742 30 10 Three Opamp Differential Amplifier Configu...

Page 840: ...463 20 1 TIMER DTI Example 1 539 20 2 TIMER DTI Example 2 539 23 1 LETIMER Triggered Output Generation 595 23 2 LETIMER Continuous Output Generation 596 23 3 LETIMER PWM Output 597 23 4 LETIMER PWM Output 597 31 1 AES Cipher Block Chaining 747 32 1 GPIO Interrupt Example 763 33 1 LCD Event Frequency Example 802 33 2 LCD Animation Enable Example 805 33 3 LCD Animation Dependence Example 805 ...

Page 841: ...TIMER Rotational Position Equation 529 20 2 TIMER Up count Frequency Generation Equation 534 20 3 TIMER Up count PWM Resolution Equation 534 20 4 TIMER Up count PWM Frequency Equation 534 20 5 TIMER Up count Duty Cycle Equation 535 20 6 TIMER 2x PWM Resolution Equation 535 20 7 TIMER 2x Mode PWM Frequency Equation Up count 535 20 8 TIMER 2x Mode Duty Cycle Equation 535 20 9 TIMER Up Down count PWM...

Page 842: ......

Page 843: ...CNCD DM160216 MPC5777M 416DS EV ADUCM350GPIOTHZ EV ADUCM350 BIO3Z ATSTK521 1130 MA160015 MA180033 MA240013 MA240026 MA320014 MA330014 MA330017 TLK10034SMAEVM TMDSCNCD28054MISO MIKROE 2152 MIKROE 2154 MIKROE 2381 TSSOP20EV DEV 11723 MIKROE 1108 MIKROE 1516 SPS READER GEVK AC244049 AC244050 AC320004 3 2077 ATSMARTCARD XPRO EIC Q600 230 ATZB 212B XPRO SPC560PADPT100S SPC560BADPT64S MA180018 EIC Q600 ...