...the world's most energy friendly microcontrollers
2016-04-28 - Giant Gecko Family - d0053_Rev1.20
42
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7.5.6 MSC_WDATA - Write Data Register
Offset
Bit Position
0x018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0x00000000
Access
RW
Name
WDATA
Bit
Name
Reset
Access
Description
31:0
WDATA
0x00000000
RW
Write Data
The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS
is set. This register is not retained when entering EM2 or lower energy modes.
7.5.7 MSC_STATUS - Status Register
Offset
Bit Position
0x01C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
1
0
0
0
Access
R
R
R
R
R
R
R
Name
PCRUNNING
ERASEABORTED
WORDTIMEOUT
WDATAREADY
INVADDR
LOCKED
BUSY
Bit
Name
Reset
Access
Description
31:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6
PCRUNNING
0
R
Performance Counters Running
This bit is set while the performance counters are running. When one performance counter reaches the maximum value, this bit
is cleared.
5
ERASEABORTED
0
R
The Current Flash Erase Operation Aborted
When set, the current erase operation was aborted by interrupt.
4
WORDTIMEOUT
0
R
Flash Write Word Timeout
When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the
flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands in
MSC_WRITECMD are triggered.
3
WDATAREADY
1
R
WDATA Write Ready
When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the
next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.
2
INVADDR
0
R
Invalid Write Address or Erase Page
Set when software attempts to load an invalid (unmapped) address into ADDR.
1
LOCKED
0
R
Access Locked
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