Si2401
18
Preliminary Rev. 0.9
This allows a modem that is transmitting at 75 bps to
initiate a “turnaround” procedure so that it can begin
transmitting data at 1200/600 bps and receiving data at
75 bps. The modem is defined as being in V.23 master
mode if it is transmitting at 75 bps, and it is defined as
being in slave mode if the modem is transmitting at
1200/600 bps. The following paragraphs give a detailed
description of the V.23 turnaround procedure.
Modem in Master Mode
To perform a direct turnaround once a modem
connection is established, the master host goes into
online-command-mode by sending an escape
command (Escape pin activation, TIES, or ninth bit
escape) to the master modem.
Note:
The host can initiate a turnaround only if the Si2401 is
the master.
The host then sends the ATRO command to the Si2401
to initiate a V.23 turnaround and return to the online
(data) mode.
The Si2401 then changes its carrier frequency (from
390 Hz to 1300 Hz) and wait to detect a 390 Hz carrier
for 440 ms. If the modem detects more than 40 ms of a
390 Hz carrier in a time window of 440 ms, it echoes the
“c” response character. If the modem does not detect
more than 40 ms of a 390 Hz carrier in a time window of
440 ms, it hangs up and echoes the “N” (no carrier)
character as a response.
Modem in Slave Mode
Configure GPIO4 as INT (SE2[7:6] [GPIO4] = 11). The
Si2401 performs a reverse turnaround when it detects a
carrier drop longer than 20 ms. The Si2401 then
reverses (changes its carrier from 1300 Hz to 390 Hz)
and waits to detect a 1300 Hz carrier for 400 ms. If the
Si2401 detects more than 40 ms of a 1300 Hz carrier in
a time window of 400 ms, it sets the S09[7] bit, and the
next character echoed by the Si2401 is a “v”.
If the Si2401 does not detect more than 40 ms of the
1300 Hz carrier in a time window of 400 ms, it reverses
again and waits to detect a 390 Hz carrier for 440 ms.
Then, if the Si2401 detects more than 40 ms of a
390 Hz carrier in a time window of 220 ms, it sets the
S09[7] bit, and the next character echoed by the Si2401
is a “c”.
At this point, if the Si2401 does not detect more than
40 ms of the 390 Hz carrier in a time window of 440 ms,
it hangs up, sets the S09[7] bit, and the next character
echoed by the Si2401 is an “N” (no carrier).
Successful completion of a turnaround procedure in
master or slave mode automatically updates
S07[4] (V23T) and S07[5] (V23R) to indicate the new
status of the V.23 connection.
To avoid using the INT pin, the host may also be notified
of the INT condition by using 9-bit data mode. Setting
S15[0] (NBE) = 1 and S0C[3] (9BF) = 0
b
configures the
ninth bit on the Si2401 TXD path to function exactly as
the INT pin has been described.
V.42 HDLC Mode
The Si2401 supports V.42 through hardware HDLC
framing in all modem data modes. Frame packing and
unpacking including opening and closing flag generation
and detection, CRC computation and checking, zero
insertion and deletion, and modem data transmission
and reception are all performed by the Si2401. V.42
error correction and V.42bis data compression must be
performed by the host.
The digital link interface in this mode uses the same
UART interface (8-bit data and 9-bit data formats) as in
the asynchronous modes, and the ninth data bit may be
used as an escape by setting S15[0] (NBE) = 1. When
using HDLC in 9-bit data mode, if the ninth bit is not
used as an escape, it is ignored.
To use the HDLC feature on the Si2401, the host must
enable HDLC operation by setting S13[1] (HDEN) = 1.
The host may initiate the call or answer the call using
either the “ATDT#”, the “ATA” command or the auto-
answer mode. (The auto-answer mode is implemented
by setting register S00 (NR) to a non-zero value.) When
the call is connected, a “c”, “d”, or a “v” is echoed to the
host controller. The host may now send/receive data
across the UART using either the 8-bit data or 9-bit data
formats with flow control.
At this point, the Si2401 begins framing data into the
HDLC format. On the transmit side, if no data is
available from the host, the HDLC flag pattern is sent
repeatedly. When data is available, the Si2401
computes the CRC code throughout the frame, and the
data is sent with the HDLC zero-bit insertion algorithm.
HDLC flow control operates in a similar manner to
normal asynchronous flow control across the UART and
is shown in Figure 4. To operate flow control (using the
CTS pin to indicate when the Si2401 is ready to accept
a character), a DTE rate higher than the line rate should
be selected. The method of transmitting HDLC frames
is as follows:
1. After the call is connected, the host should begin sending
the frame data to the Si2401 using the CTS flow control to
ensure data synchronicity.
2. When the frame is complete, the host should simply stop
sending data to the Si2401. Since the Si2401 does not yet
recognize the end-of-frame, it expects an extra byte and
assert CTS as shown in Figure 4A. If CTS is used to cause
a host interrupt, this final interrupt should be ignored by the
host.
3. When the Si2401 is ready to send the next byte, if it has
