Silicon Laboratories ISOMODEM Si2401, Manual

Page 1: ...ze low external component count and low power consumption Functional Block Diagram Data modem formats z 2400 bps V 22bis z 1200 bps V 22 V 23 Bell 212A z 300 bps V 21 Bell 103 z Fast connect and V 23...

Page 2: ...Si2401 2 Preliminary Rev 0 9...

Page 3: ...pt Detection 17 V 23 Operation V 23 Reversing 17 V 42 HDLC Mode 18 Fast Connect 20 Clock Generation Subsystem 20 AT Command Set 21 Command Line Execution 21 CR End Of Line Character 21 AT Command Set...

Page 4: ...en the typical application circuit including component tolerance and Si2401 and Si3010 are used See Typical Application Schematic on page 10 2 All minimum and maximum specifications are guaranteed and...

Page 5: ...ILIM 1 DCV 11 MINI 00 DCR 0 7 5 V DC Termination Voltage VTR IL 60 mA ILIM 1 DCV 11 MINI 00 DCR 0 40 V DC Termination Voltage VTR IL 50 mA ILIM 1 DCV 11 MINI 00 DCR 0 40 V On Hook Leakage Current ILK...

Page 6: ...A 2 4 V Low Level Output Voltage VOL IO 1 mA 0 35 V Low Level Output Voltage GPIO1 4 VOL IO 10 mA 0 6 V Input Leakage Current IL 10 10 A Pullup Resistance Pins 5 7 11 14 RPU 50 100 200 k Power Supply...

Page 7: ...100 mA 80 dB Dynamic Range3 DR ILIM 0 DCV 00 MINI 11 DCR 0 IL 20 mA 80 dB Dynamic Range3 DR ILIM 1 DCV 11 MINI 00 DCR 0 IL 50 mA 80 dB Transmit Total Harmonic Distortion4 THD ILIM 0 DCV 11 MINI 00 DC...

Page 8: ...put Voltage VXIND 0 3 to VD 0 3 V Operating Temperature Range TA 10 to 100 C Storage Temperature Range TSTG 40 to 150 C Note Permanent device damage may occur if the above absolute maximum ratings are...

Page 9: ...iming is referenced to the 50 level of the waveform Input test levels are VIH 2 0 V VIL 0 8 V Note Baud rates programmed through register SE0 are as follows 300 1200 2400 9600 19200 38400 115200 and 3...

Page 10: ...t layout to Silicon Labs for review prior to PCB fabrication R3 RV1 C41 FB1 C9 R7 R8 C5 U6 Si2401 XTALI CLKIN 1 XTALO 2 GPIO5 3 VD 4 RXD 5 TXD 6 CTS 7 RESET 8 C2A 9 C1A 10 GPIO4 11 GND 12 VA 13 GPIO3...

Page 11: ...sonic R5 R6 100 k 1 16 W 5 Venkel SMEC Panasonic R7 R8 20 M 1 16 W 5 Venkel SMEC Panasonic R9 1 M 1 16 W 1 Venkel SMEC Panasonic R10 536 1 4 W 1 Venkel SMEC Panasonic R11 73 2 1 2 W 1 Venkel SMEC Pana...

Page 12: ...erfaces directly through a UART to a microcontroller The Si2401URT EVB evaluation board connects directly to a standard RS 232 interface This allows for evaluation of the modem immediately upon poweru...

Page 13: ...some of the modem configurations As shown in Figure 3 8 bit and 9 bit data modes refer to the DTE format over the UART Line data formats are configured through registers S07 MF1 and S15 MLC If the num...

Page 14: ...e Si2401 on TXD beginning with a start bit LSB first at the DTE rate determined by the SE0 2 0 setting and terminates with a stop bit After the middle of the stop bit time the Si2401 begins looking fo...

Page 15: ...r Settings Register SF5 SF6 Country OHS ILIM RZ RT MINI 1 0 DCV 1 0 ACT 3 0 Australia 10 0 0 0 0 0 00 0011 Brazil1 00 0 0 0 00 00 0000 TBR212 00 1 0 0 11 11 0011 Czech Republic 00 0 0 0 11 11 0011 FCC...

Page 16: ...1 1 mA per bit An LCS register value of 0x00 indicates less than the required loop current is present and a value of 0xFF indicates excessive current draw 120 mA if ILIM 0 or 60 mA if ILIM 1 The user...

Page 17: ...mmable time set by S32 OCDT after going off hook default 20 ms If an overcurrent condition is detected the Si2401 sets S09 1 interrupt status As long as GPIO4 is programmed as INT and the overcurrent...

Page 18: ...e V 23 connection To avoid using the INT pin the host may also be notified of the INT condition by using 9 bit data mode Setting S15 0 NBE 1 and S0C 3 9BF 0b configures the ninth bit on the Si2401 TXD...

Page 19: ...um does not match the Si2401 echoes e error Additionally if the Si2401 detects an abort seven or more contiguous ones it echoes an A When the G e or A referred to as a frame result word is sent the Si...

Page 20: ...the master clock for the Si2401 This clock source is sent to an internal phase locked loop PLL that generates all necessary internal system clocks The PLL has a settling time of 1 ms Data on RXD shoul...

Page 21: ...figuration exists after the connection or connection attempt has ended Configuration commands change modem characteristics until they are modified or reversed by a subsequent configuration command or...

Page 22: ...modem does not have to dial i e ATDT CR or ATDP CR with no dial string the Si2401 assumes the call was manually established and attempts to make a connection Automatic Tone Pulse Dialing The Si2401 ca...

Page 23: ...rst byte following the w is the address in binary format and the second byte is the data in binary format This is a more rapid method to write registers than the SR N command and is recommended for us...

Page 24: ...als the phone number and echoes r ring b busy and c connect as appropriate c echoes only after the Si2401 detects the Handshake Tone After a 250 ms delay the modem sends the DTMF tones containing the...

Page 25: ...TX3 command to reverse data direction This sequence can be repeated for long messages Modem Result Codes and Call Progress Table 14 shows the modem result codes that can be used in call progress monit...

Page 26: ...his requires the host to read and write the low level DSP registers and may require realtime control by the host Manual call progress may be required for detection of application specific ringback dia...

Page 27: ...in 0x07 0x03 0x01 0x25 0x25 0x04 Greece 0x12 0x4B 0x08 0x1E 0x1E 0x03 Hong Kong New Zealand 0x07 0x03 0x01 0x32 0x32 0x05 Hungary 0x17 0x46 0x0F 0x1E 0x1E 0x03 Iceland 0x16 0x58 0x09 0x19 0x19 0x03 In...

Page 28: ...ction is reported in SE5 SE8 0x2 as explained above The output is priority encoded such that if multiple tones are detected the one with the highest priority whose detection is also enabled is reporte...

Page 29: ...ses and data are written in hexadecimal To write a value to a DSP register the register address is written and then the data is written When SE8 0x00 SE5 DADL is written with the low bits 7 0 of the D...

Page 30: ...quency for detector 2 UDFD2 8192 cos 2 f 9600 536 0x0009 UDFD3 User defined frequency detector 3 Center frequency for detector 3 UDFD3 8192 cos 2 f 9600 4987 0x000A UDFD4 User defined frequency detect...

Page 31: ...ed by selecting SE6 7 CPSQ 1 Figure 5 shows a block diagram of the call progress filter structure Table 19 SE5 SE6 and SE8 Relationship SE8 SE6 SE5 R W Name Description Name Description 0x00 W DADH DS...

Page 32: ...y Rev 0 9 Figure 5 Programmable Call Progress Filter Architecture Filter B Energy Detect 1 0 1 0 1 0 Filter B Filter Input y x2 CPSQ Energy Detect 0 CPCD Max A B Hysteresis A B 20log10 4096 CPDL 43 dB...

Page 33: ...ok time 5 3 ms units for pulse dialing 0x24 S07 0x07 MF1 This is a bit mapped register 0x06 S08 0x08 INTM This is a bit mapped register 0x00 S09 0x09 INTS This is a bit mapped register 0x00 S0C 0x0C M...

Page 34: ...nsmit scrambled ones delay Time between unscrambled binary one detection and scrambled binary one transmission by a call mode V 22 modem 53 3 ms units 0x09 S22 0x22 TSOL Transmit scrambled ones length...

Page 35: ...23 reverse turnaround carrier timeout Amount of time a slave mode V 23 modem searches for carriers during potential reverse turnaround sequences 5 3 ms units 0xF0 S2F 0x2F FCD FSK connection delay low...

Page 36: ...R This is a bit mapped register 0x0C SE0 0xE0 CF1 This is a bit mapped register 0x22 SE1 0xE1 GPIO1 This is a bit mapped register 0x04 SE2 0xE2 GPIO2 This is a bit mapped register 0x00 SE3 0xE3 GPD Th...

Page 37: ...ue returning the loop current Each bit represents 1 1 mA of loop current Accuracy is not guaranteed if the loop current is less than required for normal operation 0x00 SF4 0xF4 DAA4 This is a bit mapp...

Page 38: ...100 S3C 0x3C CIDG CIDG 2 0 0000_0100 S62 0x62 RC OCR IR NLR RR 0100_0001 S82 0x82 IST IST 3 0 LCLD IB 1 0 0000_1000 SDF 0xDF DGSR DGSR 6 0 0000_1100 SE0 0xE0 CF1 ICTS ND SD 2 0 0010_0010 SE1 0xE1 GPIO...

Page 39: ...0000_1000 SF6 0xF6 DAA6 MINI 1 0 DCV 1 0 ACT 3 0 1111_0000 SF8 0xF8 DAA8 LRV 3 0 DCR SF9 0xF9 DAA9 BTD ROV 0010_0000 SFC 0xFC DAAFC CTSM 0000_1111 Table 22 Bit Mapped Register Summary Continued S Regi...

Page 40: ...command 5 V23R V 23 Receive V 23 75 bps send 600 BAUD 0 or 1200 BAUD 1 bps receive 0 Disable 1 Enable 4 V23T V 23 Transmit V 23 600 BAUD 0 or 1200 BAUD 1 bps send 75 bps receive 0 Disable 1 Enable 3...

Page 41: ...k 0 Change in PPD does not affect INT 1 A low to high transition in PPD S09 bit 5 activates INT 4 NVDM No Phone Line Detect Mask 0 Change in NLD does not affect INT 1 A low to high transition in NLD S...

Page 42: ...ars on I read 5 PPD Parallel Phone Detect sticky Parallel phone detected since last off hook event Clears on I read 4 NVD No Phone Line Detect sticky No line phone detected Clears on I read 3 RI Ring...

Page 43: ...seizure signal followed by marks in order to report caller ID data Normal Bellcore caller ID 10 Reserved 11 Caller ID monitor enabled Si2401 must only detect marks in order to report caller ID data 4...

Page 44: ...n interrupt forces pin 11 low 1 An interrupt forces pin 11 high 4 RBTS Ringback Tone Selector Controls the unit step size for registers S19 S1A and S1B 0 53 33 ms units Necessary for detecting a ringb...

Page 45: ...nits S13 MF3 Modem Functions 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name BTID OFHD CIDB HDEN Type R W R W R W R W R W Bit Name Function 7 Reserved Read returns zero 6 BTID BT Caller ID Wetting Pulse 0 Enable 1...

Page 46: ...Disable 1 Enable answer tone phase reversal 6 VCTE V 25 Calling Tone 0 Disable 1 Enable V 25 calling tone 5 FHGE 550 Hz Guardtone 0 Disable 1 Enable 550 Hz guardtone 4 EHGE 1800 Hz Guardtone 0 Disabl...

Page 47: ...0 Type R W Bit Name Function 7 3 Reserved Read returns 0 2 0 CIDG 2 0 Caller ID Gain The Si2400 dynamically sets the On Hook Analog Receive Gain SF4 6 4 ARG to CIDG during a caller ID event or continu...

Page 48: ...OCR IR NLR RR Type R W R W R W R W Bit Name Function 7 Reserved Read returns zero 6 OCR Overcurrent Result Code x 0 Enable 1 Disable 5 3 Reserved Read returns zero 2 IR Intrusion Result Code I and i...

Page 49: ...s Detect 0 Disable 1 Enables the reporting of I and L result codes while off hook Asserts INT if GPIO4 SE2 7 6 is enabled as INT 2 1 IB 1 0 Intrusion Blocking This feature only works when SDF 0x00 Def...

Page 50: ...and sets the off hook intrusion sample rate to 200 ms and delay between compared samples to 800 ms SE0 CF1 Chip Functions 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ICTS ND SD 2 0 Type R W R W R W Bit Name F...

Page 51: ...D4 D3 D2 D1 D0 Name GPIO4 1 0 GPIO3 1 0 GPIO2 1 0 GPIO1 1 0 Type R W R W R W R W Bit Name Function 7 6 GPIO4 1 0 GPIO4 00 Digital input 01 Digital output relay drive 10 AOUT 11 INT function defined by...

Page 52: ...2 Data Data 0 Data 1 0 GPD1 GPIO1 Data Data 0 Data 1 SE4 CF5 Chip Functions 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name NBCK SBCK DRT GPE Type R R R W R W Bit Name Function 7 NBCK 9600 Baud Clock Read Only 6 S...

Page 53: ...ing TONE Tone Type Priority 00000 01111 DTMF 0 15 DTMFE 1 1 See Table 17 on page 28 1 10000 Answer tone detected 2100 Hz ANSE 1 2 2 10001 Bell 103 answer tone detected 2225 Hz ANSE 1 2 10010 V 23 forw...

Page 54: ...it when selected by TONC 001 See Table 17 on page 28 2 0 TONC 2 0 DTMF Tone Selector Tone Tone Type 000 Mute 001 DTMF 010 2225 Hz Bell mode answer tone with phase reversal 011 2100 Hz CCITT mode answe...

Page 55: ...r A is used in the detector 1 Cascade disabled Two independent fourth order filters available A and B The largest output of the two is used in the detector 5 Reserved 4 USEN2 User Tone Reporting Enabl...

Page 56: ...et settings 0000_0000 0x00 SEB TPD Timer and Powerdown Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PDDE Type R W Bit Name Function 7 4 Reserved Read returns zero 3 PDDE Powerdown DSP Engine 0 Power on 1 Powerdow...

Page 57: ...y These bits set the amount of time between when a ring signal is validated and when a valid ring signal is indicated RDLY 2 0 Delay 000 0 ms 001 256 ms 010 512 ms 111 1792 ms 3 1 RCC 2 0 Ring Confirm...

Page 58: ...rements at a reg ular rate If a second or subsequent TIP RING event occurs after the timer has timed out the frequency of the ring is too low and the ring is invalidated The difference between RAS 5 0...

Page 59: ...oaded with the RAS 5 0 field upon a TIP RING event and decrements at a reg ular rate When a subsequent TIP RING event occurs the timer value is compared to the RMX 3 0 field and if it exceeds the valu...

Page 60: ...lection These bits determine the length of the off hook counter The default setting is 128 ms 00 512 ms 01 128 ms 10 64 ms 11 8 ms 5 2 Reserved Read returns zero 1 0 LM 1 0 Line Mode These bits determ...

Page 61: ...5 PDL Powerdown Line Side Chip typically only used for board level debug 0 Normal operation Program the clock generator before clearing this bit 1 Places the line side device in lower power mode 4 LV...

Page 62: ...on capacitor frame lock has been established 0 Indicates isolation capacitor frame lock has not been established 2 0 Reserved Reserved SF4 DAA4 DAA Low Level Functions 4 Bit D7 D6 D5 D4 D3 D2 D1 D0 Na...

Page 63: ...X 20 ms 10 Meets Australian spark quenching spec 3 ILIM Current Limiting Enable 0 Current limiting mode disabled 1 Current limiting mode enabled This mode limits loop current to a maximum of 60 mA per...

Page 64: ...e side device which affects the TIP RING voltage on the line Low voltage countries should use a lower TIP RING volt age Raising the TIP RING voltage can improve signal headroom DCV 1 0 DCT Pin Voltage...

Page 65: ...1 DCR DC Impedance Selection 0 50 dc termination is selected This mode should be used for all standard applications 1 800 dc termination is selected 0 Reserved Do not modify SF9 DAA9 DAA Low Level Fun...

Page 66: ...D5 D4 D3 D2 D1 D0 Name CTSM Type R W Bit Name Function 7 CTSM Clear to Send CTS Mode 0 CTS pin is negated as soon as a start bit is detected and reasserted when the transmit FIFO is empty 1 CTS pin is...

Page 67: ...f a ring signal on the telephone line 4 VD Supply Voltage Provides the 3 3 V supply voltage to the Si2401 5 RXD Receive Data Serial communication data from the Si2401 6 TXD Transmit Data Serial commun...

Page 68: ...Voltage Reference This pin connects to an external capacitor and serves as the reference for the internal voltage regulator 14 GPIO3 ESC General Purpose Input Escape This pin can be either a GPIO pin...

Page 69: ...ng 1 Connects through a capacitor to the RING lead of the telephone line Provides the ring and caller ID signals to the Si2401 9 RNG2 Ring 2 Connects through a capacitor to the TIP lead of the telepho...

Page 70: ...Si2401 70 Preliminary Rev 0 9 Ordering Guide Chipset Region Power Supply Digital Line Temperature Si2401 Global 3 3 V Si2401 FS Si3010 FS 0 to 70 C...

Page 71: ...6 16 pin Small Outline Integrated Circuit SOIC Package Table 24 Package Diagram Dimensions Symbol Millimeters Typical Min Max A 1 35 1 75 3 A1 10 25 3 A2 1 30 1 50 B 33 51 C 19 25 3 D 9 80 10 01 E 3 8...

Page 72: ...ated Bill of Materials Si2401 10 Chipset on page 11 Updated SF3 description in Table 21 S Register Summary on page 33 Updated SE4 description in Register SE4 CF5 Chip Functions 5 on page 52 Updated Pi...

Page 73: ...Si2401 Preliminary Rev 0 9 73 Notes...

Page 74: ...ibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation...