Si53xx-RM
Rev. 0.52
169
A
PPENDIX
I—Si5374
AND
Si5375 PCB L
AYOUT
R
ECOMMENDATIONS
The following is a set of recommendations and guidelines for printed circuit board layout with the Si5374 and
Si5375 devices. Because the four DSPLLs are in close physical and electrical proximity to one another, PCB layout
is critical to achieving the highest levels of jitter performance. The following images were taken from the Si537x-
EVB (evaluation board) layout. For more details about this board, refer to the Si537x-EVB Evaluation Board User's
Guide.
Figure 95. Vdd Plane
Use a solid and undisturbed ground plane for the Si537x and all of the clock input and output return paths.
For applications that wish to logically connect the four RSTL_x signals, do not tie them together underneath the
BGA package. Instead connect them outside of the BGA footprint.
Where possible, place the CKOUT and CKIN signals on separate PCB layers with a ground layer between
them. The use of ground guard traces between all clock inputs and outputs is recommended.
Isolated
Vdd’s
Main
Vdd
Isolated
Vdd’s
The
four
Vdd
supplies
should
be
isolated
from
one
another
with
four
ferrite
beads.
They
should
be
separately
bypassed
with
capacitors
that
are
located
very
close
to
the
Si537x
device.
Summary of Contents for Si5316 Series
Page 2: ...Si53xx RM 2 Rev 0 52 ...
Page 110: ...Si53xx RM 110 Rev 0 52 Figure 48 sfout_5 LVPECL Figure 49 sfout_6 CML ...
Page 111: ...Si53xx RM Rev 0 52 111 Figure 50 sfout_7 LVDS ...
Page 127: ...Si53xx RM Rev 0 52 127 Figure 66 155 52 MHz In 622 08 MHz Out Loop BW 7 Hz Si5324 ...
Page 128: ...Si53xx RM 128 Rev 0 52 Figure 67 19 44 MHz In 156 25 MHz Out Loop BW 80 Hz ...
Page 129: ...Si53xx RM Rev 0 52 129 Figure 68 19 44 MHz In 156 25 MHz Out Loop BW 5 Hz Si5324 ...
Page 131: ...Si53xx RM Rev 0 52 131 Figure 70 61 44 MHz In 491 52 MHz Out Loop BW 7 Hz Si5324 ...
Page 132: ...Si53xx RM 132 Rev 0 52 Figure 71 622 08 MHz In 672 16 MHz Out Loop BW 6 9 kHz ...
Page 133: ...Si53xx RM Rev 0 52 133 Figure 72 622 08 MHz In 672 16 MHz Out Loop BW 100 Hz ...
Page 134: ...Si53xx RM 134 Rev 0 52 Figure 73 156 25 MHz In 155 52 MHz Out ...
Page 139: ...Si53xx RM Rev 0 52 139 Figure 78 86 685 MHz In 173 371 MHz Out ...
Page 140: ...Si53xx RM 140 Rev 0 52 Figure 79 86 685 MHz In 693 493 MHz Out ...
Page 142: ...Si53xx RM 142 Rev 0 52 Figure 81 10 MHz In 1 GHz Out ...
Page 174: ...Si53xx RM 174 Rev 0 52 Figure 99 Si5374 Si5375 DSPLL A ...
Page 175: ...Si53xx RM Rev 0 52 175 Figure 100 Si5374 Si5375 DSPLL B ...
Page 176: ...Si53xx RM 176 Rev 0 52 Figure 101 Si5374 Si5375 DSPLL C ...