Si53xx-RM
Rev. 0.52
79
calibration and will appear after the self-calibration routine is completed. The SQ_ICAL bit is self-clearing after a
successful ICAL.
After a successful self-calibration has been performed with a valid input clock, it is not necessary to reinitiate a self-
calibration for subsequent losses of input clock. If the input clock is lost following self-calibration, the device enters
digital hold mode. When the input clock returns, the device relocks to the input clock without performing a self-
calibration.
After power-up and writing of dividers or PLL registers, the user must set
ICAL
= 1 to initiate a self-calibration. LOL
will go low when self calibration is complete. Depending on the selected value of the loop bandwidth, it may take a
few seconds more for the output frequency and phase to completely settle.
It is recommended that a software reset precede all ICALs and their associated register writes by setting
RST_REG
(Register 136.7).
7.2.1.1. PLL Self-Calibration (Si5324, Si5327, Si5369, Si5374)
Due to the low loop bandwidth of the Si5324, Si5327, Si5369, and Si5374, the lock time of the Si5324/27/69/75 is
significantly longer than the lock time of the Si5326. As a method of reducing the lock time, the
FAST_LOCK
register bit can be set to improve lock times. As the Si5324/27/69/74 data sheets indicate,
FAST_LOCK
is the LSB
of register 137. When
FAST_LOCK
is high, the lock time decreases. Because the Si5324/27/64/74 is initialized
with
FAST_LOCK
low, it must be written before ICAL. Typical Si5324/69/74 lock time (as defined from the start of
ICAL until LOL goes low) with FASTLOCK set is from one to ten seconds. The Si5327 lock time can be as long as
20 seconds. To reduce lock times, it is recommended that a value of 001 be written to
LOCKT
(the three LSBs of
register 19).
7.2.2. Input Clock Stability during Internal Self-Calibration
An ICAL must occur when the selected active CKINn clock is stable in frequency and with a frequency value that is
within the operating range that is reported by DSPLL
sim
. The other CKINs must be stable in frequency (< 100 ppm
from nominal) or squelched during an ICAL.
7.2.3. Self-Calibration Caused by Changes in Input Frequency
If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a
self-calibration.
7.2.4. Narrowband Input-to-Output Skew (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)
The input-to-output skew is not controlled. External circuitry is required to control the input-to-output skew. Contact
Silicon Labs for further information.
7.2.5. Clock Output Behavior Before and During ICAL
Table 37. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table
Cases
CKOUT_ALWAYS_ON
SQ_ICAL
Results
1
1
0
0
CKOUT OFF until after the first ICAL
2
2
0
1
CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
3
3
1
0
CKOUT always ON, including during an ICAL
Summary of Contents for Si5316 Series
Page 2: ...Si53xx RM 2 Rev 0 52 ...
Page 110: ...Si53xx RM 110 Rev 0 52 Figure 48 sfout_5 LVPECL Figure 49 sfout_6 CML ...
Page 111: ...Si53xx RM Rev 0 52 111 Figure 50 sfout_7 LVDS ...
Page 127: ...Si53xx RM Rev 0 52 127 Figure 66 155 52 MHz In 622 08 MHz Out Loop BW 7 Hz Si5324 ...
Page 128: ...Si53xx RM 128 Rev 0 52 Figure 67 19 44 MHz In 156 25 MHz Out Loop BW 80 Hz ...
Page 129: ...Si53xx RM Rev 0 52 129 Figure 68 19 44 MHz In 156 25 MHz Out Loop BW 5 Hz Si5324 ...
Page 131: ...Si53xx RM Rev 0 52 131 Figure 70 61 44 MHz In 491 52 MHz Out Loop BW 7 Hz Si5324 ...
Page 132: ...Si53xx RM 132 Rev 0 52 Figure 71 622 08 MHz In 672 16 MHz Out Loop BW 6 9 kHz ...
Page 133: ...Si53xx RM Rev 0 52 133 Figure 72 622 08 MHz In 672 16 MHz Out Loop BW 100 Hz ...
Page 134: ...Si53xx RM 134 Rev 0 52 Figure 73 156 25 MHz In 155 52 MHz Out ...
Page 139: ...Si53xx RM Rev 0 52 139 Figure 78 86 685 MHz In 173 371 MHz Out ...
Page 140: ...Si53xx RM 140 Rev 0 52 Figure 79 86 685 MHz In 693 493 MHz Out ...
Page 142: ...Si53xx RM 142 Rev 0 52 Figure 81 10 MHz In 1 GHz Out ...
Page 174: ...Si53xx RM 174 Rev 0 52 Figure 99 Si5374 Si5375 DSPLL A ...
Page 175: ...Si53xx RM Rev 0 52 175 Figure 100 Si5374 Si5375 DSPLL B ...
Page 176: ...Si53xx RM 176 Rev 0 52 Figure 101 Si5374 Si5375 DSPLL C ...