S i 5 3 2 4
14
Preliminary Rev. 0.3
5, 10, 32
V
DD
V
DD
Supply
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following Vdd pins:
5
0.1 µF
10
0.1 µF
32
0.1 µF
A 1.0 µF should also be placed as close to the device as is practical.
7
6
XB
XA
I
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crys-
tal or external clock is set by RATE[1:0] pins.
8, 31, 20,
19
GND
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11
15
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M.
L setting corresponds to ground.
M setting corresponds to V
DD
/2.
H setting corresponds to V
DD
.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
12
13
CKIN2+
CKIN2–
I
Multi
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If
LOL_PIN
= 0, this pin will tristate. Active polarity is controlled by
the
LOL_POL
bit. The PLL lock status will always be reflected in the
LOL_INT
read only register bit.
Pin #
Pin Name
I/O
Signal Level
Description
Note:
Internal register names are indicated by underlined italics, e.g.,
INT_PIN
. See Si5324 Register Map.