Si5338-EVB
Rev. 1.4
5
6. Outputs (CLKxA/CLKxB)
Each of the four differential output drivers is capacitively coupled to the SMA connectors; so, the output signal will
have no dc bias. If a signal with dc bias is required, the ac coupling capacitors can be replaced with a 0
resistor.
The EVB provides pads for optional output terminations. These may be necessary when interfacing to SSTL and
HSTL signals.
6.1. Evaluating LVPECL Output Clocks
The EVB by default is populated to allow evaluating of all output clock formats with the exception of LVPECL
outputs. To evaluate LVPECL signals on the Si5338-EVB, a few components must be soldered down on the board.
Take CLK0 for example of. Note that CLK0 has R85, R121/R122, R1/R4, R2/R5, R3/R6, C4/C7, and C15/C17
attached to the nets of interest. The EVB comes with only R121/R122 and C15/C17 installed. This allows support
of all output types except LVPECL.
Evaluating an ac-coupled LVPECL clock on CLK0 requires a bias resistor of 130 or 200
to ground on each of the
output lines depending on driver VDDO. Refer to AN408, or Si5335 data sheet if applicable, for termination details.
Make the following changes depending on the CLK0 VDDO voltage:
For 3.3 V LVPECL (ac-coupled)
· Place 200
resistors in place of R1 and R4.
· Place 0
resistors in place of C4 and C7.
For 2.5 V LVPECL (ac-coupled)
· Place 130
resistors in place of R1 and R4.
· Place 0
resistors in place of C4 and C7.
The LVPECL output may also be dc-coupled to an LVPECL receiver. To dc-couple the CLK0 output, make the
component changes below. Note that R2, R3, R5, and R6 depend on VDDO.
Place 0
resistors in place of C15 and C17.
Place 50
resistors in place of R1 and R4.
Place C4 and C7
Select R2 and R3 (and similarly R5 and R6) to give a termination voltage of VTT = VDDO – 2 V.
For LVPECL termination on CLK1, 2, and 3 follow the guidelines above and refer to the schematics in “8.
Si5338-EVB Schematics” as needed.
6.2. Evaluating SSTL/HSTL Output Clocks
To support SSTL/HSTL outputs, either single-ended or differential, replace the output dc blocking capacitors with a
0
resistor. For example, for CLK0 output, replace C15 with 0
resistor for single-ended, or replace both C15 &
C17 with 0
for differential output. Do the same for CLK1,2,3 as needed. Remember to properly terminate at the
receiver input.
The Si5338-EVB can support on-board termination of SSTL/HSTL outputs, if on-board terminated, measurement
of the clock output at the SMA connector would require a high impedance measurement device to prevent
overloading of the output. If on-board output termination is desired, the following components must be installed
(using CLK0 as an example.)
For 1.8 or 2.5 V V
DDO
: R2 = 2 k
, R3 = 2 k
, R1 = 50
, C4 = 0.1 µF
For 3.3 V V
DDO
: R2 = 2.42 k
, R3 = 2 k
, R1 = 50
, C4 = 0.1 µF
Follow similar guidelines for CLK1,2,3 as required. Refer to AN408, or Si5335 data sheet if applicable, for more
details on clock termination.
