Silicon Laboratories SiM3U1x4, Manual

Page 1: ... 32 bit real time clock RTC with multiple alarms Watchdog timer Current to Voltage Converter Supports up to 6 mA input range Supply Voltage 2 7 to 5 5 V regulator enabled 1 8 to 3 6 V regulator disabled Low Power Features 85 nA current mode with voltage supply monitor enabled 350 nA current mode with RTC internal oscillator 620 nA current mode with RTC external oscillator 10 µs wakeup lowest power...

Page 2: ...SiM3U1xx 2 Preliminary Rev 0 8 ...

Page 3: ...agement Unit PMU 37 4 1 5 Device Power Modes 38 4 2 I O 40 4 2 1 General Features 40 4 2 2 High Drive Pins PB4 40 4 2 3 5 V Tolerant Pins PB3 40 4 2 4 Crossbars 40 4 3 Clocking 41 4 3 1 PLL PLL0 42 4 3 2 Low Power Oscillator LPOSC0 42 4 3 3 Low Frequency Oscillator LFOSC0 42 4 3 4 External Oscillators EXTOSC0 42 4 4 Data Peripherals 43 4 4 1 16 Channel DMA Controller 43 4 4 2 128 192 256 bit Hardw...

Page 4: ...tions 74 6 1 1 LGA 92 Solder Mask Design 76 6 1 2 LGA 92 Stencil Design 76 6 1 3 LGA 92 Card Assembly 76 6 2 TQFP 80 Package Specifications 77 6 2 1 TQFP 80 Solder Mask Design 80 6 2 2 TQFP 80 Stencil Design 80 6 2 3 TQFP 80 Card Assembly 80 6 3 QFN 64 Package Specifications 81 6 3 1 QFN 64 Solder Mask Design 83 6 3 2 QFN 64 Stencil Design 83 6 3 3 QFN 64 Card Assembly 83 6 4 TQFP 64 Package Speci...

Page 5: ...the SiM3U1xx devices This description can be found in the SiM3xxxx HAL API Reference Manual 1 1 3 ARM Cortex M3 Reference Manual The ARM specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex M3 reference documentation The online reference manual can be found here http infocenter arm com help topic com arm doc subset cortexm m3 index html cortexm3 1 2 Convent...

Page 6: ...xx devices when the internal regulator and USB are not used Figure 2 2 Connection Diagram with Voltage Regulator Not Used and No USB Figure 2 3 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator used and USB is connected bus powered SiM3U1xx Device VREGn VREGIN VSS VBUS VSSHD 1 uF and 0 1 uF bypass capacitors required for each power pin placed...

Page 7: ... Connected Self Powered Figure 2 5 shows a typical connection diagram for the power pins of the SiM3U1xx devices when the internal regulator used USB is connected bus powered and the VIO and VIOHD pins are sourced from separate supplies SiM3U1xx Device VREGn VREGIN VSS VSSHD 1 uF and 0 1 uF bypass capacitors required for each power pin placed as close to the pins as possible 3 3 V out VBUS USB 5 V...

Page 8: ...e Regulator Used USB Connected Bus Powered and I O Powered Separately SiM3U1xx Device VREGn VREGIN VSS VSSHD 1 uF and 0 1 uF bypass capacitors required for each power pin placed as close to the pins as possible VBUS USB 5 V in VIOHD VIO VDD 3 3 6 V in 1 8 3 3 V in 3 3 V out ...

Page 9: ... VIOHD VIOHD HV Mode default 2 7 6 0 V LV Mode 1 8 3 6 V Voltage on I O pins Port Bank 0 1 and 2 I O VIN VSS VIO V Voltage on I O pins Port Bank 3 I O and RESET VIN SiM3U1x7 PB3 0 PB3 7 and RESET VSS VIO 2 0 V SiM3U1x7 PB3 8 PB3 11 VSS Lowest of VIO 2 0 or VREGIN V SiM3U1x6 PB3 0 PB3 5 and RESET VSS VIO 2 0 V SiM3U1x6 PB3 6 PB3 9 VSS Lowest of VIO 2 0 or VREGIN V SiM3U1x4 RESET VSS VIO 2 0 V SiM3U...

Page 10: ...MHz 20 23 mA FAHB FAPB 48 MHz 13 15 3 mA FAHB FAPB 20 MHz 5 3 7 3 mA FAHB FAPB 2 5 MHz 1 0 2 8 mA Power Mode 22 3 4 Core halted with peripheral clocks ON IDD FAHB 80 MHz FAPB 40 MHz 19 22 mA FAHB FAPB 48 MHz 19 21 5 mA FAHB FAPB 20 MHz 7 8 9 7 mA FAHB FAPB 2 5 MHz 1 3 3 mA Notes 1 Perhipheral currents drop to zero when peripheral clock and peripheral are disabled unless otherwise noted 2 Currents ...

Page 11: ...rive I O dis abled IVIOHD HV Mode default 2 5 5 µA LV Mode 2 nA Table 3 2 Power Consumption Continued Parameter Symbol Conditions Min Typ Max Units Notes 1 Perhipheral currents drop to zero when peripheral clock and peripheral are disabled unless otherwise noted 2 Currents are additive For example where IDD is specified and the mode is not mutually exclusive enabling the functions increases supply...

Page 12: ... 215 nA Operating at 16 4 kHz TA 85 C 500 nA Table 3 2 Power Consumption Continued Parameter Symbol Conditions Min Typ Max Units Notes 1 Perhipheral currents drop to zero when peripheral clock and peripheral are disabled unless otherwise noted 2 Currents are additive For example where IDD is specified and the mode is not mutually exclusive enabling the functions increases supply current by the spe...

Page 13: ... 1 5 1 9 µA Voltage Supply Monitor VMON0 IVMON 15 25 µA Table 3 2 Power Consumption Continued Parameter Symbol Conditions Min Typ Max Units Notes 1 Perhipheral currents drop to zero when peripheral clock and peripheral are disabled unless otherwise noted 2 Currents are additive For example where IDD is specified and the mode is not mutually exclusive enabling the functions increases supply current...

Page 14: ...otherwise noted 2 Currents are additive For example where IDD is specified and the mode is not mutually exclusive enabling the functions increases supply current by the specified amount 3 Includes all peripherals that cannot have clocks gated in the Clock Control module 4 Includes supply current from internal regulator and PLL0OSC 48 MHz USB0OSC 48 MHz or LPOSC0 48 MHz 5 Flash execution numbers us...

Page 15: ...GM Early Warning 4 2 4 4 4 6 V Power On Reset POR Threshold VPOR Rising Voltage on VDD 1 4 V Falling Voltage on VDD 0 8 1 1 3 V VDD Ramp Time tRMP Time to VDD 1 8 V 10 3000 µs Reset Delay from POR tPOR Relative to VDD VPOR 3 100 ms Reset Delay from non POR source tRST Time between release of reset source and code execution 10 µs RESET Low Time to Generate Reset tRSTL 50 ns Missing Clock Detector R...

Page 16: ...USEN 1 3 2 3 3 3 4 V 4 VREGIN 5 5 BGDIS 1 SUSEN X IDDOUT 500 µA 2 3 2 8 3 6 V 4 VREGIN 5 5 BGDIS 1 SUSEN X IDDOUT 5 mA 2 1 2 65 3 3 V Output Current at VDD pin IDDOUT 4 VREGIN 5 5 BGDIS 0 SUSEN X 150 mA 4 VREGIN 5 5 BGDIS 1 SUSEN X 5 mA Output Load Regulation VDDLR BGDIS 0 0 1 1 mV mA Output Capacitance CVDD 1 10 µF Note Total current VREG0 is capable of providing Any current consumed by the SiM3U...

Page 17: ...REGBD 400mV Dropout 11 5 mA External Capacitance with External BJT CBJT 4 7 µF Standalone Mode Load Reg ulation LRSTAND ALONE 1 mV mA Standalone Mode External Capacitance CSTAND ALONE 47 nF Current Limit Range ILIMIT 1 Sense Resistor 10 720 mA Current Limit Accuracy 10 Foldback Limit Accuracy 20 Current Sense Resistor RSENSE 1 Internal Pull Down RPD 10 k Internal Pull Up RPU 5 k Current Sensor Sen...

Page 18: ...lity and Reliability Report Table 3 8 Internal Oscillators Parameter Symbol Conditions Min Typ Max Units USB Oscillator USB0OSC Oscillator Frequency fUSB0OSC No Clock Recovery Full Temperature and Supply Range 47 3 48 48 7 MHz No Clock Recovery TA 25 C VDD 3 3 V 47 8 48 48 2 MHz USB Active with Clock Recovery Full Temperature and Supply Range 47 88 48 48 12 MHz Power Supply Sensitivity PSSUSB0OSC ...

Page 19: ...CK fREF 48 MHz fPLL0OSC 80 MHz M 59 N 99 LOCKTH 0 1 7 µs fREF 20 MHz fPLL0OSC 80 MHz M 24 N 99 LOCKTH 0 1 7 µs fREF 32 kHz fPLL0OSC 80 MHz M 0 N 2440 LOCKTH 0 91 µs Table 3 8 Internal Oscillators Continued Parameter Symbol Conditions Min Typ Max Units ...

Page 20: ... Supply Range 13 4 16 4 19 7 kHz TA 25 C VDD 3 3 V 15 8 16 4 17 3 kHz Power Supply Sensitivity PSSLFOSC TA 25 C 2 4 V Temperature Sensitivity TSLFOSC VDD 3 3 V 0 2 C RTC0 Oscillator RTC0OSC Missing Clock Detector Trigger Frequency fRTCMCD 8 15 kHz RTC Robust Duty Cycle Range DCRTC 25 55 Note PLL0OSC in free running oscillator mode Table 3 9 External Oscillator Parameter Symbol Conditions Min Typ M...

Page 21: ... Low Power Mode 4 MHz Conversion Time tCNV 10 Bit Conversion SAR Clock 16 MHz APB Clock 40 MHz 762 5 ns Sample Hold Capacitor CSAR Gain 1 5 pF Gain 0 5 2 5 pF Input Pin Capacitance CIN High Quality Inputs 18 pF Normal Inputs 20 pF Input Mux Impedance RMUX High Quality Inputs 300 Normal Inputs 550 Voltage Reference Range VREF 1 VDD V Input Voltage Range VIN Gain 1 0 VREF V Gain 0 5 0 2xVREF V Power...

Page 22: ...Distortion Up to 5th Harmonic THD 12 Bit Mode 78 dB 10 Bit Mode 77 dB Spurious Free Dynamic Range SFDR 12 Bit Mode 79 dB 10 Bit Mode 74 dB Dynamic Performance with Internal Reference in Low Power Mode 10 kHz Sine Wave Input 1dB below full scale Max throughput Signal to Noise SNR 12 Bit Mode TBD 66 dB 10 Bit Mode TBD 60 dB Signal to Noise Plus Distortion SNDR 12 Bit Mode TBD 66 dB 10 Bit Mode TBD 6...

Page 23: ... LSB Output Compliance Range VOCR VDD 1 0 V Full Scale Output Current IOUT 2 mA Range 2 0 2 046 2 10 mA 1 mA Range 1 00 1 023 1 05 mA 0 5 mA Range 495 511 5 525 µA Offset Error EOFF 250 nA Full Scale Error Tempco TCFS 2 mA Range 100 ppm C VDD Power Supply Rejection Ratio 2 mA Range 220 ppm V Test Load Impedance to VSS RTEST 1 k Dynamic Performance Output Settling Time to 1 2 LSB min output to max ...

Page 24: ...able 3 13 Current to Voltage Converter IVC Parameter Symbol Conditions Min Typ Max Units Supply Voltage VDD VDDIVC 2 2 3 6 V Input Pin Voltage VIN 2 2 VDD V Minimum Input Current source IIN 100 µA Integral Nonlinearity INLIVC 0 6 0 6 Full Scale Output VIVCOUT 1 65 V Slope MIVC Input Range 1 mA INxRANGE 101 1 62 1 66 1 73 V mA Input Range 2 mA INxRANGE 100 810 830 855 mV mA Input Range 3 mA INxRANG...

Page 25: ...Reference VREF0 Valid Supply Range VDD VREF2X 0 1 8 3 6 V VREF2X 1 2 7 3 6 V Output Voltage VREFP 25 C ambient VREF2X 0 1 195 1 2 1 205 V 25 C ambient VREF2X 1 2 39 2 4 2 41 V Short Circuit Current ISC 10 mA Temperature Coefficient TCVREFP 25 ppm C Load Regulation LRVREFP Load 0 to 200 µA to VREFGND 4 5 ppm µA Load Capacitor CVREFP Load 0 to 200 µA to VREFGND 0 1 µF Turn on Time tVREFPON 4 7 µF ta...

Page 26: ...mperature Sensor Parameter Symbol Conditions Min Typ Max Units Offset VOFF TA 0 C 760 mV Offset Error EOFF TA 0 C 14 mV Slope M 2 8 mV C Slope Error EM TBD µV C Linearity 1 C Turn on Time 1 8 µs Note Represents one standard deviation from the mean ...

Page 27: ...0 16 7 mV CMPHYP 11 32 8 mV Negative Hysterisis Mode 0 CPMD 00 HYSCP CMPHYN 00 0 37 mV CMPHYN 01 7 9 mV CMPHYN 10 16 1 mV CMPHYN 11 32 7 mV Positive Hysterisis Mode 1 CPMD 01 HYSCP CMPHYP 00 0 47 mV CMPHYP 01 5 85 mV CMPHYP 10 12 mV CMPHYP 11 24 4 mV Negative Hysterisis Mode 1 CPMD 01 HYSCP CMPHYN 00 0 47 mV CMPHYN 01 6 0 mV CMPHYN 10 12 1 mV CMPHYN 11 24 6 mV Positive Hysterisis Mode 2 CPMD 10 HY...

Page 28: ...9 mV CMPHYN 10 7 9 mV CMPHYN 11 16 mV Input Range CP or CP VIN 0 25 VDD 0 2 5 V Input Pin Capacitance CCP PB2 Pins 7 5 pF PB3 Pins 10 5 pF Common Mode Rejection Ratio CMRRCP 75 dB Power Supply Rejection Ratio PSRRCP 72 dB Input Offset Voltage VOFF TA 25 C 5 0 5 mV Input Offset Tempco TCOFF 3 5 µV C Reference DAC Resolution NBits 6 bits Table 3 16 Comparator Continued Parameter Symbol Conditions Mi...

Page 29: ...over Point VCRS 1 3 2 0 V Output Impedance ZDRV Driving High Driving Low 38 38 Pull up Resistance RPU Full Speed D Pull up Low Speed D Pull up 1 425 1 5 1 575 k Output Rise Time tR Low Speed Full Speed 75 4 300 20 ns Output Fall Time tF Low Speed Full Speed 75 4 300 20 ns Receiver Differential Input Sensitivity VDI D D 0 2 V Differential Input Common Mode Range VCM 0 8 2 5 V Input Leakage Current ...

Page 30: ... and PB2 Pins 4 pF PB3 Pins 7 pF Weak Pull Up Current VIN 0 V IPU VIO 1 8 6 3 5 2 µA VIO 3 6 30 20 10 µA Input Leakage Pullups off or Analog ILK 0 VIN VIO 1 1 µA Input Leakage Current of Port Bank 3 I O VIN above VIO IL VIO VIN VIO 2 0 V pins without EXREG functions 0 5 150 µA VIO VIN VREGIN pins with EXREG functions 0 5 150 µA High Drive I O PB4 Output High Voltage VOH Standard Mode Low Drive IOH...

Page 31: ...HD 6 V VIOHD 0 6 V Input Low Voltage VIL 0 6 V N Channel Sink Current Limit 2 7 V VIOHD 6 V VOL 0 8V ISINKL Mode 0 1 76 mA Mode 1 2 34 Mode 2 3 52 Mode 3 4 69 Mode 4 7 03 Mode 5 9 38 Mode 6 14 06 Mode 7 18 75 Mode 8 28 13 Mode 9 37 5 Mode 10 56 25 Mode 11 75 Mode 12 112 5 Mode 13 150 Mode 14 225 Mode 15 300 Total N Channel Sink Current on P4 0 P4 5 DC ISINKLT 400 mA Table 3 18 Port I O Continued P...

Page 32: ... 11 37 5 Mode 12 56 25 Mode 13 75 Mode 14 112 5 Mode 15 150 Total P Channel Source Current on P4 0 P4 5 DC ISRCLT 400 mA Pin Capacitance CIO 30 pF Weak Pull Up Current in Low Volt age Mode IPU VIOHD 1 8 V 6 3 5 2 µA VIOHD 3 6 V 30 20 10 µA Weak Pull Up Current in High Volt age Mode IPU VIOHD 2 7 V 15 10 5 µA VIOHD 6 V 30 20 10 µA Input Leakage Pullups off ILK 1 1 µA Table 3 18 Port I O Continued P...

Page 33: ...a multi layer PCB with any exposed pad soldered to a PCB pad Table 3 20 Absolute Maximum Ratings Parameter Symbol Conditions Min Max Units Ambient Temperature Under Bias TBIAS 55 125 C Storage Temperature TSTG 65 150 C Voltage on VDD VDD VSS 0 3 4 2 V Voltage on VREGIN VREGIN EXTVREG0 Not Used VSS 0 3 6 0 V EXTVREG0 Used VSS 0 3 3 6 V Voltage on VBUS VBUS VIO 3 3 V VSS 0 3 5 8 V VIO 3 3 V VSS 0 3 ...

Page 34: ...HD 400 mA Total Current Sourced out of Ground Pins IVSS VSS VSSHD 400 mA Current Sourced or Sunk by Any I O Pin IPIO PB0 PB1 PB2 PB3 and RESET 100 100 mA PB4 300 300 mA Current Injected on Any I O Pin IINJ PB0 PB1 PB2 PB3 and RESET 100 100 mA PB4 300 300 mA Total Injected Current on I O Pins IINJ Sum of all I O and RESET 400 400 mA Power Dissipation at TA 85 C PD LGA 92 Package 570 mW TQFP 80 Pack...

Page 35: ...full speed USB operation with 0 25 accuracy Low power internal oscillator 20 MHz and 2 5 MHz modes Low frequency internal oscillator 16 4 kHz External RTC crystal oscillator 32 768 kHz External oscillator Crystal RC C CMOS clock modes Programmable clock divider allows any oscillator source to be divided by binary factor from 1 128 Data Peripherals 16 Channel DMA Controller 128 192 256 bit Hardware...

Page 36: ...ces are available in 40 pin or 64 pin QFN 64 pin or 80 pin TQFP or 92 pin LGA packages All package options are lead free and RoHS compliant See Table 6 1 for ordering information A block diagram is included in Figure 4 1 Figure 4 1 Precision32 SiM3U1xx Family Block Diagram USB0 2 kB Buffer 5 Bidirectional Endpoints Internal Oscillator I O EMIF Standard I O pins Crossbars 5 V tolerant pins High Dri...

Page 37: ...EG0 The External Regulator provides all the circuitry needed for a high power regulator except the power transistor NPN or PNP and current sensing resistor if current limiting is enabled The External Regulator module has the following features Interfaces with either an NPN or PNP external transistor that serves as the pass device for the high current regulator Automatic current limiting Automatic ...

Page 38: ...at full speed Code executing from Flash Power Mode 1 PM1 Core operating at full speed Code executing from RAM Execute code from RAM Jump to code in Flash Power Mode 2 PM2 Core halted AHB and APB operate at full speed for peripherals WFI or WFE instruction NVIC or WIC wakeup Power Mode 3 Fast Wake PM3FW All clocks stopped except LFOSC0 or RTC0OSC AHB and APB set to Low Power Oscillator Core clock s...

Page 39: ...ould then execute a WFI or WFE instruction If the WFI instruction is called from an interrupt service routine the interrupt that wakes the device from PM3FW must be of a sufficient priority to be recognized by the core By keeping the core clock running at a slow frequency in PM3 and changing the AHB and APB clocks to the Low Power Oscillator the device can wake up faster than in standard Power Mod...

Page 40: ...upports various functions including GPIO UART1 pins EPCA0 pins or Port Mapped Level Shifting 4 2 3 5 V Tolerant Pins PB3 The 5 V tolerant pins can be connected to external circuitry operating at voltages above the device supply without needing extra components to shift the voltage level 4 2 4 Crossbars The SiM3U1xx devices have two Crossbars with the following features Flexible peripheral assignme...

Page 41: ...als and is synchronized with the AHB clock The APB clock can be equal to the AHB clock if AHB is less than or equal to 50 MHz or set to the AHB clock divided by two Clock Control allows the AHB and APB clocks to be turned off to unused peripherals to save system power Any registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled Most peripherals have...

Page 42: ...s including dithering and spectrum spreading using the STALL bit during jitter sensitive operations 4 3 2 Low Power Oscillator LPOSC0 The Low Power Oscillator is the default AHB oscillator on SiM3U1xx devices and enables or disables automatically as needed The Low Power Oscillator has the following features 20 MHz and divided 2 5 MHz frequencies available for the AHB clock Automatically starts and...

Page 43: ... the following features Operates on 4 word 16 byte blocks Supports key sizes of 128 192 and 256 bits for both encryption and decryption Generates the round key for decryption operations All cipher operations can be performed without any firmware intervention for a set of 4 word blocks up to 32 kB Support for various chained and stream ciphering configurations with XOR paths on both the input and o...

Page 44: ... synchronization triggers and outputs Pulse Width Modulation PWM waveform generation High speed square wave generation Input capture mode DMA capability for both input capture and waveform generation PWM generation halt input The Standard PCA module PCA includes the following features Two independent channels Center and edge aligned waveform generation Programmable clock divisor and multiple optio...

Page 45: ...y from VDD and remains operational even when the device goes into its lowest power down mode The output can be buffered and routed to an I O pin to provide an accurate low frequency clock to other devices while the core is in its lowest power down mode 4 5 4 Low Power Timer LPTIMER0 The Low Power Timer LPTIMER0 module runs from the clock selected by the RTC0 module allowing the LPTIMER0 to operate...

Page 46: ...module includes the following features Full and Low Speed functionality Implements 5 bidirectional endpoints with 4 of these capable of initiating autonomous DMA transfers USB 2 0 compliant USB peripheral support no host capability Direct module access to 2k bytes of RAM for dedicated FIFO memory Dedicated USB0 oscillator with clock recovery to meet USB clocking requirements with no external compo...

Page 47: ...rror overrun and underrun detection Multi master and half duplex support Multiple loop back modes supported 4 6 5 SPI SPI0 SPI1 SPI is a 3 or 4 wire communication interface that includes a clock input data output data and an optional select signal The SPI module includes the following features Supports 3 or 4 wire master or slave modes Supports up to 10 MHz clock in master mode and 5 MHz clock in ...

Page 48: ...tup hold times Spike suppression up to 2 times the APB period 4 6 7 I2 S I2S0 The I2 S module receives digital data from an external source over a data line in the standard I2 S left justified right justified or time domain multiplexing format de serializes the data and generates requests to transfer the data using the DMA The module also reads stereo audio samples from the DMA serializes the data...

Page 49: ...e SARADC module clock Counting up from zero the phase counter marks sixteen equally spaced events for any number of SARADC modules The ADCs can use this phase counter to start a conversion The programmable pulse generator creates a 50 duty cycle pulse with a period of 16 phase counter ticks Up to four programmable outputs available to external devices can be driven by the pulse generator with prog...

Page 50: ...her with a single conversion Scanning option allows the module to convert a single or series of channels and compare against the threshold while the AHB clock is stopped and the core is in a low power mode 4 7 5 Low Current Comparators CMP0 CMP1 The Comparators take two analog input voltages and output the relationship between these voltages less than or greater than as a digital signal The Low Po...

Page 51: ... the register descriptions unless the bits only reset with a power on reset The contents of RAM are unaffected during a reset any previously stored data is preserved as long as power is not lost The Port I O latches are reset to 1 in open drain mode Weak pullups are enabled during and after the reset For VDD Supply Monitor and power on resets the RESET pin is driven low until the device exits the ...

Page 52: ...ardless of the peripheral s lock state 4 10 On Chip Debugging The SiM3U1xx devices include JTAG and Serial Wire programming and debugging interfaces and ETM for instruction trace The JTAG interface is supported on SiM3U1x7 and SiM3U1x6 devices and the ETM interface is supported on SiM3U1x7 devices The JTAG and ETM interfaces can be optionally enabled to provide more visibility while debugging at t...

Page 53: ... 33 34 35 36 37 38 39 40 VSS VIO PB1 13 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VBUS VSS VDD VIO D D RESET PB0 0 PB0 1 PB0 2 PB0 3 PB0 4 PB0 5 PB0 6 PB0 7 PB0 8 PB0 9 PB0 10 PB0 13 PB0 14 PB0 15 PB1 0 PB1 1 PB1 2 TRST PB1 3 TDO SWV PB1 4 TDI PB1 5 ETM0 PB1 6 ETM1 VIO PB1 8 ETM3 PB1 9 TRACECLK PB1 10 PB1 11 PB1 12 PB1 14 PB2 3 PB2 4 PB2 5 PB2 6 PB2 7 PB2 8 PB2 9 PB2 10 PB2 11 PB...

Page 54: ...0 4 PB0 6 PB0 8 PB0 9 PB0 10 VREGIN VIO PB1 13 PB1 14 PB2 3 PB2 5 PB2 7 PB2 9 PB2 11 PB2 12 PB2 13 PB2 14 PB1 15 PB2 1 PB4 4 PB4 5 PB4 3 PB4 2 VIOHD PB4 0 PB4 1 PB3 0 PB3 1 PB3 2 PB3 4 PB3 6 PB3 8 VSSHD PB3 3 PB3 5 PB3 7 PB3 9 PB3 10 PB3 11 VSS PB2 4 PB2 6 PB2 8 PB2 10 PB2 0 PB2 2 VBUS VSS PB0 0 PB0 1 PB0 3 PB0 5 PB0 7 PB0 13 PB0 15 PB1 0 PB1 2 PB1 4 PB1 6 VIO PB1 10 PB1 11 PB1 12 PB0 12 PB1 9 SWD...

Page 55: ... 74 A44 VIO Power I O 32 49 73 A19 A29 A43 VREGIN Power Regulator 76 A45 VSSHD Ground High Drive 4 B2 VIOHD Power High Drive 5 A3 RESET Active low Reset 80 A48 D USB Data 79 A47 D USB Data 78 A46 VBUS USB Bus Sense 77 B35 SWCLK TCK Serial Wire JTAG 45 B20 SWDIO TMS Serial Wire JTAG 44 A27 PB0 0 Standard I O 72 B33 XBR0 ADC0 0 PB0 1 Standard I O 71 B32 XBR0 ADC0 1 CS0 0 PB0 2 Standard I O 70 A42 XB...

Page 56: ...B25 XBR0 ADC0 11 PB1 2 TRST Standard I O JTAG 54 A32 XBR0 PB1 3 TDO SWV Standard I O JTAG Serial Wire Viewer 53 B24 XBR0 ADC0 12 ADC1 12 PB1 4 TDI Standard I O JTAG 52 A31 XBR0 ADC0 13 ADC1 13 PB1 5 ETM0 Standard I O ETM 51 B23 XBR0 ADC0 14 ADC1 14 PB1 6 ETM1 Standard I O ETM 50 A30 XBR0 ADC0 15 ADC1 15 PB1 7 ETM2 Standard I O ETM 48 B22 XBR0 ADC1 11 CS0 8 Table 5 1 Pin Definitions and alternate f...

Page 57: ...rd I O 37 B17 XBR1 A17m A9 LSI0 Yes INT0 0 INT1 0 WAKE 3 ADC1 2 CS0 13 PB2 1 Standard I O 36 A21 XBR1 A16m A8 LSI1 Yes INT0 1 INT1 1 WAKE 4 ADC1 1 CS0 14 PB2 2 Standard I O 35 B16 XBR1 AD15m A7 LSI2 Yes INT0 2 INT1 2 WAKE 5 ADC1 0 CS0 15 PMU_Asleep PB2 3 Standard I O 34 A20 XBR1 AD14m A6 LSI3 Yes INT0 3 INT1 3 WAKE 6 PB2 4 Standard I O 31 B14 XBR1 AD13m A5 LSI4 Yes INT0 4 INT1 4 WAKE 7 Table 5 1 P...

Page 58: ... A13 XBR1 AD4m D4 Yes CMP0P 1 CMP1P 1 PB2 14 Standard I O 21 D2 XBR1 AD3m D3 Yes CMP0N 1 CMP1N 1 PB3 0 5 V Tolerant I O 20 A12 XBR1 AD2m D2 CMP0P 2 CMP1P 2 PB3 1 5 V Tolerant I O 19 A11 XBR1 AD1m D1 CMP0N 2 CMP1N 2 PB3 2 5 V Tolerant I O 18 A10 XBR1 AD0m D0 DAC0T0 DAC1T0 LPT0T0 CMP0P 3 CMP1P 3 PB3 3 5 V Tolerant I O 17 B8 XBR1 WR DAC0T1 DAC1T1 INT0 8 INT1 8 CMP0N 3 CMP1N 3 Table 5 1 Pin Definition...

Page 59: ...5 DAC1T5 LPT0T2 INT0 13 INT1 13 WAKE 12 CMP0P 6 CMP1P 6 EXREGSP PB3 9 5 V Tolerant I O 11 B5 XBR1 BE0 DAC0T6 DAC1T6 INT0 14 INT1 14 WAKE 13 CMP0N 6 CMP1N 6 EXREGSN PB3 10 5 V Tolerant I O 10 B4 XBR1 INT0 15 INT1 15 WAKE 14 CMP0P 7 CMP1P 7 EXREGOUT PB3 11 5 V Tolerant I O 9 B3 XBR1 WAKE 15 CMP0N 7 CMP1N 7 EXREGBD Table 5 1 Pin Definitions and alternate functions for SiM3U1x7 Continued Pin Name Type...

Page 60: ...package are no connect pins They should be soldered to the PCB for mechanical stabil ity but have no internal connections to the device Table 5 1 Pin Definitions and alternate functions for SiM3U1x7 Continued Pin Name Type Pin Numbers TQFP 80 Pin Numbers LGA 92 Crossbar Capability see Port Config Section Port Match External Memory Interface m muxed mode Port Mapped Level Shifter Output Toggle Logi...

Page 61: ...in TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PB4 3 VSSHD PB4 2 VIOHD PB4 0 PB4 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB0 0 PB0 1 PB0 2 PB0 3 PB0 4 PB0 5 PB0 6 PB0 7 PB0 8 PB0 10 PB0 11 PB0 12 PB0 13 PB0 14 TDO SWV PB0 15 TDI PB1 0 PB1 1 VIO PB1 3 PB1 4 PB1 5 PB3 0 PB3 1 PB3 2 PB3 3 PB3 4 PB3 5 PB3 6 PB3 7 PB3 8 PB3 9 SWCLK TCK SWDIO TMS PB...

Page 62: ...0 27 28 29 31 32 64 pin QFN TopView PB0 0 PB0 1 PB0 2 PB0 3 PB0 4 PB0 5 PB0 6 PB0 7 PB0 8 VBUS VSS VDD D D RESET VREGIN PB0 10 PB0 11 PB0 12 PB0 13 PB0 14 TDO SWV PB0 15 TDI PB1 0 PB1 1 VIO PB1 3 PB1 4 PB1 5 SWCLK TCK SWDIO TMS PB0 9 PB1 2 VSS VIO PB1 6 PB1 7 PB1 13 PB1 14 PB1 15 PB2 0 PB2 1 PB2 2 PB2 3 PB1 8 PB1 9 PB1 10 PB1 11 PB1 12 PB4 3 VSSHD PB4 2 VIOHD PB4 0 PB4 1 PB3 0 PB3 1 PB3 2 PB3 3 PB...

Page 63: ...S Ground 25 59 VDD Power Core 58 VIO Power I O 24 39 VREGIN Power Regulator 60 VSSHD Ground High Drive 2 VIOHD Power High Drive 3 RESET Active low Reset 64 D USB Data 63 D USB Data 62 VBUS USB Bus Sense 61 SWCLK TCK Serial Wire JTAG 36 SWDIO TMS Serial Wire JTAG 35 PB0 0 Standard I O 57 XBR0 ADC0 2 CS0 1 PB0 1 Standard I O 56 XBR0 ADC0 3 CS0 2 PB0 2 Standard I O 55 XBR0 ADC0 4 CS0 3 PB0 3 Standard...

Page 64: ...andard I O JTAG 42 XBR0 ADC0 13 ADC1 13 PB1 0 Standard I O 41 XBR0 ADC0 14 ADC1 14 PB1 1 Standard I O 40 XBR0 ADC0 15 ADC1 15 PB1 2 Standard I O 38 XBR0 ADC1 11 CS0 8 PB1 3 Standard I O 37 XBR0 ADC1 10 CS0 9 PB1 4 Standard I O 34 XBR0 ADC1 8 PB1 5 Standard I O 33 XBR0 ADC1 7 PB1 6 Standard I O 32 XBR0 ADC0T15 WAKE 0 ADC1 5 CS0 10 Table 5 2 Pin Definitions and alternate functions for SiM3U1x6 Conti...

Page 65: ...m A0 PB1 15 Standard I O 21 XBR0 AD7m D7 PB2 0 Standard I O 20 XBR1 AD6m D6 LSI0 Yes INT0 0 INT1 0 PB2 1 Standard I O 19 XBR1 AD5m D5 LSI1 Yes INT0 1 INT1 1 PB2 2 Standard I O 18 XBR1 AD4m D4 LSI2 Yes INT0 2 INT1 2 CMP0N 0 CMP1N 0 RTC0OSC_OUT PB2 3 Standard I O 17 XBR1 AD3m D3 LSI3 Yes INT0 3 INT1 3 CMP0P 0 CMP1P 0 PB3 0 5 V Tolerant I O 16 XBR1 AD2m D2 CMP0P 1 CMP1P 1 Table 5 2 Pin Definitions an...

Page 66: ...CMP0N 3 CMP1N 3 PB3 6 5 V Tolerant I O 10 XBR1 CS0 DAC0T3 DAC1T3 INT0 7 INT1 7 WAKE 12 CMP0P 4 CMP1P 4 EXREGSP PB3 7 5 V Tolerant I O 9 XBR1 BE1 DAC0T4 DAC1T4 INT0 8 INT1 8 WAKE 13 CMP0N 4 CMP1N 4 EXREGSN PB3 8 5 V Tolerant I O 8 XBR1 CS1 DAC0T5 DAC1T5 LPT0T1 INT0 9 INT1 9 WAKE 14 CMP0P 5 CMP1P 5 EXREGOUT Table 5 2 Pin Definitions and alternate functions for SiM3U1x6 Continued Pin Name Type Pin Nu...

Page 67: ...High Drive I O 5 LSO1 PB4 2 High Drive I O 4 LSO2 PB4 3 High Drive I O 1 LSO3 Table 5 2 Pin Definitions and alternate functions for SiM3U1x6 Continued Pin Name Type Pin Numbers Crossbar Capability see Port Config Section Port Match External Memory Interface m muxed mode Port Mapped Level Shifter Output Toggle Logic External Trigger Inputs Analog or Additional Functions ...

Page 68: ... 2 3 4 5 6 7 11 12 13 14 15 16 17 30 29 28 27 26 25 24 PB0 0 PB0 1 PB0 2 VBUS VDD D D RESET VREGIN 32 31 20 19 10 9 21 22 PB0 4 PB0 5 PB0 6 PB0 8 PB0 7 PB0 9 PB0 10 SWCLK SWDIO PB0 3 40 pin QFN Top View VSS VIO PB0 12 PB1 1 PB1 2 PB0 13 PB0 14 PB0 15 PB1 0 PB4 3 VSSHD PB4 2 VIOHD PB4 0 PB4 1 PB3 0 PB3 1 PB3 2 PB3 3 PB0 11 PB1 3 ...

Page 69: ...Power Core 35 VIO Power I O 13 VREGIN Power Regulator 36 VSSHD Ground High Drive 2 VIOHD Power High Drive 3 RESET Active low Reset 40 D USB Data 39 D USB Data 38 VBUS USB Bus Sense 37 SWCLK Serial Wire 24 SWDIO Serial Wire 23 PB0 0 Standard I O 34 XBR0 ADC0 8 CS0 7 RTC1 PB0 1 Standard I O 33 XBR0 RTC2 PB0 2 Standard I O 32 XBR0 ADC0 9 CS0 0 VREFGND PB0 3 Standard I O 31 XBR0 ADC0 10 CS0 1 VREF PB0...

Page 70: ...O 19 XBR0 ADC1T15 WAKE 1 ADC1 4 CS0 11 PB0 14 Standard I O 18 XBR0 WAKE 2 ADC1 3 CS0 12 PB0 15 Standard I O 17 XBR0 WAKE 3 ADC1 2 CS0 13 PB1 0 Standard I O 16 XBR0 WAKE 4 ADC1 1 CS0 14 PB1 1 Standard I O 15 XBR0 WAKE 5 ADC1 0 CS0 15 PMU_Asleep PB1 2 Standard I O 12 XBR0 CMP0N 0 CMP1N 0 RTC0OSC_OUT PB1 3 Standard I O 11 XBR0 CMP0P 0 CMP1P 0 Table 5 3 Pin Definitions and alternate functions for SiM3...

Page 71: ...1T2 LPT0T2 INT0 2 INT1 3 WAKE 14 CMP0P 2 CMP1P 2 EXREGOUT PB3 3 5 V Tolerant I O 7 XBR1 DAC0T3 DAC1T3 INT0 3 INT1 3 WAKE 15 CMP0N 2 CMP1N 2 EXREGBD PB4 0 High Drive I O 6 PB4 1 High Drive I O 5 PB4 2 High Drive I O 4 PB4 3 High Drive I O 1 Table 5 3 Pin Definitions and alternate functions for SiM3U1x4 Continued Pin Name Type Pin Numbers Crossbar Capability see Port Config Section Port Match Output...

Page 72: ...x 6 channels Enhanced 2 x 2 channels Standard PWM capture and clock generation capabilites ADC 2 x 12 bit 250 ksps 10 bit 1 Msps SAR DAC 2 x 10 bit IDAC Temperature Sensor Internal VREF 16 channel Capacitive Sensing CAPSENSE Comparator 2 x low current Current to Voltage Converter IVC USB Full or low speed crystalless operation using internal USB oscillator Serial Buses 2 x USART 2 x UART 3 x SPI 2...

Page 73: ...2 SiM3U167 B GQ 256 32 24 65 6 16 16 16 8 8 16 TQFP 80 SiM3U166 B GM 256 32 16 50 4 13 15 15 6 6 15 QFN 64 SiM3U166 B GQ 256 32 16 50 4 13 15 15 6 6 15 TQFP 64 SiM3U164 B GM 256 32 28 4 7 11 12 3 3 10 QFN 40 SiM3U157 B GM 128 32 24 65 6 16 16 16 8 8 16 LGA 92 SiM3U157 B GQ 128 32 24 65 6 16 16 16 8 8 16 TQFP 80 SiM3U156 B GM 128 32 16 50 4 13 15 15 6 6 15 QFN 64 SiM3U156 B GQ 128 32 16 50 4 13 15 ...

Page 74: ...5 0 30 0 35 c 3 15 3 20 3 25 D 7 00 BSC D1 6 50 BSC D2 4 00 BSC e 0 50 BSC E 7 00 BSC E1 6 50 BSC E2 4 00 BSC aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 eee 0 10 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components ...

Page 75: ...50 f 0 35 P1 3 20 P2 3 20 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 All feature sizes shown are at Maximum Material Condition MMC and a card fabrication tolerance of 0 05 mm is assumed 3 Dimensioning and Tolerancing is per the ANSI Y14 5M 1994 specification 4 This land pattern design is based on the IPC 7351 guidelines ...

Page 76: ...tencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pins 4 A 2 x 2 array of 1 25 mm square openings on 1 60 mm pitch should be used for the center ground pad 6 1 3 LGA 92 Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The r...

Page 77: ...ackage Specifications Figure 6 4 TQFP 80 Package Drawing Table 6 4 TQFP 80 Package Dimensions Dimension Min Nominal Max A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 b 0 17 0 20 0 27 c 0 09 0 20 D 14 00 BSC D1 12 00 BSC e 0 50 BSC E 14 00 BSC E1 12 00 BSC ...

Page 78: ...hown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This package outline conforms to JEDEC MS 026 variant ADD 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Table 6 4 TQFP 80 Package Dimensions Continued Dimension Min Nominal Max ...

Page 79: ...m Table 6 5 TQFP 80 Landing Diagram Dimensions Dimension Min Max C1 13 30 13 40 C2 13 30 13 40 E 0 50 BSC X 0 20 0 30 Y 1 40 1 50 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 This land pattern design is based on the IPC 7351 guidelines ...

Page 80: ...ign 1 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all pads 6 2 3 TQFP 80 Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J ...

Page 81: ...30 D 9 00 BSC D2 3 95 4 10 4 25 e 0 50 BSC E 9 00 BSC E2 3 95 4 10 4 25 L 0 30 0 40 0 50 aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 eee 0 05 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This package outline conforms to JEDEC MO 220 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Bod...

Page 82: ... mm C1 8 90 C2 8 90 E 0 50 X1 0 30 Y1 0 85 X2 4 25 Y2 4 25 Notes 1 All dimensions shown are in millimeters mm 2 This Land Pattern Design is based on the IPC 7351 guidelines 3 All dimensions shown are at Maximum Material Condition MMC Least Material Condition LMC is calculated based on a Fabrication Allowance of 0 05 mm ...

Page 83: ...shed stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all pads 4 A 3x3 array of 1 0 mm square openings on a 1 5 mm pitch should be used for the center ground pad 6 3 3 QFN 64 Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recomme...

Page 84: ...ications Figure 6 8 TQFP 64 Package Drawing Table 6 8 TQFP 64 Package Dimensions Dimension Min Nominal Max A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 b 0 17 0 22 0 27 c 0 09 0 20 D 12 00 BSC D1 10 00 BSC e 0 50 BSC E 12 00 BSC E1 10 00 BSC L 0 45 0 60 0 75 0 3 5 7 ...

Page 85: ... mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This package outline conforms to JEDEC MS 026 variant ACD 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Body Components Table 6 8 TQFP 64 Package Dimensions Continued Dimension Min Nominal Max ...

Page 86: ...m Table 6 9 TQFP 64 Landing Diagram Dimensions Dimension Min Max C1 11 30 11 40 C2 11 30 11 40 E 0 50 BSC X 0 20 0 30 Y 1 40 1 50 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 This land pattern design is based on the IPC 7351 guidelines ...

Page 87: ...ign 1 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all pads 6 4 3 TQFP 64 Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recommended card reflow profile is per the JEDEC IPC J ...

Page 88: ...0 30 D 6 00 BSC D2 4 35 4 50 4 65 e 0 50 BSC E 6 00 BSC E2 4 35 4 5 4 65 L 0 30 0 40 0 50 aaa 0 10 bbb 0 10 ccc 0 08 ddd 0 10 eee 0 05 Notes 1 All dimensions shown are in millimeters mm unless otherwise noted 2 Dimensioning and Tolerancing per ANSI Y14 5M 1994 3 This package outline conforms to JEDEC MO 220 4 Recommended card reflow profile is per the JEDEC IPC J STD 020 specification for Small Bo...

Page 89: ...n mm C1 5 90 C2 5 90 E 0 50 X1 0 30 Y1 0 85 X2 4 65 Y2 4 65 Notes 1 All dimensions shown are in millimeters mm 2 This Land Pattern Design is based on the IPC 7351 guidelines 3 All dimensions shown are at Maximum Material Condition MMC Least Material Condition LMC is calculated based on a Fabrication Allowance of 0 05 mm ...

Page 90: ...shed stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all pads 4 A 3x3 array of 1 1 mm square openings on a 1 6 mm pitch should be used for the center ground pad 6 5 3 QFN 40 Card Assembly 1 A No Clean Type 3 solder paste is recommended 2 The recomme...

Page 91: ... datasheet is revised 7 1 Revision Identification The Lot ID Code on the top side of the device package can be used for decoding device revision information Figures 7 1 7 2 7 3 and 7 4 show how to find the Lot ID Code on the top side of the device package In addition firmware can determine the revision of the device by checking the DEVICEID registers Figure 7 1 LGA 92 SiM3U1x7 Revision Information...

Page 92: ...rmware using the rising and falling edge flags to make decisions may see a false trigger of the comparator if the output of the comparator is high during a debug session This does not impact the non debug operation of the device 7 2 3 Workaround There is not a system agnostic workaround for this issue 7 2 4 Resolution This issue exists on Revision A and Revision B devices It may be corrected in a ...

Page 93: ...SiM3U1xx Preliminary Rev 0 8 93 NOTES ...

Page 94: ...icon Laboratories assumes no responsibility for the functioning of undescribed fea tures or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application ...