SiRFatlasV
Hardware Design Guide
January, 2010
SiRF Design Guide
– Proprietary and Confidential
1
SiRFatlasV
F
EATURE
L
IST
Computing Cores
500 MHz ARM11 with 16KB D-cache and I-cache, 16KB D-TCM and I-TCM
250 MHz Enhanced DSP for GPS
Low Power advanced 65nm process
Memory Subsyste m
64-bit 250MHz
system bus with 16 DMA channels
1.8V 16-bit Mobile-DDR support
1.8V 16-bit
DDR2 support
Advanced Autonomous GPS
64 c
hannels
-161 dBm sensitivity
SiRF Always-Fix technology
Able
to acquire and track Galileo signals on all channels
Display, Graphics, and Multimedia
Capable of supporting up to 800x480 at 16 bits color
Support RGB565 or 16bit CPU I/F TFT LCD panel
Hardware VPP (Video post processor) for de-interlace, scalar, color space conversion
Two hardware overlay layers
Peripherals and Interfaces
Power Integration
Two switching DC/DC for core (700mA) and DRAM (500mA)
One high PSRR and low noise 150mA LDO for I/O and peripheral
One high PSRR and low noise 100mA LDO for analog power
One high PSRR and low noise 10mA LDO for PLL
One high PSRR and low noise 50mA LDO for RF
Audio Integration
One
mono differential audio output with 93db SNR and 70db THD (“A” weighted)
One stereo audio
output with 93db SNR and 70db THD (“A” weighted) Connectivity
One dedicated AC97/I
2
S interface
Two dedicated UART ports
Two USP ports for PCM, DSP, I
2
S, SPI, UART mode
Two I
2
C ports
12-bit ADC with 4-wire touch screen controller and 3 channel analog input, stream measurement
mode for low cost audio input