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ATCA-F125 (6873M Artwork) Installation and Use (6806800J94N)
Functional Description
Functional Description
4.10.1
BCM5709S Dual Gigabit Ethernet MAC/PHY
The Broadcom BCM5709S is a PCI Express based single-chip dual Gigabit Ethernet MAC
controller with integrated PHY and SerDes cores. This device supports a 4x PCI Express
v1.1/v2.0 compliant interface to the host processor in the AMC bay. The dual MAC/PHY
supports either 1Gb SERDES or triple speed copper interfaces. This device will be
configured to use the SERDES interfaces. Controller 0 is routed to the AMC-Base cross
connect mux. Controller 1 is routed to the AMC-Fabric cross connect mux.
Table 4-6
AMC Bay Port Assignments
Connector
Region
Port No. PrAMC Usage
ATCA-F125 Source/Target
Clocking
1
TCLKA
From FPGA Telecom Clock logic
2
TCLKB
From FPGA Telecom Clock logic
3
TCLKC
From FPGA Telecom Clock logic
4
TCLKD
From FPGA Telecom Clock logic
5
FCLKA
From PCIE 100 MHz differential
clock distribution
Common Options
0
Gigabit Ethernet Link 0
To BCM56334
1
Gigabit Ethernet Link 1
To BCM56820 using mux
2
SATA Link 0
To SATA HDD Mux
3
SATA Link 1
Unused
Fat Pipes
4
PCI-Express Lane 0
To BCM5709S x4 PCIE
5
PCI-Express Lane 1
6
PCI-Express Lane 2
7
PCI-Express Lane 3
8
PCIE/XAUI/SGMII
To RTM or FIX XAUI or FIX SGMII
9
PCIE/XAUI/SGMII
10
PCIE/XAUI/SGMII
To RTM or FIX XAUI
11
PCIE/XAUI/SGMII
Extended Options
12
Unused
Unused
13-20
Unused
Unused
