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Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic

 with PECI

Revision 0.2 (02-11-09)

4

SMSC SCH5027E

PRODUCT PREVIEW

 

Block Diagram

Figure 1 SCH5027E Block Diagram

LEDs

LED2

*

LED1

*

Internal Bus

(Data, Address, and Control lines)

Power Mgmt

IO_PME_S5*

IO_SMI*

GP1[0:4]*, GP21*,GP22*

GP27*, GP32*,GP33*

GP36*, GP37* , GP4[0,2,3]*

GP5[0:1]*, GP6[0:1]*

Note 1: 

This diagram does not show power and  ground 

connections.  

Note 2:  

Signal names followed by an asterisk (*) are 

located on multifunction pins.  This diagram is designed to 
show the various functions available on the chip and 
should not be used as a pin layout .

CLOCK 

GEN

CLK32

CLOCKI

WDT

32 byte 

Security

 Key 

Register

nDSR1, nDTR1
nDCD1, nRI1

Power Control 

and Recovery

`

SLP_S3#, SLP_S5# 

PWRGD_CPU , 
PWRGD_3V
SLP_S3DEL#
PS_ON#
nRSMRST

nFPRST, PB_IN#
PWRGD_PS

nH

W

M

_I

N

T

VR

E

F

PE

C

I_REQUE

S

T

#*

PE

C

I

RE

A

D

Y

VI

D

3

/P

W

M

A

VI

D

4

/P

W

M

B

VI

D

5 /

 F

ANTA

C

H3

V1

_I

N

V2

_I

N

VC

C

P

_I

N

 +

2.5

V

T

R

_I

N

Rem

o

te

1

-

Re

m

o

te

1+

Rem

o

te

2

-

Re

m

o

te

2+

PW

M

1/

x

T

est

 O

u

t

PW

M

2

PWM

3

/ A

DDR

_

E

N#

F

ANTA

C

H1

F

ANTA

C

H2

FA

NTA

C

H

4

/ A

DDR

_

SEL

P

W

MA

*, PWMB

*

FAN

T

ACHA

*

FAN

T

ACHB

*

S

M

B

u

s

SD

A

SC

L

K

Hardware

Monitor

General 

Purpose 

I/O

IO_PME_S3*

VC

C

VT

R

Vb

at

SL

P

_S

3#

SL

P

_S

5#

HWN

_

IN

T

14.

31

8M

hz

96 M

h

z

PC

I_

RESET#

WDT*

SER_IRQ

LAD[3:0]

LFrame#

LDRQ#

PCI_RESET#

PCI_CLK

LPC 

Bus Interface

SERIAL

IRQ

SMbus 

Isola-

tion

Switch

 SDA1

 SCLK1

 SDA2

 SCLK2

SMSC 

Proprietary 

82077 

Compatible 

Floppydisk 

Controller with 

Digital Data 

Separator & 

Write Precom-

pensation

nRDATA, nWDATA

nDIR, nSTEP

nMTR0, nTRK0, InNDEX

DRVDEN0*, nWRTPRT

nWGATE, nHDSEL

nDSKCHG, nDS0,

High-Speed

16550A

UART

PORT 1

TXD1*, RXD1

nCTS1, nRTS1* 

Multi-Mode 

Parallel Port

with 

ChiProtect

TM

/

FDC MUX

(see LPC47B27x)

PD[7,0]

BUSY, SLCT, PE, 
nERROR, nACK
nSTROBE, nINIT, 
nSLCTIN, nALF

Intruder 

Detection

nINTRD_IN

Keyboard/Mouse

8042

controller

KCLK*, KDAT*

MCLK*, MDAT*
A20M*
nKBDRST*

PCI  Reset 

Outputs

nPCIRST_OUT[1:4]*

nIDE_RSTDRV*

High-Speed

16550A

UART

PORT 2

TXD2 (IRTX)*,
RXD2 (IRRX)*

DSR2*, DTR2*

DCD2*, RI2*

CTS2*, RTS2 *

Summary of Contents for SCH5027E

Page 1: ... UARTs with Send Receive 16 Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry 480 Address and 15 IRQ Options Infrared Port Multiprotocol Infrared Interface IrDA 1 0 Compliant SHARP ASK IR 480 Addresses Up to 15 IRQ Multi Mode Parallel Port with ChiProtect Standard Mode IBM PC XT PC AT and PS 2 Compatible Bi directional Parallel Port Enhanced Parallel P...

Page 2: ...ustomer Copies of this document or other SMSC literature as well as the Terms of Sale Agreement may be obtained by visiting SMSC s website at http www smsc com SMSC is a registered trademark of Standard Microsystems Corporation SMSC Product names and company names are the trademarks of their respective holders SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES INCLUDING WITHOUT LIMITATION ANY AND ...

Page 3: ...and FANTACH conditions The hardware monitoring block of the SCH5027E is accessible via the System Management Bus SMBus The same interrupt event reported on the nHWM_INT pin also creates PME wakeup events and speaker alarm annunciation The SCH5027E also allows for a two or three piece linear fan function The Motherboard Glue logic includes various power management and system logic including generat...

Page 4: ...VID4 PWMB VID5 FANTACH3 V1_IN V2_IN VCCP_IN 2 5VTR_IN Remote1 Remote1 Remote2 Remote2 PWM1 xTest Out PWM2 PWM3 ADDR_EN FANTACH1 FANTACH2 FANTACH4 ADDR_SEL PWMA PWMB FANTACHA FANTACHB S M B u s SDA SCLK Hardware Monitor General Purpose I O IO_PME_S3 VCC VTR Vbat SLP_S3 SLP_S5 HWN_INT 14 318Mhz 96 Mhz PCI_RESET WDT SER_IRQ LAD 3 0 LFrame LDRQ PCI_RESET PCI_CLK LPC Bus Interface SERIAL IRQ SMbus Isol...

Page 5: ...on for foot length L measured at the gauge plane 0 25 mm above the seating plane 7 Details of pin 1 identifier are optional but must be located within the zone indicated Table 1 128 Pin QFP Package Parameters MIN NOMINAL MAX REMARKS A 3 4 Overall Package Height A1 0 05 0 5 Standoff A2 2 55 3 05 Body Thickness D 23 00 23 20 23 40 X Span D1 19 90 20 00 20 10 X body Size E 17 00 17 20 17 40 Y Span E1...

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