3-8
Computer Group Literature Center Web Site
Functional Description
3
Refer to
for a map of the FPGA register set.
Status Register
The Status Register (STAT) is a read only register. Reads of the unused
bits produce indeterminate values. Writes have no effect. The Temp
Alarm, SMB Alert, Alarm B, and Alarm A are all latched when active. You
must initiate a write to the LEN register to clear the latched signals. Refer
to
.
Table 3-5. Map of the FPGA register set
DEVICE 00h
SYSTEM
DEVICE 10h
LAN A Ctrl
DEVICE 11h
LAN B Ctrl
DEVICE 14h
FLASH Ctrl
00 Status
01 LAN A
01 LAN B
01 FLASH
03 Watchdog
04 INT Sel
05 SCI Mask
06 NMI Mask
07 IRQ Mask
08 Alm Mask
09 FLT Latch
0B Power On
0F DEV SEL
0F DEV SEL
0F DEV SEL
0F DEV SEL
Table 3-6. Bit descriptions for the STAT register
7 (most
significant
bit)
6
5
4
3
2
1
0 (least
significant
bit)
ALARM
FAL-
DEG-
ENUM-
LM81
ALARM A
(NMI)
LM81
ALARM B
(SMI)
SMB
ALERT
CPU
TEMP
ALARM
Solution Systems Technologies Inc.
720-565-5995 | info@solusys.com | www.solusys.com
Solution Systems Technologies Inc.
720-565-5995 | info@solusys.com | www.solusys.com