PQM-700 Operating Manual
28
measurement error can be described with the following relationship
1
:
Power measurement erro
r ≈ phase error (in radians) × tan(φ) × 100 %
where
tan(φ)
is the tangent of the angle between the fundamental voltage and current components.
From the formula, it can be concluded that the measurement errors are increasing as the displace-
ment power facto
r is decreasing; for example, at the phase error of only 0.1° and cosφ = 0.5, the
error is 0.3%. Anyway, for the power measurements to be accurate, the phase coincidence of volt-
age and current circuits must be the highest possible.
4.3
Signal sampling
The signal is sampled simultaneously in all eight channels at the frequency synchronized with
the frequency of power supply voltage in the reference channel. This frequency equals 10.24 kHz
for the 50 Hz and 60 Hz mains systems.
Each period includes then about 205 samples for 50 Hz systems, and about 170 samples for
60 Hz systems. A 16-bit analog-to-digital converter has been used which ensures 64-fold over-
sampling.
3-decibel channels attenuation has been specified for frequency of about 12 kHz, and the am-
plitude error for the 2.4 kHz maximum usable frequency (i.e. the frequency of 40th harmonics in the
60 Hz system) is about 0.3
dB. The phase shift for this frequency is below 15°. Attenuation in the
stop band is above 75 dB.
Please note that for correct measurements of phase shift between the voltage harmonics in
relation to current harmonics and power of these harmonics, the important factor is not absolute
phase shift in relation to the basic frequency, but the phase coincidence of voltage and current
circuits. The highest phase difference error for f = 2.4
kHz is maximum 15°. Such error is decreasing
with the decreasing frequency. Also an additional error caused by used clamps are transducers
must be considered when estimating the measurement errors for harmonics power measurements.
4.4
PLL synchronization
The sampling frequency synchronization has been implemented by hardware. After passing
through the input circuits, the voltage signal is sent to a band-pass filter which is to reduce the
harmonics level and pass only the voltage fundamental component. Then, the signal is sent to the
phase locked loop circuits as a reference signal. The PLL system generates the frequency which is
a multiple of the reference frequency necessary for clocking of the analog-to-digital converter.
The necessity to use the phase locked loop system results directly from the requirements of the
IEC 61000-4-7 standard which describes the methodology and admissible errors during the meas-
urements of harmonic components. The standard requires that the measuring window, being the
basis for a single measurement and evaluation of harmonics content, is equal to the duration of 10
periods in the 50 Hz mains systems and 12 periods in the 60 Hz systems. In both cases, it corre-
sponds to about 200 ms. Because the mains frequency can be subject to periodical changes and
fluctuations, the window duration might not equal exactly 200 ms and for the 51 Hz frequency will
be about 196 ms.
The standard also recommends that before the Fourier transform (to separate the spectral com-
ponents), the data are not subject to windowing operation. Absence of frequency synchronization
and allowing the situation in which the FFT is performed on the samples from not the integer number
of periods can lead to spectral leakage. This phenomenon causes that the spectral line of a har-
monic blurs also to a few neighboring interharmonic spectral lines which may lead to loss of data
about actual level and power of the tested spectral line. The use of Hann weighting window, which
reduces the undesirable spectral leakage, has been permitted, but is limited to the situations when
the PLL has lost synchronization.
The IEC 61000-4-7 defines also the required accuracy of the synchronization block: the time
1
“
Current
sensing for energy metering”, William Koon, Analog Devices, Inc
.
Summary of Contents for PQM-700
Page 85: ...85 Notes...
