2-8
BVW-55
IC
74VHCT04MTCX (NS)
TC74HCT04AF (TOSHIBA)
TC74HCT04AF(EL)
TC74VHC04FT(EL) (TOSHIBA)
TC74VHCT04AFT(EL) (TOSHIBA)
A
A
Y =
Y
14
13
V
DD
GND
12
11
10
9
8
7
6
5
4
3
2
1
A
0
1
Y
1
0
0 : LOW LEVEL
1 : HIGH LEVEL
Y =
A
C-MOS HEX INVERTERS
—TOP VIEW—
1
2
3
4
5
6
7
14
13
12
11
10
9
8
GND
V
DD
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
0
1
: LOW LEVEL
: HIGH LEVEL
A
B
A
B
Y
Y =
Y = A • B =
A
+
B
C-MOS QUAD 2-INPUT AND GATES
—TOP VIEW—
74VHCT08MTCX (NS)
SN74HC08APW-E05 (TI)
SN74HCT08APW-E05
SN74HCT08APW-E20 (TI)
TC74VHC08FT(EL) (TOSHIBA)
1
2
3
4
5
6
7
8
9
10
EN
IN
D1
IN
D2
IN
D3
IN
D4
IN
D5
IN
D6
IN
D7
IN
D8
IN
20
19
18
17
16
15
14
13
12
11
GND
V
DD
Q1
OUT
Q2
OUT
Q3
OUT
Q4
OUT
Q5
OUT
Q6
OUT
Q7
OUT
Q8
OUT
CK
IN
2
3
4
5
6
7
8
9
11
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
EN
1
EN
0
0
0
1
CK
x
D
1
0
x
x
INPUTS
OUT
Q
1
0
Q
0
HI-Z
EACH FLIP-FLOP
D Q
Q
EN
EN
Q
Q
D
11
1
CK
EN
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
D1
Q1 D2
Q2 D3
Q3 D4
Q4 D5
Q5 D6
Q6 D7
Q7 D8
Q8
C-MOS 3-STATE D-TYPE EDGE-TRIGGERED FLIP-FLOP
—TOP VIEW—
0
1
x
HI-Z
Q
0
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
: HIGH IMPEDANCE
: NONSTABLE
74VHCT574MTCX (NS)
SN74HC574APW-E05
SN74HC574APW-E20 (TI)
TC74VHC574FT(EL) (TOSHIBA)
1
2
3
4
8
7
6
5
V
EE
V
CC
_ +
_ +
DUAL OPERATIONAL AMPLIFIERS
(SINGLE-SUPPLY TYPE)
—TOP VIEW—
AD828AR (AD)
AD828AR-REEL
NJM2119M(TE1) (JRC)
NJM2904V(TE2) (JRC)
NJM3404AV (JRC)
NJM3404AV(TE2)
NJU7062M(TE2) (JRC)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CKS
MCLK
PD
BICK
SDATA
LRCK
SMUTE
DFS
DEM0
DEM1
DZFL
DZFR
VREF
AOUTL
+
AOUTL
_
AOUTR
+
AOUTR
_
DIF2
DIF1
DIF0
DV
DD
AV
DD
AGND
19
18
17
16
24
23
13
14
15
8
6
7
10
9
11
12
3
4
21
5
DIF0
DIF1
DIF2
LRCK
BICK
SDATA
DFS
SMUTE
DEM0
DEM1
CKS
MLCK
VREF
PD
AOUTL
+
AOUTL
_
AOUTR
+
AOUTR
_
DZFL
DZFR
INPUT
BICK
CKS
DEM0, DEM1
DFS
DIF0 - DIF2
LRCK
MCLK
PD
SDATA
SMUTE
VREF
: AUDIO SERIAL DATA CLOCK
: MASTER CLOCK SELECT
: DE-EMPHASIS FREQUENCY SELECT
: DOUBLE SPEED SAMPLING MODE
: DIGITAL INPUT FORMAT
: L/R CLOCK
: MASTER CLOCK
: POWER DOWN MODE
: AUDIO SERIAL DATA
: SOFT MUTE
: VOLTAGE REFERENCE
OUTPUT
AOUTL
_
AOUTL
+
AOUTR
_
AOUTR
+
DZFL
DZFR
: L CHANNEL NEGATIVE ANALOG SIGNAL
: L CHANNEL POSITIVE ANALOG SIGNAL
: R CHANNEL NEGATIVE ANALOG SIGNAL
: R CHANNEL POSITIVE ANALOG SIGNAL
: L CHANNEL ZERO INPUT DETECT
: R CHANNEL ZERO INPUT DETECT
C-MOS 98 kHz SAMPLING 24-BIT
T
∑
D/A CONVERTER
—TOP VIEW—
DGND
8
6
7
13
19
18
24
17
16
AOUTL
+
AOUTL
_
DZFL
AOUTR
+
AOUTR
_
LRCK
BICK
SDATA
9
SMUTE
SOFT
MUTE
x
1
x
2
11
12
4
3
DEM0
DEM1
MCLK
CKS
DIF0
15
DIF2
SERIAL
INPUT
INTERFACE
DE-EMPHASIS
CONTROL
8
x
INTERPOLATOR
8
x
INTERPOLATOR
T
∑
MODULATOR
T
∑
MODULATOR
CLOCK
DIVIDER
SCF
SCF
POWER
DOWN
21
VREF
5
PD
23
DZFR
14
DIF1
10
DFS
: 256 fs/384 fs
: 128 fs/198 fs
AK4324-VF-E2 (ASAHI)
Summary of Contents for BVW-55
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