2-28
BVW-55
IC
OUTPUT
ACP
ACP O
AD WCK
ADSW
AOP O
AZ1
BOP O
CH
CP
CS
DIAG
DO 0 - 7
DOP O
ER 1
ER 2
EOP O
GB OUT
GCK
IOCK
PB SYNC
PBV/CCP
SH OUT
SH2
TEST OUT0, 1
TOUT
VOT 3
WCP
WZ
; ADVACE WRITE CLAMP PULSE
; COMPARATOR
; WRITE CLOCK FOR A/D CONVERTER
; A/D SWITCH (CONNECT TO PIN 40)
; A SAWTOOTH WAVE FOR PB SYNC NOISE REJECT
; ADVANCE WRITE ZERO
; A SAWTOOTH WAVE FOR PLL PHASE COMPARATE
; COUNT H
; CLAMP PULSE FOR IMPACT ERROR COMPENSATION
; CHIP SELECT FOR IMPACT ERROR A/D CONVERTR
; DIAGNOSTIC
; IMPACT ERROR COMPENSATION DATA (8 BITS)
; PLL ERROR AMP OUTPUT 2
; PLL ERROR
; AFC ERROR
; PLL ERROR AMP OUTPUT 1
; GUARD BAND
; GATED WRITE CLOCK
; CLOCK FOR IMPACT ERROR A/D CONVERTER
; PB SYNC
; Y MODE; PB V
C MODE; CENTER WRITE CLAMP PULSE FOR CTDM SIGNAL
; SAMPLING & HOLD PULSE
; SAMPLING PULSE FOR AFC
; FOR TEST
; FOR TEST
; H BLANKING
; WRITE CLAMP PULSE
; WRITE ZERO
CXD2221Q (SONY)
80
75
70
65
60
55
51
50
45
40
35
31
81
85
90
95
100
D GND
A V
DD
A V
DD
D V
DD
A GND
1
5
10
15
20
25
30
D GND
A GND
A V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
O
I
I
I
I
O
I
I
—
I
O
I
I
I
O
O
O
I
I
I
PB SYNC
H BLKG
VIN 4
REF 3
VIN 3
VOT 3
AI 3
ACPI
A GND
ACP X
ACP O
MD1
COUNT H
BOP X
BOP O
ER 1
ER 2
MD2
CLR
Y/C
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
—
I
I
O
I
I
I
I
I
I
O
—
I
I
I
O
I
I
O
I
A V
DD
COP I
COP X
COP O
SWP
TST
WRITE V
TEST0
TEST1
EOP X
EOP O
A GND
AI 2
DOP I
DOP X
DOP O
VCO I
VCO EN
DIAG
DSEL
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
O
O
O
O
I
I
I
—
I
O
I
I
I
I
I
I
I
I
—
I
ADSW
GB OUT
TEST OUT0
TEST OUT1
TEST IN2
TEST IN3
PLL RESET
D V
DD
DDF
SH OUT
PB/EE
NOSIG
FR30
R20
FBID
DO
GBI
SHW
D GND
GH
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
O
O
O
O
O
I
O
O
O
—
O
O
O
I
I
I
I
O
O
O
—
O
O
O
O
O
O
O
I
I
I
I
I
I
I
O
—
I
I
WCP
ACP
TOUT
PBV/CCP
AZ1
WZ
WCK
GCK
AD WCK
AD WCK
D V
DD
CH
SH2
CP
ERR IN
SVLK
SVD
IEC OFF
IOCK
CS
DO 0
D GND
DO 1
DO 2
DO 3
DO 4
DO 5
DO 6
DO 7
CLP TIM
VIN 2
REF 1
REF 2
VIN 1
AOP I
AOP X
AOP O
A V
DD
PB SY
CCP I
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
PIN
No.
C-MOS WRITE CLOCK GENERATORE FOR TBC
—TOP VIEW—
INPUT
ACP I
ACP X
AI 2, 3
AOP I
AOP X
BOP X
CCPI
CLP TIM
CLR
COP I
COP X
COUNT H
DDF
DO
DOP I
DOP X
DSEL
EOP X
ERR IN
FBID
FR30
GBI
GH
H BLKG
IEC OFF
MD1
MD2
NOSIG
PB SY
PB/EE
PLL RESET
R20
REF 1
REF 2
REF 3
SHW
SVD
SVLK
SWP
TEST IN 2, 3
TEST0, 1
TST
VCO EN
VCO I
VIN 1
VIN 2
VIN 3
VIN 4
WCK
WRITE V
Y/C
; COMPARATOR (
+
)
; COMPARATOR (
_
)
; CURRENT SOURCE
; OP AMP A (
+
) (REFERENCE VOLTAGE 0.7 V)
; OP AMP A (
_
)
FOR SAWTOOTH WAVE GENERATION OF PB SYNC NOISE REJECTOR
; OP AMP B (
_
)
FOR SAWTOOTH WAVE GENERATION OF PLL PHASE COMPARATOR
; REFERENCE VOLTAGE (3.8 V)
; CHROMA WRITE CLAMP PULSE TIMING SHIFT
; CLEAR
; OP AMP C (
+
)
; OP AMP C (
_
)
; COUNT H
; DOUBLE-DIFFERENTIAL PULSE
; DROP-OUT PULSE
; REFERENCE VOLTAGE INPUT FOR PLL ERROR AMP
; PLL ERROR AMP INPUT 2
; A/D SELECT (CONNECT TO PIN 41)
; PLL ERROR AMP INPUT 1
; ERROR IN (8 BITS, SERIAL) FROM IMPACT ERROR COMPENSATION
; FAST BIDIREX MODE
; FORWARD/REVERSE 30 OR OVER TIMES MODE
; GUARD BAND (H ; PLL PHASE COMPARATE ENABLE)
; GATED H
; H BLANKING PULSE
; IMPACT ERROR COMPENSATION DISABLE
; MODE SELECT (H ; 525, L ; 625)
; MODE SELECT (H ; 13.5 MHz, L ; 14.3 MHz)
; NO SIGNAL STATUS
; PB SYNC
; MODE SELECT (H ; E-E MODE, L ; PB MODE)
; PLL COUNTER RESET
; FREQUENCY CONTROL OF AD WCK (L ; HALF, H ; NORMAL)
; CLAMP LEVEL IN FOR SYNC SEPARATOR
; SLICE LEVEL IN FOR SYNC SEPARATOR
; CLAMP LEVEL IN FOR H BLANKING GENERATOR
; SWITCHING WINDOW PULSE
; SERVO LOCK VD
; SERVO LOCK SIGNAL
; SWITCHING PULSE
; FOR TEST
; FOR TEST
; FOR TEST
; INTERNAL VCO ENABLE
; INTERNAL VCO ERROR VOLTAGE
; VIDEO IN FOR FINE SYNC SEPARATOR
; VIDEO IN FOR ROUGH SYNC SEPARATOR
; VIDEO IN FOR H BLANKING GENERATOR
; VIDEO IN FOR MIX SYNC SEPARATOR
; WRITE CLOCK
; WRITE V
; MODE SELECT (H ; Y MODE, L ; C MODE)
Summary of Contents for BVW-55
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