2-58
BVW-55
IC
CXD8953Q (SONY)
81
85
90
95
100
50
45
40
35
31
80
75
70
65
60
55
51
1
5
10
15
20
25
30
PIN
No.
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
PIN
No.
I/O
SIGNAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TEST0
V
DD
V
DD
TEST1
TEST2
TEST3
TEST4
TEST5
ICLOCK
IDATA0
IDATA1
IDATA2
IDATA3
GND
GND
GND
IDATA4
IDATA5
IDATA6
IDATA7
O
—
—
O
O
I
I
O
I
I
I
I
I
—
—
—
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
O
I
I
—
—
O
O
O
—
O
O
O
O
O
—
O
—
—
—
O
O
O
O
—
O
—
O
O
O
O
I
I
O
O
O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IDATA8
IDATA9
FORM0
FORM1
AUTO
MODE0
MODE1
MODE2
OTHANC
EDHVLD
DPR
INTR
D7
D6
D5
D4
D3
D2
D1
D0
TEST6
A3
A2
A1
A0
WRITE
READ
CS
TEST7
TEST8
RESET
V
DD
V
DD
TEST9
TEST10
TEST11
GND
TEST12
OCLOCK
ODATA9
ODATA8
ODATA7
V
DD
ODATA6
GND
GND
GND
ODATA5
ODATA4
ODATA3
ODATA2
V
DD
ODATA1
GND
ODATA0
TEST13
OD1
OL525
TEST14
TEST15
APERR
FFERR
ANCER
ANCEDH
ANCEDA
ANCIDH
ANCIDA
V
DD
ANCUES
APEDH
APEDA
GND
APIDH
APIDA
APUES
FFEDH
FFEDA
FFIDH
FFIDA
FFUES
GND
V
DD
GND
GND
GND
V
DD
GND
V
DD
V
DD
V
DD
GND
V
DD
V
DD
GND
GND
GND
C-MOS ERROR DETECTION AND HANDLING
—TOP VIEW—
INPUT
A0 - A3
AUTO
CS
FORM0, FORM1
ICLOCK
IDATA0 - IDATA9
MODE0
MODE1
MODE2
READ
RESET
TEST3, TEST4, TEST6,
TEST8, TEST14, TEST15
WRITE
OUTPUT
ANCER
APERR
DPR
EDHVLB
FFERR
INTR
OCLOCK
OD1
ODATA0 - ODATA9
OL525
OTHANC
TEST0 - TEST2, TEST5,
TEST7, TEST9 - TEST13
INPUT/OUTPUT
ANCEDA
ANCEDH
ANCIDA
ANCIDH
ANCUES
APEDA
APEDH
APIDA
APIDH
APUES
D0 - D7
FFEDA
FFEDH
FFIDA
FFIDH
FFUES
: ADDRESS
: AUTO DETECT
: CHIP SELECT
: VIDEO FORMAT
: CLOCK
: VIDEO DATA
: 1 = Detect each FLAG and calculate CRC.
Add the result and output.
0 = Input each FLAG from outside and calculate CRC.
Add the result and output.
: 1 = If other ANCILLARY DATA existe EDH,
such as AUDIO, no EDH is added.
0 = EDH is added unconditionally.
: MODE SELECT
: READ
: RESET
: TEST
: WRITE
: ANCILLARY DATA ERROR
: ACTIVE PICTURE ERROR
: INPUT SIGNAL DETECT
: ERROR DETECTION & HANDLING CORRESPOND DETECT
: FULL FIELD ERROR
: INTERRUPT
: OUTPUT CLOCK
: D1/D2 FORMAT SELECT
: OUTPUT DATA
: 525/625, 422/4FC FORMAT SELECT
: OTHER ANC DATA DETECT
: TEST
: ANCILLARY EDA FLAG
: ANCILLARY EDH FLAG
: ANCILLARY IDA FLAG
: ANCILLARY IDH FLAG
: ANCILLARY UES FLAG
: ACTIVE PICTURE EDA FLAG
: ACTIVE PICTURE EDH FLAG
: ACTIVE PICTURE IDA FLAG
: ACTIVE PICTURE IDH FLAG
: ACTIVE PICTURE UES FLAG
: CPU DATA
: FULL FIELD EDA FLAG
: FULL FIELD EDH FLAG
: FULL FIELD IDA FLAG
: FULL FIELD IDH FLAG
: FULL FIELD UES FLAG
IDATA0 -
IDATA9
LATCH
10 - 3,
17 - 22
DELAY
FORMAT
DETECT
31
DPR
FORMAT
SELECT
23
FORM0
24
FORM1
25
AUTO
77
OD1
78
OL525
TIMING
GEN
525/625 422/4FC
EAV TRS
29
OTHANC
27
MODE1
51
RESET
28
MODE2
59
OCLOCK
VIDEO0 - 9
TEST3, TEST4,
TEST6, TEST8,
TEST14, TEST15
6, 7, 41,
50, 79, 80
TEST0 - TEST2,
TEST5, TEST7,
TEST9 - TEST13
1, 4, 5, 8, 49,
54-56, 58, 76
ANC CHECK
SUM
&
PARITY
CHECK
AP
CRC
GEN
DELAY
AP
CRC
DATA
DETECT
FF
CRC
GEN
FF
CRC
DATA
DETECT
FLAG
DATA
DETECT
ENABLE
TIMING
INTRRUPT PULSE
ANCILLARY ERROR
ERROR
FLAG
CONVERTER
(EDH
→
EDA)
FLAG DATA
ERROR
DETECT
AP CRC DATA
EDH DATA
ADD TIMING
ERROR
DETECT
FF CRC DATA
MIX
EDH DATA GENERATOR
ANC & EDH HEADER
HEADER
CHECK
SUM
GEN
75, 73,
71 - 68, 64,
63 - 60
ODATA0 -
ODATA9
83
ANCER
81
APERR
82
FFERR
32
INTR
INTERRUPT
MODE
CONT
AP ERROR
FF ERROR
EDH
DATA
INSERT
INTERRUPT
MODE
FLAG
DATA
FLAG
DATA
SELECTOR
FLAG DATA from CPU
(EDH IDH UES)
CRC DATA
ERROR
FLAG DATA from EXT
FLAG DATA to CPU
FLAG DATA to EXT
WRITE
DATA
READ
DATA
SELECT
40 - 33
D0-D7
45 - 42
A0-A3
46
WRITE
48
CS
47
READ
MODE0
26
ANCEDA, ANCEDH,
ANCIDA, ANCIDH,
ANCUES, APEDA,
APEDH, APIDA,
APIDH, APUES,
FFEDA, FFEDH,
FFIDA, FFIDH,
FFUES
84 - 87,
89 - 91,
93 - 100
3FF
000
DID
BNO
DC
3FC
9
ICLOCK
Summary of Contents for BVW-55
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