2-65
BVW-55
IC
IDT79R3041-20PF (IDT)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NC
NC
V
DD
GND
GND
V
DD
V
DD
GND
NC
NC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
NC
NC
V
DD
GND
V
DD
GND
V
DD
GND
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
GND
V
DD
V
DD
GND
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
GND
V
DD
GND
V
DD
NC
NC
C-MOS RISC CPU
—TOP VIEW—
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
—
—
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
NC
NC
A/D (31)
A/D (30)
A/D (29)
A/D (28)
A/D (27)
GND
V
DD
A/D (26)
A/D (25)
A/D (24)
A/D (23)
A/D (22)
A/D (21)
V
DD
GND
A/D (20)
A/D (19)
A/D (18)
A/D (17)
A/D (16)
A/D (15)
NC
NC
PIN
NO.
I/O
SIGNAL
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
—
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
—
—
NC
NC
GND
V
DD
A/D (14)
A/D (13)
A/D (12)
A/D (11)
A/D (10)
A/D (9)
V
DD
GND
A/D (8)
A/D (7)
A/D (6)
A/D (5)
A/D (4)
A/D (3)
GND
V
DD
A/D (2)
A/D (1)
A/D (0)
NC
NC
PIN
NO.
I/O
SIGNAL
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
—
—
O
O
O
—
—
O
O
O
O
O
O
—
—
O
O
I
I
I
I
I
O
—
—
NC
NC
BURST/WRNEAR
ADDR (3)
ADDR (2)
V
DD
GND
DIAG
LAST
ALE
RD
WR
DATAEN
V
DD
GND
SYSCLK
BUSGNT
RESET
BUSERROR
ACK
RDCEN
BUSREQ
MEMSTROBE
NC
NC
PIN
NO.
I/O
SIGNAL
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
—
—
—
—
O
I/O
I/O
I
I
I
I
I
—
—
I
O
O
O
O
I
I
—
—
—
—
NC
NC
V
CC
GND
TC
*
2/
EXTDATAEN
*
1/
IOSTROBE
SINT (0)
SINT (1)
SINT (2)
INT (3)
INT (4)
V
DD
GND
INT (5)
ADDR (0)
ADDR (1)
BE16 (0)
BE16 (1)
TRISTATE
CLK IN
V
DD
GND
NC
NC
PIN
NO.
I/O
SIGNAL
*
1 : SBRCOND (3)
*
2 : SBRCOND (2)
INPUT
ACK
BUSERROR
BUSREQ
CLK IN
INT (3) - INT (5)
RDCEN
RESET
SBRCOND (2), SBRCOND (3)
SINT (0) - SINT (2)
TRISTATE
OUTPUT
ADDR (0) - ADDR (3)
A/D (0) - A/D (3)
A/D (4) - A/D (31)
ALE
BE16 (0), BE16 (1)
BURST
BUSGNT
DATAEN
DIAG
EXT DATA EN
IO STROBE
LAST
MEMSTROBE
RD
SYSCLK
TC
WR
WRNEAR
INPUT/OUTPUT
A/D (0) - A/D (31)
: ACKNOWLEDGE
: BUS ERROR
: DMA ARBITER BUS REQUEST
: MASTER CLOCK
: PROCESSOR INTERRUPT 3 - 5
: READ BUFFER CLOCK ENABLE
: MASTER PROCESSOR RESET
: BRANCH CONDITION PORT
: PROCESSOR INTERRUPT 0 - 2
: TRI-STATE
: LOW ADDRESS 0 - 3
: BYTE ENABLE STROBES 0 - 3 FOR 32-BIT BUS/DATA 0 - 3
: HIGH-ORDER ADDRESS 4 - 31/DATA 4 - 31
: ADDRESS LATCH ENABLE
: BYTE ENABLE STROBES FOR
16-BIT MEMORY PORT 0, 1
: BURST TRANSFER
: DMA ARBITER BUS GRANT
: DATA ENABLE
: DIAGNOSTIC
: EXTENDED DATA ENABLE
: IO STROBE
: LAST DATUM IN MINI BURST
: MEMORY STROBE
: READ
: SYSTEM REFERENCE CLOCK
: TERMINAL COUNT
: WRITE
: WRITE NEAR
: ADDRESS LATCH ENABLE
CLOCK
GENERATOR
UNIT
MASTER PIPELINE CONTROL
GENERAL REGISTERS
(32
x
32)
INTEGER
CPU CORE
ALU
SHIFTER
MULTIPLY/DIVIDE
ADDRESS ADDER
PC CONTROL
EXCEPTION/CONTROL
REGISTERS
BUS INTERFACE
REGISTERS
COUNTER
REGISTERS
PORT SIZE
REGISTER
VIRTUAL ADDRESS
INSTRUCTION
CACHE
2KB
DATA
CACHE
512B
DATA BUS
PHYSICAL ADDRESS BUS
R3051 SUPERSET
BUS INTERFACE UNIT
48 - 46, 43 - 38,
35 - 30, 23 - 18,
15 - 10, 7 - 3
A/D (0) - A/D (31)
BUSREQ,
BUSGNT
SYSCLK
RD, WR
61, 62
66
72, 67
32
80
83 - 87, 90
SINT (0) - SINT (2)
INT (3) - INT (5)
CLK IN
96
SYSTEM CONTROL
COPROCESSOR
TC
32
DATA
UNPACK
UNIT
4-DEEP
WRITE
BUFFER
DATA
PACK
UNIT
DMA
ARBITER
BIU
CONTROL
4-DEEP
READ
BUFFER
TIMING/
INTERFACE
CONTROL
SBRCOND (2)
SBRCOND (3)
81, 82
2
32
Summary of Contents for BVW-55
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