— 44 —
7-9. IC BLOCK DIAGRAMS
DEFI
EFLG
SBSY
XVSS
XIN
XOUT
XVDD
MUTER
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
MUTEL
N.C
TEST4
TEST2
CLV+
CLV-
V / P
HFL
TES
SLICE LEVEL
CONTROL
µ
COM
INTERFACE
XTAL
TIMING GENERATOR
2K x 8BIT
RAM
RAM ADDRESS
GENERATOR
MUTE
CLV
DIGITAL SERVO
DIGITAL
ATTENUATOR
OVERSAMPLING
DIGITAL FILTER
1BIT DAC
L.P.F
DIGITAL OUT
GENERAL PORT
SYNCRONOUS DETECTION
EFM DEMODULATION
SUBCODE CLASSIFICATION
QCRC
64
1
11
12
13
14
15
16
17
28
18 19 20 21
23 24 25 26 27
29
30
31
32
63
62
61
60
59 58 57 56 55 54 53 52
51
50
49
48
47
45
46
44
42
43
33
34
41
40
39
38
37
36
35
22
TEST1
CS
TEST5
RES
TEST1
16M
4.2M
COCK
COIN
SQOUT
RWC
WRQ
FSX
SBCK
SFSY
PW
EMPH
CF2
DOUT
TGL
TOFF
TEST3
JP+
JP-
PCK
FSEQ
VDD
CONT1
CONT2
CONT3
CONT4
CONT5
C1, C2
ERROR DETECTION
&
CORRECTION
FLAG PROTCESS
IC102 LC78622E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
VCC1
LDS
LDD
BHI
PHI
LF2
VR
REFI
VCC2
FSS
DRF
CE
DAT
CL
CLK
DEF
FD-
FA
FA-
FE
FE-
SL-
SL+
AGND
SP
SPI
SPG
SP-
SPD
SLEQ
SLD
JP-
NC
TBC
FSC
DGND
SLI
SLC
RFS-
RFSM
CV+
CV-
SLOF
HFL
TES
TOFF
TGL
JP+
FIN2
FINI
E
F
TB
TE-
TE
TESI
SCI
TH
TA
TD-
TD
JR
TO
FD
62
61
60
59
55 54 53 52 51 50
49
48
47
46
45
44
43
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
42
58
57
56
RF DET
I / V
VCA
VCA
LSC
RF AMP
BAL
TE
T. SERVO & T. LOGIC
F. SERVO & F. LOGIC
SPINDLE SERVO
SLED SERVO
µ
-COM
INTERFACE
APC
REF
+ -
+
-
+
-
+
-
+ -
+ -
+ -
- +
+ -
63
IC101 LA9240M
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QQ 376315150
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