CDX-GT590UI/GT595UI
CDX-GT590UI/GT595UI
13
13
4-1. BLOCK DIAGRAM – MAIN Section –
SECTION 4
DIAGRAMS
20
22
11
12
28
8
17
18
3
25
7
19
27
13
24
4
AU_LCH
AU_RCH
TXD(MC_BUS)
RXD(MC_BUS)
WAKE_UP
Z_MUTE
CD_ON
CDM_ON
SYS_RST
EJECT_OK
VBUS_ON
A_ATT
BU_CHECK
MECHA 8.5V
A+3.3V
BU_+3.3V
DR_+6V
R-CH
R-CH
R-CH
R-CH
R-CH
BU+3.3V
AUDIO +8.5V
BU_+3.3V
SERVO+3.3V
R-CH
BU +3.3V
15
D701
ELECTRONIC VOLUME
IC302
J1
(ANTENNA)
PHASE LOCKED LOOP
(PLL)
IC001
L6
FM MIX
L2
CN701
CD
MECHANISM
UNIT
(MG-101Z)
(1/2)
I2C BUS CONTROLLED
POWER AMP/MULTIPLE
VOLTAGE REGULATOR
IC301
SYSTEM CONTROL
IC401 (1/2)
RESET
IC403
CN802
R-CH (FRONT)
R-CH (REAR)
BATT
R-CH
J901
AUX
X1
4MHz
S401
RESET
R-CH
BATT
R-CH (REAR/SUB)
R-CH
AUDIO +8.5V
SERVO+3.3V
MECHA+6V
PANEL+B
7
10
12
11
16
1
9
2
4
3
6
I2C_SCK
I2C_SIO
I2C_SCK
I2C_SIO
I2C_SCK
I2C_SIO
I2C_SCK
I2C_SIO
FL+
FL–
L
R
RL+
RL–
FR+
FR–
RR+
RR–
ANT-REM
BATT
ACC
MUTE
Q102
MUTE DRIVE
Q303,304
ACC DETECT
Q805
MUTE
Q103
5
AMP-REM
REAR/SUB
D306
D308
D309
FU601
B.U+5V
FRONT
R-CH
L
J302
R
-1
-2
-3
-4
AUDIO
OUT
MUTE
Q104
BU+3.3V
BATT
BACK-UP
CHECK
Q802,807,808
D806,807
MECHA +6V
3.3V
6
3
FLASH_W
UART_CLK
7
CLK IN
2
RESET
RX
4
1
5
TX
CN401
FLASH
PROGRAMMING
BU +3.3V
B.U +5V
CD MUTE
Q305
FLASH
PROGRAMMING
BUFFER
Q401,402,701
S
LJQDO
P
DWK
R-CH
LV
RPLWWHG
GXH
WR
VDPH
DV
L-CH.
: AM
: CD
: FM
: BUS AUDIO
: AUX